Bert Simonovich's Design Notes

Innovative Signal Integrity & Backplane Solutions

Twin-rod and Rod-over-plane Transmission Line Geometries

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In my last Design Note on coaxial transmission geometry,  I mentioned it was one of three unique cross-sectional geometries that have exact equations for inductance and capacitance. The other two are twin-rod and rod-over-plane.  All three relationships assume the dielectric material is homogeneous and completely fills the space when there are electric fields.

A common application for twin-rod geometry is twin-lead ribbon cable; once used for RF transmission between antenna and TV sets. With the popularity of cable and satellite TV over the years, twin-lead has given way to coaxial cable due to its superior noise rejection and shielding effectiveness.

If we look at Figure1, we can see the electromagnetic field relationship of a twin-rod geometry when it is driven differentially. As current propagates along one rod, an equal and opposite current flows in the opposite direction along the other.

The right half of Figure 1 shows the magnetic-field loops and direction of rotation around each rod. Only one loop is shown for clarity, but the number of loops is a function of the amount of current and the length of the rods. The counter-rotating  loops of current forms a virtual return at exactly one half of the space between the two rods. We call this a virtual return because if we were to put a conducting plane in the same position, the electromagnetic fields would look exactly the same.

image

Figure 1 Twin-rod geometry showing electromagnetic field relationship.

In his book, “Signal Integrity Simplified”,  Eric Bogatin defines the loop inductance as, “the total number of field line loops around a conductor per amp of current”, and the loop self-inductance as, “the total number of field line loops around a conductor per amp of current in the same loop” . Applying these definitions to the figure, the loop inductance (L) is the inductance between the two rods, and the loop self-inductance (L/2) is the loop self inductance to the virtual return plane; equal to one half the loop inductance.

Likewise, the left half of Figure 1 shows the electric field with a capacitance (C) between the two rods, and twice the capacitance (2C) from each rod to the virtual return plane.

The relationships between capacitance, inductance and impedance of a twin-rod geometry are described by the following equations:

image

Where:

Ctwin = Capacitance between twin-rods – F

Ltwin = Loop Inductance between twin-rods – H

Zdiff = Differential impedance of twin-rods – Ω

Dk = Dielectric constant of material

Len = Length of the rods – inches

r = Radius of the rods – inches

s = Space between the rods – inches

Because the electro-magnetic fields create a virtual return plane at exactly one half of the spacing between the rods, each rod behaves like a single rod-over-plane geometry as illustrated in Figure 2.

image

Figure 2 Electromagnetic fields comparison of Twin-rod (left) vs. Rod-over-plane (right) geometries.

Whenever an AC current carrying conductor is in close proximity to a conducting plane, as is the case for rod-over-plane, some of the magnetic-field lines penetrate it.  When the current changes direction, the associated magnetic-field lines also change direction; causing small voltages to be induced in the plane. These voltages create eddy currents, which in turn produce their own magnetic-fields.

Eddy current-induced magnetic-field line patterns look exactly like magnetic-field lines from an imaginary current  below the plane; located the same distance as the real current  above the plane. This imaginary current is called an image current, and has the same magnitude as the real current; except in the opposite direction [1]. The image current creates associated image magnetic-field lines in the opposite direction of the real field lines. As a result, the real magnetic-field lines are compressed between the rod and the plane. Since the rod-over-plane geometry has only one rod, the loop inductance is the same as the loop self-inductance.

For a twin-rod geometry, the odd mode capacitance is the capacitance of each rod to virtual return plane and is equal to twice the capacitance between rods.

image

 

 

 

 

Likewise, the odd mode inductance is the inductance of each rod to virtual return plane and equal to one half the inductance between rods.

image

 

 

 

The odd mode impedance of each rod is half of the differential impedance, and is equivalent to the rod-over-plane impedance.

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[1] “Signal Integrity Simplified”, Eric Bogatin

Written by Bert Simonovich

March 1, 2011 at 9:41 am

Coaxial Transmission Line Geometry

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The coaxial (coax) transmission line geometry, described by Figure 1, consists of a center conductor; imbedded within a dielectric material; surrounded by a continuous outer conductor; also known as the shield. All share the same geometric center axis; hence the name coaxial. It is common practice to transmit the signal on the center conductor, while the outer conductor provides the  return path  for current back to the source. The shield  is usually grounded at both ends.

image
Figure 1 Example of a coaxial transmission line geometry and the electromagnetic
field patterns with respect to the current through the structure.

As the signal propagates along the transmission line, an electromagnetic field is set up between the outer surface of the center conductor and the inner surface of the shield. As illustrated in red, the electric E-field  pattern sets the capacitance per unit length, and the magnetic H-field, in blue, sets the inductance. For the center conductor, the “X” represents current flowing into the page and the “.” (dots) within the shield ring is current flowing out of the page.

Figure 2 describes the magnetic-field relationship for a coax geometry. As current propagates along the center conductor, concentric magnetic-field lines (blue) are created in the direction as shown following the right hand rule.

imageWhenever an AC current carrying conductor is in close proximity to a conducting plane, some of the magnetic-field lines penetrate it. If this plane totally surrounds the inner conductor, it becomes the outer conductor in a coax geometry, and some of the magnetic-field lines penetrate the entire circumference.  When the current changes direction, the associated magnetic-field lines also change direction, causing small voltages to be induced in the outer conductor. These voltages create eddy currents, which in turn, produce their own magnetic-fields.

Eddy current-induced magnetic-field line patterns look exactly like magnetic-field lines  (grey) from imaginary currents  surrounding the outer conductor. These imaginary currents are referred to as image currents, and have the same magnitude as the real current; except they are in the opposite direction [1]. For simplicity, there are only eight image currents shown. But in reality, there are many more; forming a continuous loop of imaginary currents on  a radius equal to twice the radius of the outer conductor to the center of the circle. The image currents create associated image magnetic-field lines in the opposite direction of the real field lines. As a result, the real magnetic-field lines are compressed and are entirely contained within the outer conductor.

The outer conductor thus forms a shield preventing external magnetic-fields from coupling noise onto the main signal and likewise, prevents its own magnetic field from escaping and coupling to other cables or equipment. This is why it is a popular choice for RF applications.

The nice thing about a coaxial transmission line is you can use equations to calculate the exact inductance and capacitance per unit length. There are only two other geometries that can do the same. They are, twin-rod and rod-over-plane; which I will cover at a later time in separate design notes.

The relationships between capacitance, inductance and impedance can be expressed by the following equations:

image
Where:

Ccoax = Capacitance – F

Lcoax = Inductance – H

Zo = Characteristic Impedance – Ohms

Dk = Effective Dielectric constant

Len = Length of the rods

D1 = Diameter of conductor

D2 = Diameter of shield

The coaxial structure can be flexible or semi-rigid in construction. Flexible coax is used for cable applications; like distributing cable TV or connecting radio transmitters/receivers with their antennas. To achieve its flexibility, the shield is usually braided and is protected by an outer plastic sheathing. Being flexible, the same cable can be reconfigured for different equipment applications.

Semi-rigid coax, in comparison, employs a solid tubular outer shield, which yields 100% RF shielding, and enables the dielectric material and center conductor to maintain a constant spacing; even through bends. If you have ever worked on your automobile brakes, semi-rigid coax resembles the rigid brake lines routed through the chassis to the wheels. Semi-rigid coax is usually used for microwave applications where optimum impedance control is required.  A bending tool is needed to form it to a consistent radius. After initial forming and installation, it is not intended to be flexed or reconfigured.

[1] “Signal Integrity Simplified”, Eric Bogatin

Written by Bert Simonovich

February 22, 2011 at 8:57 pm

PCB Vias – An Overview

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imageVias make electrical connections between layers on a printed circuit board. They can carry signals or power between layers. For backplane designs, the most common form of vias use plated through hole (PTH) technology. They connect the pins of connectors to inner signal layers. A PTH via is formed by drilling a hole through the layers to be connected and then copper plating it.

High Density Interconnects (HDI) is another via technology used to form very small vias where drilling holes, using a conventional drill bit, is impractical. Also known as micro-vias, this technology creates the hole with a laser before plating.

Via Aspect Ratio

Via aspect ratio is defined as the ratio of the circuit board thickness to the smallest unplated drilled hole diameter. It is an important metric you need to be aware of when specifying the minimum via hole size for your design, and designing your stack-up. For example, an unplated via with a drill diameter of 0.020 inches and a board thickness of 0.200, would have an aspect ratio of 10:1. The smaller the aspect ratio, the more consistent the plating is throughout the length of the via. It is desirable to have 2 mil plating thickness for the via walls. Large aspect ratio vias tend to have more plating at each end compared to the middle. This increases the chance of cracked via barrels due to z-axis expansion while soldering.

An aspect ratio of 6:1 pretty much ensures your board can be fabricated anywhere. Most high-end board shops have the capability of fabricating boards with 10:1 aspect ratio; for drill diameters of less than 0.020 inches. Practically, the smallest drill diameter used for a through holed via is 0.013 inches. At 10:1, the maximum board thickness would be 0.130 inches.

For drill diameters larger than 0.020 inches, the max aspect ratio can be anywhere from 15:1 to over 20:1; depending on the board shop. Since backplane via hole size is driven by the compliant pins of the connector, it is best to work with your board shop to determine the maximum board thickness they can fabricate with the minimum finished hole size (FHS) specified in the design.

Via Configurations

The following lists the various via configurations you might expect to find on any multi-layer PCB design:

  • Stub Via
  • Through Via
  • Blind or Micro-via
  • Buried Via
  • Back-drilled Via

Stub Via

imageThe Stub Via is the most common via configuration found in PCBs today. As illustrated, there are two variations; Stub Via A and Stub Via B.

For the Stub Via A example, it shows the through portion starting from the top layer and ending at some inner layer. The stub portion is the remaining portion continuing from the inner layer junction to the bottom layer.

The Stub Via B example shows the through portion  originating from one internal signal layer and terminating on another internal signal layer. In this scenario, there are two stubs. The first stub is from the first internal layer junction to the top layer; the second stub is from the second internal layer junction to the bottom layer.

Through Via

imageThrough vias are the oldest and simplest via configurations originally used in 2-4 layer PCB designs. Since the signals originate and terminate from the outer layers of the PCB, there are no stubs. In multi-layer PCB applications, they are an inexpensive way to eliminate the resonance effects caused by stubs where other mitigation techniques are not practical or are too expensive.

 

Blind/Buried Via

imageBlind and buried vias are just like any other via, except  they do not go all the way through the PCB. A Blind Via connects one or more internal layers to only one external layer. Controlled-depth drilling is used to form the holes prior to plating.

A buried via, on the other hand, is a plated hole which is completely buried within the board. It connects one or more internal layers and does not connect to an external layer. Using buried via technology is costly because the inner layers being interconnected need to be fully fabricated and plated before final lamination of the entire PCB.

A micro-via is a form of blind via. Because the holes are so small (0.006 inches or less), they are formed using lasers, and cannot penetrate more than one or two layers at a time. They are most commonly used in high-density PCB designs like cell phones, or in FPGA and custom ASIC chip packaging.

Back-drilled Via

imageHigh speed point-point serial link based backplanes are often thick structures; due to the system architecture and card-card interconnect requirements. Back-drilling the via stub is common practice on thick PCBs to minimize stub length for bit-rates greater than 3Gb/s.

Back-drilling is a process to remove the stub portion of a PTH via. It is a post-fabrication drilling process where the back-drilled hole is of larger diameter than the original PTH. This technology is often used instead of blind-via technology to remove the stubs of connector vias in very thick high-speed backplane designs. State of the art board fabrication shops are able to back-drill to within 8 mils of the signal layer to keep, so there will always be a small stub portion attached to the via.

Back-drilling is not without limitations. Smaller vias and tighter pitch driven by large pin count BGA packages makes back-drilling impractical in these applications; due to drill bit size and tolerance issues. Fortunately, smaller via diameters limit the maximum PCB thickness due to aspect ratio; thereby limiting the length of the stub to the board thickness. Careful planning the high-speed layers within the stack-up is one way to control stub length.

imageWe worry about stubs in high-speed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot of the channel. If one of these frequency nulls happen to line up at or near the Nyquist frequency of the bit rate, the received eye will be devastated resulting in a high bit-error-rate; even link failure.  A shorter stub length means these resonances will be pushed out further in frequency; ideally past the 5th harmonic of the Nyquist frequency as a rule of thumb.

Rules of thumb, in general, are no substitute for actual modeling and simulation. You should never depend on them to sign-off the final design; but you can use them to gain some intuition before hand. With that in mind, you can estimate the maximum stub length in inches using the following equation:

image

Where:

L Stub_max = maximum stub length in inches.

Dkeff = effective dielectric constant of the material surrounding the via hole structure.

BR = Bit rate in GB/s.

For example, the maximum stub length at 5GB/s should be less than 0.120 inches in FR4 material with a Dkeff of 4.0 to ensure the first resonant frequency null is greater than 5 times the Nyquist frequency of the bit rate. If the stub length is greater than this, it does not mean the design will not work at 5GB/s. Depending on just how much longer it is means there will be less than optimum eye opening at the receiver.

If you know the length of the stub, you can predict the fundamental resonant frequency, using the following equation:

image

Where:

Stub_len = stub length in inches.

fo = fundamental resonant frequency in GHz

So, using the same  Dkeff of 4.0, and stub length of 0.120 inches, we calculated in the above example, the first resonant frequency null would occur at approximately 12.3 GHz. If we assume this is the 5th harmonic, then the Nyquist frequency is approximately 2.5GHz and the bit rate is 5Gb/s; which is where we started.

Written by Bert Simonovich

February 15, 2011 at 1:29 pm

PCB Cross-sectional Geometries

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PCB cross-sectional geometries describe the details of the dielectric substrates, traces and reference planes within a PCB stack-up.  Their physical relationship with one another can then be used to predict the characteristic impedance of the respective traces. There are only three generic cross-sectional geometries with variations within each. They are:

  • Coplanar
  • Microstripline
  • Stripline

Coplanar:

imageCoplanar geometry, or sometimes called coplanar waveguide (CPW), is a signal conductor sandwiched between two coplanar reference conductors or planes. These reference planes are usually ground. The characteristic impedance is controlled by the signal trace width and the gap between it and reference planes. This is a common transmission line structure for RF and microwave designs using single-sided printed circuit board technology. As a rule of thumb, the width of the reference plane on each side of the signal trace should be at least five times the distance between the left and right plane.

Microstrip line:

The microstrip line is the most popular transmission line geometry used in two or four layer printed circuit boards. The characteristic impedance is controlled by the signal trace width, on one side of the substrate, and the thickness of the substrate to the reference plane below it. The embedded microstrip line has the signal trace covered with prepreg or other dielectric material.

Cross section views below showing Microstrip line (left) and embedded microstrip line (right).

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Stripline:

Cross section views below shows an example of single stripline (left) and dual stripline (right) geometries. These are geometries are typically found in multi-layer PCBs of 6 layers or more.  The characteristic impedance is controlled by the trace width, thickness and its proximity to the reference planes above and below.

Single stripline has one signal layer sandwiched between two reference planes. If the signal layer is exactly spaced between the two reference planes, the geometry is called a symmetrical stripline; as opposed to an asymmetrical stripline, where the signal trace is offset from the center of the cross-section.

Dual stripline geometries have two signal layers sandwiched between reference planes, and are mainly used to save layers; caveat is a trace on one layer is routed orthogonal to the trace on the other  to mitigate crosstalk.

image

Differential Pair Geometry:

Differential signaling is when a signal and its complement are transmitted on two separate conductors. These conductors are called a differential pair. In a PCB, both traces are routed together with a constant space between them as edge-coupled or broadside-coupled.

imageEdge-coupled routes the traces side-by-side on the same layer as microstrip or stripline. The advantage is that any noise on the reference plane(s) is common to both traces and thus cancelled at the receiver. Most differential pairs are routed this way.

Broadside-coupled routes one trace exactly over the other on 2 separate layers as dual stripline. Since each trace is more tightly coupled to its adjacent reference plane than the opposite reference plane, any noise on the planes will not be common to both traces and thus, will not be cancelled at the receiver. Because of this, and the fact that it usually results in a thicker PCB, this geometry is rarely used.

Odd-Mode Impedance:

imageConsider a pair of equal width microstrip line traces, labeled 1 and 2, with a constant spacing between them. Each individual trace, when driven in isolation, will have a characteristic impedance Zo, defined by the self-loop inductance and self-capacitance of the trace with respect to the reference plane.

When a pair of traces are driven differentially, the mode of propagation is odd. If the spacing between the transmission lines is close, there will be electromagnetic coupling between the two traces. This coupling is defined by the mutual inductance and capacitance.

The proximity of the traces to a reference plane(s) influences the amount of electromagnetic coupling between traces. The closer the traces are to the reference plane(s), the lower the self-loop inductance and stronger self-capacitance to the plane(s); resulting in a lower mutual inductance, and weaker mutual capacitance between traces. The result is a lower differential impedance.

A 2D field solver is usually used to extract the parameters for a given geometry. Once the RLGC parameters are extracted, an L C matrix can be set up as follows:

image

The self-loop inductance and self-capacitance for trace 1 and 2 are L11, C11, L22, C22 respectively. The off diagonal terms in each matrix, L12, L21, C12, C21, are the mutual inductance and mutual capacitance. We use the LC matrix to determine the odd-mode impedance.

The odd-mode impedance is the impedance of one trace, of a differential pair, when driven differentially. It can be calculated by the following equation:

image

Where:

Zodd = odd mode impedance

Lo = self-loop inductance = L11 = L22

Co = self-capacitance = C11 = C22

Lm = mutual inductance = L12 = L21

Cm = mutual capacitance = |C12 |=|C21|

Even Mode Impedance:

When current flows down both traces, of the same polarity, the mode of propagation is even and the coupling is positive. The even mode impedance can be calculated using the following equation:

image

Differential Impedance:

The differential impedance is twice the odd-mode impedance:

image

Average Impedance:

When current flows down two traces randomly, as if they were single-ended, the mode of propagation is a combination of odd and even. The average impedance of each trace is affected by its proximity to the adjacent trace(s); calculated by the following equation:

image

Coupling Coefficient:

The coupling coefficient, Kcc, is a number that conveys the amount of electromagnetic coupling between two traces. Knowing the odd and even mode impedance, Kcc can be calculated by the following equation:

image

Backward Crosstalk Coefficient:

Two traces near one another will couple a portion of its own signal to the other. If we consider one trace as the aggressor, and the other as the victim, the amount of coupled noise travelling backwards on the victim’s trace, opposite to the aggressor’s direction, is called Near-End crosstalk (NEXT) or backwards crosstalk. The amount of coupled noise, travelling in the same direction as the aggressor’s direction, is called Far-End crosstalk (FEXT).

In stripline, there is little to no FEXT, but backwards crosstalk will saturate to a fraction of the amplitude of the aggressor’s voltage for the length of time the traces are coupled. This fraction of the aggressor’s voltage is  called the backward crosstalk coupling coefficient Kb. It is equal to one half of the coupling coefficient Kcc :

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Example:

A 8-9-8 mil differential pair; with 12mil core; 12 mil prepreg; Dk=4; stripline geometry; 1/2 oz copper; has the following R L G C matrix extracted from a 2D field solver:

image

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image

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If the two traces are driven differentially, then the differential impedance is 100 Ohms and there is 13% coupling of the two traces. On the other hand, if the traces are driven single-ended then the characteristic impedance of each trace is 53 Ohms. With 9 mils of space between them, the backward crosstalk is 7%.

If you increase the spacing between traces until Zodd equals approximately Zeven, the coupling will reduce to near zero, and there will be little backward crosstalk. Depending on your design and your noise budget, you may be able to live with a certain amount of backwards crosstalk. The only way to know the spacing between traces to achieve the budget is to plug in the numbers.

Acknowledgment:

I would like to thank my old Nortel colleague, the late Dick Goulette, for sharing these equations many years ago. They have served me well over the years.

Written by Bert Simonovich

February 7, 2011 at 8:52 pm

Backplane High Level Design –the Secret to Success

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In a previous design note on Backplane Architecture and Design, I touched briefly on the concept of a Backplane High Level Design (HLD). In this design note, I will touch on key aspects that go into this process, using a simple fictitious system architecture as a straw-man, to demonstrate the principle.

For any new backplane design, I always recommend starting with a HLD. It helps you capture your thoughts, in an organized manner, and later provides the road map to follow for detailed design of the backplane. It also facilitates concurrent design of the rest of the system by the rest of the design team.

I like to use PowerPoint to capture the HLD information, but any other graphical based tool could be used. Later on in the design process, the drawings in the HLD document are reused in a more formal design specification document.

One of the first things I do, when coming on board a project, is capture the system architecture in a series of functional block diagrams starting from the high-level system block diagram, as shown in Figure 1. This is an example of what you might receive from the system architect at the beginning of a project.

image

Each block diagram details how the respective circuit packs, or other components of the system, interconnect to one another; complete with the number of signal I/Os for that function. For example, Figure 2 below shows the system data path and system control plane block diagrams. It illustrates one possible way of how you would arrange the circuit pack blocks, as they would appear in a shelf, when viewed from the front. Whenever possible, I like to arrange the blocks this way, because it presents a consistent look and feel throughout the documentation; from mechanical views, to connector placement, and route planning.

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Preliminary Route Planning:

After all the functional block diagrams are completed, I usually go through a preliminary route planning exercise. The idea here is to gain some intuition for the final routing strategy, and to uncover any hidden issues that may surface down the road.

This is the most crucial step in any backplane design. Usually at this stage of the project, the system packaging architect is busy developing the shelf packaging concept, and is looking for feedback on connectors and card locations, so he (or she) can complete the common features drawing. The common features drawing defines all the x-y coordinates for all connectors and other mechanical parts on the backplane.

An example of a preliminary routing plan strategy diagram is shown in Figure 3. Each color represents two routing layers; for a total of 6 layers. The heavy black lines represent the high-speed serial link bundles of the data path; routed completely from SW1 and SW4 to LC1-10. The partially routed heavy red and blue lines, follow the exact same route plan as the heavy black lines, except they terminate to the respective color-coded SW cards. The beauty of this comes later, when the actual routing of the backplane takes place. Because the routing is identical, except for the source and destinations, it is a simple copy and paste exercise to replicate the routing on 5 of the 6 layers. The only editing required is at each end of the links. As you can appreciate, this is a huge time saver in completing the final layout!

imageimageWhen the preliminary route plane is complete, a pin-list summary for each circuit pack is compiled using an Excel spreadsheet. The pin-list summarizes the minimum number of pins needed per circuit pack for the function. Later on, it helps to drive the selection and number of connectors.

After completing the preliminary route planning exercise, and pin-list summary, you will gain a sense for:

  • the number of routing layers you will need
  • circuit pack connector signal grouping and partitioning
  • connector selection criteria for density
  • minimum vertical routing channel space needed between connectors
  • worst case topologies for signal integrity analysis

Backplane Connector Selection:

Large companies invest a lot of money and time to qualify a connector family. There is always strong pressure to reuse connectors from one system design to another because of cost. Qualifying a new connector is no trivial task. It takes a significant development effort to model, characterize and test the connectors. If you try to qualify a new connector, at the same time as designing a new system, you run the risk of delaying the overall program if serious issues develop along the way. Sometimes though, reusing the same connector just won’t cut it. For whatever the reason, one day you will be forced to look at other connectors.

Choosing the right connector for any new system is the most important aspect for any backplane design; regardless if it is reuse of a previous connector, or looking at new ones. The connector is the lifeblood of the backplane because it ultimately drives minimum slot pitch and circuit board height. It must be capable of supporting current and next generation high-speed signaling standards, and be robust enough to withstand multiple insertions. Factors such as pin density, pin pitch, pairs per row, overall size, skew, and crosstalk are examples to consider in this process.

Preliminary Stack-up:

In any high-speed serial link architecture, the data plane links are the most critical signals. They are the ones that usually define the total number of routing layers for the final PCB stack-up. When we include 4 layers, for redundant power distribution, to the 6 routing layers, the minimum number of layers for the backplane will be 18 layers as shown in Figure 4.

image

The right half of the figure gives counter-bore details. Another name often used is back-drilling. It is a common procedure done on backplanes to minimize via stubs, which is a killer for multi-gigabit serial links.

Detailed Route Plan:

Usually, around this time in the project schedule, the mechanical architect has put together a preliminary common features drawing, showing the preliminary connector placement. We use this drawing as a template to do a more detailed routing plan analysis.

By studying the preliminary route plan and pin-list, we can come up with a strategy to organize and partition the signals within the connector, and perform a more detailed routing analysis. This process can take a few iterations before it is optimum, but eventually, we end up with a more detailed routing plan as summarized in Figure 5. Each illustration here represents two routing layers per drawing. One layer is for Tx and the other is for Rx.

image

Vertical Routing Channel Analysis:

imageBefore we sign-off on connector placement and route plan though, we need to verify there is enough space between connectors for the vertical routing channels. Otherwise, this may be a deal breaker for the chosen connector; slot pitch; total number of layers; or even the whole system packaging concept. If you do not have enough space here, there will be compromises needed somewhere else to accommodate it. The worst case scenario is having to double the number of layers, or having to choose a higher cost connector.

Signal Integrity Analysis:

Finally preliminary channel simulations must be done before we can sign-off on the backplane physical architecture concept. Now that all the detailed routing analysis is complete, we can easily establish several topologies to analyze.

imageOne example of a worst case reference topology is highlighted in Figure 6. During this stage, we use Manhattan distance to estimate trace lengths.

After procuring the connector models, and developing circuit models to represent the via structures, I like to use Agilent ADS to capture and simulate the topologies. An example of the circuit topology, and simulation results are summarized in Figure 7.

Here, the topology was simulated at 10GB/s. The S-parameters are compared against the IEEE 802.3 10BaseKR spec. You would normally do this for every topology of interest. Later on, during the detailed design phase of the program, I would get 3D models of the vias built and use actual routed lengths from the backplane and circuit pack cards to confirm the design.

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Summary:

Hopefully by now, you can appreciate the backplane architecture and design can be a complex beast to tame, and get right the first time. There are many complex interrelated steps that require the due diligence and meticulous planning to be successful. We have only scratched the surface here. You can download the full white paper titled, “ Backplane Architecture High-Level Design” , from which this design note is based upon, and an example of the PowerPoint HLD document from our website at: www.lamsimenterprises.com.

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If you would like more information on our signal integrity and backplane services, or how we can help you achieve your next high-speed design challenge, email us at: info@lamsimenterprises.com.

Written by Bert Simonovich

January 31, 2011 at 8:56 pm

Via Stub Termination -Brought to You by “The Stubinator”

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Thick backplanes with long via stubs will cause unwanted resonances in the channel insertion loss compared to vias with little or no stub length as shown by the red and green traces in the plot of Figure 1. If these resonances occur at or near the Nyquist frequency of the bit rate, there will be little or no eye-opening left at the receiver.

image

Figure 1 Topology circuit model of 2 differential vias with 30 inches of PCB etch. Insertion loss plot of Long via-no stub (green); short via-long stub (red); stub terminated (blue).  Received eye diagrams after optimized FFE receive equalization at 10GB/s. Modeled and simulated using Agilent ADS.

In a typical backplane application, the signal entering the via structure from the top will travel along the through portion until it reaches the junction of the internal track and stub. At that point, the signal splits with some of the signal continuing along the trace, and the rest continuing along the stub. If the signal was Arnold Schwarzenegger, he would say, “I’ll be back!”. Having done this gig before, he knows that when he reaches the end of the stub it’s like hitting a brick wall; there’s no where to go but back up the stub. Like Arnold, when the signal reaches the end of the stub, it reflects back up the stub. When it arrives at the same junction, a portion combines with the original signal and the rest continues back toward the source. If the round trip delay is half a cycle, the two waves are completely 180 degrees out of phase and there is cancellation of the original signal. The frequency where maximum cancellation occurs is called the ¼ wave resonant frequency, fo. Resonance nulls due to stubs in an insertion loss plot, like the one shown in Figure 1, occurs at the fundamental frequency fo and at every odd harmonic.

If you know the length of the stub (in inches) and the effective dielectric constant Dkeff, the resonant frequency can be predicted with the following formula:

image

 

(1)

 

It is common practice to reduce stub lengths in high-speed backplane designs by back-drilling the stubs as close as possible to the active internal signal layer. This is a complex and costly process involving setting individual drill depths on a per board basis. Special design features must be designed into the artwork to set correct back-drill depth. Furthermore, it is difficult to verify ALL back-drilled holes were drilled correctly. I know of a case where a backplane came back and one via (that they knew of) had a significantly longer stub than was specified. The problem showed up by accident when they were characterizing the channel using a VNA and saw an unexpected resonant null in the SDD21 insertion loss plot. When all was said and done, it turned out there was a glitch in the fabricator’s software controlling the back-drilling process. There is no practical way to find these faults; short of doing VNA measurements on 100% of the back-drilled holes. With hundreds of them in a typical high-speed backplane, the cost would be prohibitive. Thus we have to trust the fabrication process of the vendor(s).

If only there was a way to terminate the stub and get rid of all this back-drilling. Well there just might be a solution. After returning from last year’s DesignCon2010, I was intrigued by a paper presented by Dr. Nicholas Biunno on a new matched terminated stub technology  developed by Sanmina-SCI Corporation. They call this technology MTSviaTM and it allows the embedding of metal thin-film or polymer thick film resistors within a PCB stack-up during its fabrication. I like to call it “The Stubinator”. They developed this technology as an alternative to back-drilling. The beauty of this is you can terminate all the high-speed via stubs on just one resistive layer at the bottom of the PCB.

Of course, for this to work, we need to terminate the vias with a resistance equal to the differential via impedance to be most effective. But how do we determine the via differential impedance without going through a bunch of trial and error builds?  In a DesignCon2009 paper titled, “Practical Analysis of Backplane Vias” I coauthored with Eric Bogatin from Bogatin Enterprises L.L.C., Sanjeev Gupta and Mike Resso from Agilent Technologies, we showed how you can model and simulate differential vias as simple twin-rod transmission line structures using simple transmission line circuit models as shown in Figure 1. You can download a copy of this award-winning paper from my web site at: Lamsimenterprises.com .

After determining  fo (either by measurement of a real structure or through 3D modeling) and solving for Dkeff by rearranging equation (1), the differential via impedance calculated using the following equation:

image

 

(2)

 

 

Where:

s = the center to center spacing of the vias

D = Drill diameter.

Example:

The differential vias used in the model of Figure 1 has the following parameters:

s = 0.059 in.

D = 0.028 in.

stub_length = 0.269 in.

Dkeff = 6.14 by Equation (1) and fo=4.4GHz ;

Zdiff = 66 Ohms by Equation (2).

By adding a 66 Ohm resistor across the bottom of each via stub in the model, the blue trace in the plot shows the stub resonance has completely disappeared at the expense of an additional flat loss of about -10dB. The eye has opened up nicely.

This “Stubinator” technology looks like it could be a promising alternative to back-drilling. It resolves many of the issues and limitations highlighted above. Combined with silicon that can accommodate the additional signal loading, it may extend the life of traditional copper interconnections for next generation of Ethernet standards beyond 10GB/s.

Written by Bert Simonovich

January 27, 2011 at 11:39 pm

Backplane Architecture and Design

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imageAccording to Wiktionary, an Architect is: “A person who plans, devises or contrives the achievement of a desired result.” Because the backplane is the key component in any system architecture, the sooner you consider the backplane’s physical architecture near the beginning of a project, the more successful the project will be. If you think about it in the same way as designing a building, you would never consider building it without first engaging a building architect to plan and oversee the detailed design. Likewise, the backplane architect plans and oversees the physical backplane design before any layout is ever started. He or she works closely with a system-packaging engineer to satisfy the system requirements before any concept becomes final. Sometimes the original system architecture needs revisions due to physical limitations the backplane imposes. This can only be established with due diligence and planning during the high-level design stage.

Unlike other circuit pack designs used in the system, the backplane is much like the keel of a ship of which the rest of the ship’s construction depends on for support and structural integrity throughout its lifetime. Backplanes need to be right the first time so that circuit packs can interoperate together day one and be capable of supporting future system upgrades as technology advances. Once the system has been deployed into the field, it is next to impossible to change the backplane to correct any deficiencies or to upgrade for performance like you can by redesigning the plug-in circuit packs.

imageThe seasoned backplane architect is a unique individual usually tasked to turn the system architect’s ideas and dreams, like the system block diagram example shown to the left, into reality. An often-misunderstood profession, backplane architects wear many hats to accomplish their goals. Often they must juggle the design requirements from many disciplines and decide on the best trade-offs for the final design. They must converse fluently with system architects, mechanical designers, circuit pack designers, connector suppliers, PCB layout designers, ASIC/FPGA and software engineers. They must be organized and meticulous in their documentation and design. But, most importantly, they must have a sound knowledge of mechanical, PCB layout/fabrication, signal integrity, power and EMC issues.

The greatest danger in leaving the backplane design as an afterthought is the connector selection and pin-out definition. If left to system packaging engineers and board designers to define, they may not be optimum for either performance or system cost. Many times system architects and packaging engineers will merely take the total number of signals and choose a connector with the highest pin density per inch without considering PCB routing or signal integrity implications. Inefficient routing of the traces leads to an increase in layer count and results in a thicker board. Thicker boards leads to higher hole aspect ratios and longer vias affecting high speed performance. Additional layer count impacts common equipment cost.

The high-level design stage is where the physical backplane architecture starts to take shape. It uncovers potential layout routing issues and gives you the confidence the design will work the first time. The importance of this stage cannot be overstated.  It primarily drives these key activities:

  • Sanitizes the system architecture.
  • Defines the final selection of appropriate connectors.
  • Defines the connector signal partitioning and circuit pack pin-outs.
  • Provides the routing plan and design rules for layout.
  • Defines the net topologies for signal integrity analysis and link budgeting.
  • Facilitates the mechanical design of shelf and system packaging.
  • Defines the minimum slot pitch for optimum routing channels.
  • Facilitates early circuit pack floor planning and final card size.
  • Facilitates ASIC and FPGA pin selection for optimum routing to backplane connectors.
  • Estimates PCB layer count and board thickness.
  • Establishes an estimate for system cost of goods to support the business case.

imageProper route planning and connector pin-out definition is vital for optimum performance. When done correctly, the final schematic capture and actual PCB layout will flow smoothly with no surprises. As an example, the left half of the figure (labeled HLD Plan) shows a sample of an inner layer high-level design route plan I did using Framemaker as the drawing tool on a design before any schematic was ever captured or pin-outs defined. Everything was planned from the number of layers to how the tracks needed to break out of the connector fields. The right half of the figure is the actual layout done in Cadence Allegro showing the inner layer routing of the artwork.  The due diligence done in the high-level design stage made the actual layout fairly trivial. If you forgo this step, the worst-case scenario is the project will need to be reset to redesign shelf mechanicals or redefine card pin-outs causing delay in meeting time to market objectives and ballooning R&D costs.  It’s a classic case of pay me now or pay me later.

At Lamsim Enterprises Inc., we can help you with these or any other design challenges you may have by providing innovative signal integrity and backplane solutions. Visit us at our web site at: lamsimenterprises.com .

Backplane Architecture Terms and Definitions

The following is a list of common terms and definitions associated with system architecture and backplane design:

Backplane

A backplane is a multi-layered printed circuit board assembly serving as the backbone of a system. Its purpose is to interconnect several printed circuit board assemblies called circuit packs or cards using plug in connectors to form a complete system. These cards plug into one side of the shelf assembly. Usually in mission critical system applications like central office telco or data centers, the backplane is passive meaning it does not contain active semiconductor devices permanently attached as part of the final assembly. Usually only connectors are the only components, but occasionally capacitors and resistors are also used. Active backplanes on the other hand, contains active components and often found in enterprise or consumer grade applications

Midplane

A midplane is similar to a backplane in function except that the circuit packs plug into both sides of the shelf assembly. In these systems, cards with I/O cabling from the faceplate plug into one side of the shelf, while non-I/O circuit pack plug in on the other side. Some midplane architectures have the front card plugged in orthogonally to the rear cards for high speed applications.

Parallel Bus Topologies

Parallel bus topologies carry data words in parallel on multiple traces from card-slot to card-slot across a backplane or from chip to chip on a circuit pack. Up until the late 1990’s, most system architectures used this form of interconnect. Due to signal integrity and timing issues associated with some parallel bus architectures with 10 to 16 card slots, the speed of the bus was limited to 25-66 MHz Two popular industry standard systems still using parallel busses today are CompactPCI and VMEbus.

The main issue with a parallel bus topology is fault tolerance where a single point of failure on the bus can bring down the entire system. Mission critical systems often had to employ redundant busses to guard against single point failures.

As performance demand increased, newer high speed system architectures were designed using serial technology in a point-to-point or point-to-multi-point switched fabric topologies.

Switched Fabric

Switched fabric, or just plain fabric, is the term most popular used in telecommunications and high-speed networks, including InfiniBand, Fiber Channel, PCIe, ATCA and other proprietary fabric based architectures. In these architectures, all data passes through the fabric before continuing to its destination. It offers better total throughput than parallel busses because traffic is spread across multiple physical links. It manages and controls all functions of the network and acts as a repeater for the data flow.

Single Star Topology

Star topologies are one of the most common high-speed serial topologies used in networks today. The advantage is it reduces the chance of network failure by connecting all of the systems to a central node. A failure of a link from any peripheral node to the central node results in the isolation of that peripheral node from all others. As a result, the rest of the systems remain unaffected.

In its simplest form, a single star topology consists of one central hub node interconnected point-to-point to other peripheral nodes resembling a spoke wheel or star configuration. When implemented in a backplane, the central node is usually the switched fabric card and the peripheral nodes are line cards. The fabric card switches messages between the other line cards in the network. The line cards usually have faceplate I/O connectors to connect to other shelves in a network.

The main disadvantage with a single star topology is high dependence of the system on the functioning of the central fabric. Failure of the fabric card can bring down the entire system. Because of this, mission critical systems employ two fabric cards for redundancy in a dual star topology configuration.

Dual Star/Multi-star Topology

The dual star or multi-star topology is similar to the star network topology except it has two or more central hub nodes interconnected point-to-point to other peripheral nodes. When implemented in a backplane application, these central nodes are usually the switched fabric cards and peripheral nodes are the line cards. The additional fabric(s) provides redundancy in mission critical system applications in case of failure, or for upgrading fabric card hardware.

Fully Connected Mesh Topology

A fully connected mesh topology, when applied to a backplane application, does not have one central fabric node(s) as in the case of star topologies. Instead, each line card node connects with all other line card nodes forming a mesh. Its major disadvantage is the number of connections grows significantly with the number of nodes. This requires additional backplane connector pins and layers to interconnect them. Because of this, it is impractical for large systems and only used when there are a small number of cards needing to be interconnected.

Written by Bert Simonovich

January 14, 2011 at 2:51 pm

Fiber Weave Effect Timing Skew

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imageFiber weave effect timing skew is becoming more of an issue as bit rates continue to soar upwards. For signaling rates of 5GB/s and beyond, it can actually ruin your day. For example, the figure on the left shows a 5GB/s received eye is totally closed due to 12.7 inches of fiber weave effect. It was modeled and simulated using Agilent ADS software.

So what is fiber weave effect anyways and why should we be concerned about it? Well, it’s the term commonly used when we want to describe the situation where a fiberglass reinforced dielectric substrate causes timing skew between two or more transmission lines of the same length. Since the dielectric material used in the PCB fabrication process is made up of fiberglass yarns woven into cloth and impregnated with epoxy resin, it becomes non-homogeneous.

imageThe speed at which a signal propagates along a transmission line depends on the surrounding material’s relative permittivity (er), or dielectric constant (Dk). The higher the Dk, the slower the signal propagates along the transmission line. When one trace happens to line up over a bundle of glass yarns for a portion of its length, as illustrated by the top trace in the figure on the left, the propagation delay is different compared to another trace of the same length which lines up over mostly resin. This is known as timing or phase skew and is due to the delta Dk surrounding the respective traces.

Fiber weave effect is a statistical problem. It is not uncommon for PCB designs to have long parallel lengths of track routing without any bends or jogs. This is particularly true in large passive backplane designs. Because the fiber weave pattern tends to run parallel to the x-y axis, any traces running the same way will eventually encounter a situation of worst case timing skew if you build enough boards. This was demonstrated by Intel after compiling more than 58,000 TDR and TDT measurements over two years. In 2007, Jeff Loyer et al presented a DesignCon paper “Fiber Weave Effect: Practical Impact Analysis and Mitigation Strategies” where they published the data and proposed techniques to mitigate the effect of fiber weave skew. They showed statistically it is possible to have a worst case timing skew of approximately 16ps per inch representing a delta Dk of approximately 0.8.

In high speed differential signalling this is an issue because any timing skew between the positive (D+) and negative (D-) data converts some of the differential signal into a common signal component. Ultimately this results in eye closure at the receiver and contributes to EMI radiation.

You can calculate the timing skew using the following equation:

image

Where:

tskew = total timing skew due to fiber weave effect length (sec)

Dkmax= dielectric constant of material predominated by fiberglass.

Dkmin= dielectric constant of material predominated by resin.

c = speed of light = 2.998E+8 m/s (1.18E+10 in/s)

imageA practical methodology you can use to estimate the minimum and maximum values of Dk is by studying the material properties available from PCB laminate suppliers. Consider two extreme styles of fiberglass cloths used in modern PCB laminate construction as illustrated by the figure on the left. The loose weave pattern of 106 has the highest resin content of all the most popular weaves, while the tight weave pattern of 7628 has the lowest. Therefore, you could use the specified values of Dk for cloth styles 106 and 7628 to get Dkmin and Dkmax respectively. Once you have these and apply a tolerance, you can estimate the tskew .

Example:

Assume Fr4 material; one inch of fiber weave effect; Dk106= 3.34(+/-0.05) and Dk7628= 3.97(+/-0.05), then timing skew is calculated as follows:

image

Modern serial link interfaces use differential signalling on a pair of transmission lines of equal length for interconnect between two points. In a DesignCon 2007 paper, “Losses Induced by Asymmetry in Differential Transmission Lines” by Gustavo Blando et al, they showed how intra-pair timing skew between the positive (D+) and negative (D-) data caused an increase in the differential insertion loss profile due to timing induced resonances. These resonances appear as dips in the differential insertion loss profiles of the channel as shown in the following figure:

image

This figure presents the results from an ADS simulation I did recently of a PCIe Gen2 channel running at 5GT/s. The eye diagrams are at the receiver after approximately 30” of track length chip to chip. The channel model was parameterized to allow for adjusting the fiber weave effect length as required.

As you can see, when the length of the fiber weave effect induced skew increases from 0 to 12.7 inches, the fundamental frequency nulls in the differential insertion loss plots decrease. These nulls occur at the fundamental frequency (fo) and every odd harmonic.

Also, the eye shows some degradation at 5.6 inches of fiber weave effect and starts to distort significantly after 7.8 inches. At 12.7 inches, fo equals the Nyquist frequency of the data rate (in this case 2.5GHz) and the eye is totally closed.

You can predict the resonant frequency ahead of time and use it to gain some intuition before you simulate and validate the results. If you know the total intra-pair timing skew, fo is calculated using the following equation:

image

Where:

fo = resonant frequency

tskew = total intra-pair timing skew

Example:

Using tskew = 16 ps/in we calculated above and using 12.7 inches from the last simulation results in the figure above, the fundamental resonant frequency null is:

image

You can find more details of this phenomena plus a novel way to model and simulate it from a recent  White Paper I published titled, “Practical Fiber Weave Effect Modeling”. It, along with other papers, is found on my website at LamsimEnterprises.com.

Written by Bert Simonovich

January 8, 2011 at 3:03 pm

Characteristic Impedance and Propagation Delay of a Transmission Line

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A transmission line is any two conductors with some length separated by a dielectric material. One conductor is the signal path and the other is its return path. As the leading edge of a signal propagates down a transmission line, the electric field strength between two oppositely charged conductors creates a voltage between them. Likewise, the current passing through them produces a corresponding magnetic field. A uniform transmission line terminated in its characteristic impedance will have a constant ratio of voltage to current at a given frequency at every point on the line.

To ensure good signal integrity, it is important to maintain a constant impedance at every point along the way. Any change in the characteristic impedance results in reflections which manifests itself into noise on the signal. In any printed circuit board design, it is almost impossible to maintain a constant impedance of the transmission path from transmitter to receiver. Things like vias, non-homogeneous dielectric, thickness variation and other component paracitics all contribute to impedance mismatch.   In high-speed designs, uncontrolled impedance can significantly reduce voltage and timing margins to the point where the circuit may be marginal or worst inoperable. The best you can do is to try to minimize each impedance discontinuity when they occur.

Lossy Transmission Line Circuit Model:

imageThe circuit model for a lossy transmission line assumes an infinite series of two-port components as illustrated. The series resistor  represents the distributed resistance with the units as ohms (Ω) per unit length. The series inductor represents the distributed loop inductance with the units as henries (H) per unit length. Separating the two conductors is the dielectric material represented by conductance G in siemens (S) per unit length. Finally, the shunt capacitor represents the distributed capacitance between the two conductors with units of farads (F) per unit length.

A 2D field solver is the best tool to extract these parameters from a given transmission line geometry. It assumes, however, that the same geometry is maintained through its entire length. Many spice like simulators need these RLGC parameters for their lossy transmission line models.

Given the RLGC parameters, the characteristic impedance can be calculated by the following equation:

image

Where:

Zo is the intrinsic characteristic impedance of the transmission line.

Ro is the intrinsic series resistance per unit length of the transmission line.

Lo is the intrinsic loop inductance per unit length of the transmission line.

Go is the intrinsic conductance per unit length of the transmission line.

Co is the intrinsic capacitance per unit length of the transmission line.

Lossless Transmission Line:

For the lossless transmission line model, Ro and Go are assumed to be zero. As a result, the equation reduces to simply:

image

Propagation Delay:

Propagation delay, as it relates to transmission lines, is the length of time it takes for the signal to propagate through the conductor from on point to another. Given the inductance and capacitance per unit length, the propagation delay of the signal can be determined by the following equation:

image

Where:

tpd is the propagation delay in seconds/unit length.

Lo is the intrinsic loop inductance per unit length of the transmission line.

Co is the intrinsic capacitance per unit length of the transmission line.

Relative permittivity is also known as relative dielectric constant . The number is a measure of an insulator material’s ability to transmit an electric field compared to a vacuum, which is 1. For simplicity, it is usually referred to it as just the dielectric constant, Dk.

Electromagnetic signals propagate at the speed of light through free space. When these signals are surrounded by insulating material other than air or a vacuum, the propagation delay increases proportionally. You can determine the propagation delay with a known Dk by the following equation:

image

Where:

Dk is the dielectric constant of the material.

c is the speed of light in free space = 2.998E8 m/s or 1.180E10 in/s.

Written by Bert Simonovich

January 2, 2011 at 5:36 pm

Driver’s Output Impedance From IBIS

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In a recent post from the SI-list I subscribe to asks a question; “How do you find the driver impedance information from the IBIS file?” Most of the time we want this information so that we can explore mitigation techniques to control reflections caused by impedance discontinuities of the transmission path.

IBIS stands for Input/Output Buffer Information Specification and is controlled by the IBIS Open Forum organization. It is a device modeling technique used in simulation to provide a simple table based; non-proprietary buffer model derived from a real semi-conductor device. IBIS models can be used to characterize I/V output curves, rising/falling waveforms and pin parasitics of the device packaging.

imageWhen a driver’s output impedance is not matched to the transmission line characteristic impedance (Zo), there are reflections which causes ringing at the receiver as shown by the red waveform in the figure on the left. Terminating the transmission line at the receiver using a pull-up or pull-down resistor to match Zo is one way to cure this. Although this approach works fine, it is not the preferred method because the resistor value would be in the 45-70 Ohm range to match the typical single-ended transmission line impedances found in modern PCB designs. Such a low resistance causes additional loading on the driver resulting in higher power dissipation.

A better method is to add a series resistor at the end of the driver to make up the difference in impedance. For example if the buffer’s output impedance is 20 Ohms driving a 50 Ohm transmission line, you would add a 30 Ohm resistor in series with the output.

Because the buffer is a semi-conductor, it’s output impedance could vary based on rising/falling edge transitions, manufacturing process (slow, typical, fast), and the load it is driving. Since IBIS models are ASCII based, you can simply use your favourite text editor to view and quickly estimate the output impedance when driving 50 Ohms using two of the four V-T waveform tables.

Here’s how:

The output impedance is often different for the rising edge compared to the falling edge. To determine the output impedance of a low to high transition you would use the pull-down [Rising Waveform]; R_fixture = 50; V_fixture = 0.000 table. A sample of what this table looks like is shown below:

[Rising Waveform]
R_fixture = 50.0000
V_fixture = 0.000

| time           V(typ)                V(min)               V(max)
|
0.000S          0.000V              0.000V                0.000V
0.2000nS      0.000V              0.000V              -1.7835uV
0.4000nS      -1.1143mV       -8.0018uV        -7.8340mV
0.6000nS       0.1336V           -5.4161mV         0.9354V
0.8000nS       1.1220V           -12.5300mV       2.3940V
*                   *                        *                        *
*                   *                        *                        *
9.6000nS       2.5680V             2.1880V            2.7880V
9.8000nS       2.5680V             2.1880V            2.7880V
10.0000nS  2.5680V         2.1880V        2.7880V

imageThe first three lines of the table tells us that the rising waveform has a 50 Ohm resistor connected to the buffer output and pulled-down to 0V as shown by the equivalent circuit on the right.

The combination of the output impedance (Zs) and the 50 Ohm load forms a simple voltage divider network described by the following equation:

clip_image002

Where:

VO = Voltage at the output pin of the buffer
VDC = Supply voltage
Zs = Buffer impedance

Solving for Zs, we end up with the following equation:

clip_image002[5]

If VDC is 3.3V, and VO is 2.568V using the typical voltage at 10 nS from the V-T table above, the output impedance for the rising edge into 50 Ohms is equal to 14.25 Ohms.

To determine the output impedance of a high to low transition you would use the pull-up [Falling Waveform]; table similar to the following example:

[Falling Waveform]
R_fixture = 50.0000
V_fixture = 3.3000
V_fixture_min = 3.0000
V_fixture_max = 3.4500
| time           V(typ)              V(min)              V(max)
|
0.000S       3.3000V         3.0000V         3.4500V
0.2000nS       3.3000V             3.0000V             3.4500V
0.4000nS       3.2995V             3.0000V             3.4500V
*                   *                        *                        *
*                   *                        *                        *
9.4000nS       0.5598V             0.6824V             0.4812V
9.6000nS       0.5598V             0.6824V             0.4812V
9.8000nS       0.5598V             0.6824V             0.4812V
10.0000nS  0.5598V         0.6824V         0.4812V

image

This time, the table tells us the falling waveform has a 50 Ohm resistor connected to the buffer output and pulled-up to V_fixture as shown by the equivalent circuit on the right.

The output impedance is calculated by the following equation:

clip_image002[11]

Where:

VO = Output voltage when the driver is sinking current
V_Fix = Voltage of the test fixture

Using typical values for V_Fix = 3.3V and VO = 0.5598V at 10nS,  Zs = 10.21 Ohms.

As you can see for this particular IBIS model, the output impedance varies depending on the edge transition. For a rising edge, the output impedance is 14.25 ohms and 10.21 Ohms for a falling edge when using the typical values. The impedances will also vary under min/max conditions.

If your load is something other than 50 Ohms, you should NOT rely on this simple method for signoff. Instead you should simulate it if the design is critical. Sometimes though we need a quick ball park number to gain some insight of a particular design or to give us some intuition of what to expect from simulation.

You can validate this methodology using any Spice-like simulator which supports IBIS models. There are many to choose from like HSPICE, Hyperlynx, Cadence Spectraquest, Ansoft Designer from ANSYS and Agilent ADS to name a few. Chances are if you work for a large company, you already have access to some of these tools. If you are a student or someone just starting to learn about signal integrity, there is an alternative available. Fortunately, Spectrum Software offers Micro-cap 10; a free trial of its SPICE software you can use. Although it is limited to the number of components, nodes and performance, it is more than adequate for this and other signal integrity studies. Personally, I found it quite easy to pick up and get productive fairly quickly.

imageFor the purpose of the analysis, the output buffer and it’s impedance (Zs) can be simplified as shown by the schematic on the left. When the buffer drives a 50 Ohm transmission line, you typically see the waveforms at the driver’s output (blue) and receiver’s input (red) as shown in the following plot:

imageThe initial step in the rising and falling edges of the blue waveform (Vs) is due to the voltage divider action between Zs and Zo. Let us call these steps as a “porch” and designate the voltages as Vp_rise/Vp_fall for the rising and falling porches respectively.

Vp_rise is equivalent to the maximum voltage of Rising Waveform table found in the IBIS model. Vp_fall is equivalent to the minimum voltage of Falling Waveform table.

The analysis is best summarized by the following Figure:

image

A common circuit topology was built using the schematic editor. The respective greyed-out devices are disabled during simulation making it a convenient way of switching them in and out for the different topologies. R1 is reserved for the series termination resistor and is set to 0 Ohms initially. Once the output impedance is determined, R1 is set to the difference between Zo and the output impedance Zs.

The top topology simulates the Pull-up test fixture and used to verify the Falling Waveform table in the IBIS model. Similarly, the center topology simulates the Pull-down test fixture for the Rising Waveform table. The bottom topology has the output buffer driving a real world 50 Ohm transmission line.

The results of the simulations are shown adjacent to their respective topologies. Referring to the last case, Vp_rise=2.555V and Vp_fall=3.3V-2.726V=0.574V .  As you can see there is excellent correlation when you compare them against the IBIS model’s voltages of  2.568V and  0.5598V respectively. Using the simulated voltages and solving for Zs, we get 14.58 Ohms and 10.53 Ohms respectively.

Because Zs is different for the rise time and fall time, you can never perfectly compensate for the impedance mismatch. The best approach is sometimes to take the average value between the two. In this case Zs_avg=12.56 Ohms.

Once Zs is known, the series resistor can be calculated as follows:

clip_image002[1]

When 38 ohms is substituted in the transmission line topology, the waveform is clean with minimum reflections as shown by the following results:

image

In conclusion, the methodology presented here is a simple and effective way to predict the driver’s output impedance from an IBIS model. Try it next time someone asks you the question, “How do you find the driver impedance information from the IBIS file?”

Written by Bert Simonovich

December 22, 2010 at 2:26 pm

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