Archive for the ‘Printed Circuit Boards’ Category
COUPLED TRANSMISSION LINES AND CROSSTALK
Originally published Signal Integrity Journal August 9, 2022
When two coplanar parallel traces running in close proximity over the coupled length, as shown in Figure 1, they are electromagnetically coupled together.
When two complementary signals are transmitted, there is mutual electromagnetic coupling defined by the amount of mutual inductance and capacitance. This is known as differential signaling. The differential impedance (Zdiff), is the instantaneous impedance of a pair of transmission lines.
The impedance of each trace, when driven differentially, is known as the oddmode impedance (Zodd). Conversely, when each trace is driven with the same polarity, the impedance of each trace is known as the evenmode impedance (Zev).
Differential impedance is simply twice the oddmode impedance:
Equation 1
When Zodd = Zev, the traces are deemed to be uncoupled and there will be no crosstalk (XTalk). The characteristic impedance (Zo) of a single trace, in isolation, is equal to the geometric average (Zavg) of Zodd and Zev. When Zodd and Zev are not equal, there will be some level of XTalk, depending on the space between traces. In this case, Zo is approximately equal to Zav and is given as;
Equation 2
Crosstalk
There are two types of XTalk generated; NearEnd (NEXT), or backwards XTalk, and FarEnd (FEXT), or forward XTalk.
Figure 1 Illustration of NEXT and FEXT. As the aggressor signal propagates from port 3 to port 4, NearEnd XTalk appears on port 1 and FarEnd XTalk appears on port 2 after one time delay (TD) of the interconnect.
NEXT
Refer to Figure 1. Through electromagnetic coupling, NEXT voltage (Vb) is related to the coupled current through a terminating resistor (not shown) at port 1; when driven by an aggressor voltage (Va) at port 3. When port 1 is terminated, the backward crosstalk coefficient (Kb) is defined by;
Equation 3
where;
Vb = the voltage at port 1
Va = the peak voltage of the aggressor at port 3
The general signature of the NEXT waveform, for a gaussian step aggressor, is shown in Figure 2. Va is the aggressor voltage at port 3 of Figure 1. Vb is the NEXT voltage at port 1. The NEXT voltage continues to increase in response to the rising edge of the aggressor until it saturates after the aggressor’s risetime. The green waveform (VaFE) is the aggressor voltage at port 4 after one time delay (TD). The duration of Vb waveform lasts for 2TD of the coupled length.
Figure 2 NEXT voltage signature, Vb in response to a gaussian step aggressor, Va. The duration of NEXT is equal to 2TD of the coupled length. VaFE is the aggressor voltage shown after one TD. simulated with Teledyne Lecroy WavePulser 40iX software.
When TD is equal to onehalf of the linear risetime, the NEXT voltage becomes saturated. The minimum length to reach saturation is known as the saturated length (Lsat), and is given by [1]:
Equation 4
where:
Lsat = the saturation length for nearend cross talk in inches
RT = Linear risetime to reach Va in ns
c = the speed of light = 11.8 in nsec
Dkeff = The effective dielectric constant surrounding the trace.
For example, a signal with a linear RT of 0.1nsec, to reach an aggressor voltage of 1V using FR4 material, with a Dkeff of 4, the saturation length in stripline is;
Important note: In PCB stripline construction, Dkeff is the Dk of the dielectric mixture of core and prepreg. But in microstrip, without solder mask, Dkeff is the mixture of Dk of air and Dk of the substrate. It is very difficult to predict the exact Dkeff in microstrip without a field solver, but a good approximation can be obtained by [3];
Equation 5
where;
Dkeff_{MS} = effective dielectric constant surrounding the trace in microstrip
Dk = Dielectric constant of the material
H = Height of dielectric
W = trace width
t = trace thickness
For example, a signal with a linear RT of 0.1ns, to reach an aggressor voltage of 1V and Dkeff_{MS} of 2.64, the saturation length in microstrip is;
If the coupled length (Lcoupled) is less than Lsat, the NEXT voltage will peak at a value less than the saturated NEXT voltage. The actual NEXT voltage, Vb is scaled by the ratio of coupled length to saturation length and is given by [1]:
Equation 6
For example, for a coupled of length of 100 mils and saturated length of 295 mils, NEXT voltage will be (100/295) or 33.9% of the saturated NEXT voltage.
NEXT vs Coupled Length in Stripline
Figure 3 plots NEXT voltage vs coupled lengths for 100mils, 295 mils and 590 mils representing less than, equal to and greater than Lsat respectively. For a coupled stripline geometry modeled with Polar SI9000 field solver (Figure 3B), Kb is 0.065.
Each length was then simulated in Polar Si9000 and touchstone files were imported into Keysight PathWave ADS software for further analysis. The results are plotted in Figure 3A.
Figure 3 Example of NEXT voltage vs couple lengths of 100 mils, 295 mils and 590 mils in stripline, with linear rise time of 0.1ns. Modeled with Polar Si9000 and simulated with Keysight PathWave ADS.
As can be seen, using a 1V aggressor with a linear risetime of 0.1ns and a saturated length of 295 mils, the NEXT voltage is 63.2 mV, compared to full saturated NEXT voltage of 64.8 mV. With a coupled length of 100 mils, NEXT voltage saturates at 22.2 mV, for the duration of the aggressor’s risetime, compared to 22.03mV predicted by Equation 6 [1].
NEXT vs Coupled Length in Microstrip
Similarly, Figure 4 plots NEXT voltage vs coupled lengths for 100mils, 363 mils and 590 mils for Lsat respectively. For a coupled microstrip geometry modeled with Polar SI9000 field solver (Figure 3B), Kb is 0.055.
Each length was then simulated in Polar Si9000 and touchstone files were imported into Keysight PathWave ADS software for further analysis. The results are plotted in Figure 4A.
Figure 4 Example of NEXT voltage vs couple lengths of 100 mils, 363 mils and 590 mils in microstrip with linear rise time of 0.1ns. Modeled with Polar Si9000 and simulated with Keysight PathWave ADS.
As can be seen, using a 1V aggressor with a linear risetime of 0.1ns and a saturated length of 363 mils, the NEXT voltage is 54.6 mV, compared to full saturated NEXT voltage of 54.9 mV. With a coupled length of 100 mils, NEXT voltage saturates at 15.8 mV for the duration of the aggressor’s risetime, compared to 15.1mV predicted by Equation 6.
The magnitude of the NEXT voltage is a function of the coupled spacing between the two traces. As the two traces are brought closer together, the mutual capacitance and inductance increases and thus the NEXT voltage, Vb, will increase as defined by [1];
Equation 7
where;
Vb = NEXT voltage on victim
Kb = Backward crosstalk (NEXT) coefficient
Va = Aggressor voltage
Cm = Mutual capacitance per unit length
Lm = Mutual inductance per unit length
Co = Trace capacitance per unit length
Lo = Trace inductance per unit length
Unfortunately, the only practical way to calculate Kb is to use a 2D field solver to get the inductive and capacitance matrix elements from a field solver.
Alternatively, if only the odd and even mode impedances are known, then Kb is given as [2];
Equation 8
where;
Zterm = Victim input termination impedance, normally the characteristic impedance (Zo) of a single trace.
When Zterm is open circuit, Kb’ is given as [2];
Equation 9
FEXT:
FEXT voltage is correlated to the coupled current through a terminating resistor (not shown) at port 2 of Figure 1. The forward crosstalk coefficient, Kf, is equal to the ratio of FEXT voltage to aggressor voltage at the far end, defined as;
Equation 10
where;
Vf = the far end crosstalk voltage
VaFE = the peak voltage of the aggressor at farend
The general signature of the FEXT waveform, for a gaussian step aggressor, is shown in Figure 5. V_{f} is the forward crosstalk voltage at port 2 of Figure 1. VaFE is the aggressor voltage appearing at the far end port 4. FEXT voltage differs from NEXT in that it only appears as a pulse at TD after the signal is launched. In this example, the negative going FEXT pulse is the derivative of the aggressor’s rising edge at TD. The opposite is true on the falling edge of an aggressor.
Figure 5 FEXT voltage signature, Vf, is forward crosstalk (FEXT) voltage in response to a gaussian step aggressor voltage, VaFE. Simulated with Teledyne Lecroy WavePulser 40iX software.
Unlike the NEXT voltage, the peak value of FEXT voltage scales with the coupled length. It peaks when its amplitude grows to a level comparable to the voltage at 50% of the aggressor’s risetime at TD as shown in Figure 6. In this example, the coupled lengths are: 2, 4, 6, 8 and 10 inches respectively.
As the wave propagates along the transmission line, the RT degrades due to the dielectric dispersive loss. In the same way the aggressor waveform couples FEXT voltage onto the victim, FEXT voltage also couples noise back onto the aggressor affecting the risetime as shown. Due to superposition, the aggressor waveform shown at each TD is the sum of the FEXT voltage and the original transmitted waveform that would have appeared at TD with no coupling.
Figure 6 Microstrip FEXT voltage increase vs TD for coupled lengths of 2, 4, 6, 8 and 10 inches respectively. Simulated with Teledyne Lecroy WavePulser 40iX software.
If the risetime at TD is known, the FEXT voltage, Vf can be predicted by [1];
Equation 11
where;
Vf = FEXT voltage on victim
VaFE = Farend aggressor voltage
Kf = FEXT coefficient
Cm = Mutual capacitance per unit length
Lm = Mutual inductance per unit length
Co = Trace capacitance per unit
Lo = Trace inductance per unit length
RT = Risetime of aggressor signal at TD in sec
c = Speed of light
Dkeff = Effective dielectric constant surrounding the trace
Len = Length of trace
Although the inductive and capacitive matrix elements can be obtained using a 2D field solver, the risetime is more difficult to predict because of risetime degradation, as well as impedance variations along the line causing reflections. But worst of all, as seen in Figure 6, is the forward crosstalk coupling affecting the aggressor’s risetime makes it next to impossible to predict.
The only practical way to calculate Kf is to model and simulate the topology using a circuit simulator that supports coupled transmission lines. The circuit simulator should have an integrated 2D field solver built in to allow automatic generation of a coupled transmission line model from the crosssectional information.
Since the dielectric surrounding the traces in stripline is more homogeneous, than it is in microstrip, the best way to significantly reduce, or eliminate FEXT, is to route the traces in stripline geometry. Depending on the difference in Dk between core and prepreg used in the stackup, there is always a probability there will be some small amount of FEXT generated. The best way to mitigate this is to choose cores and prepregs to have similar values of Dk when designing the stackup.
References:
[1] E. Bogatin, “Signal Integrity Simplified”, 2^{nd} edition, Prentice Hall PTR, 2010
[2] B. Young, “Digital Signal Integrity”, Upper Saddle River, NJ: Prentice Hall, 2001
[3] E. O. Hammerstad, “Equations for Microstrip Circuit Design,” 1975 5th European Microwave Conference, 1975, pp. 268272, doi: 10.1109/EUMA.1975.332206.
[4] E. Bogatin, B. Simonovich, “Dramatic Noise Reduction using Guard Traces with Optimized Shorting Vias”, DesignCon 2013, Santa Clara, CA, USA
Field Solver Nuances: How to avoid GIGO
To avoid “garbage in, garbage out” (GIGO) with any field solver, first you need to understand the little nuances of PCB fabrication process and how to interpret manufacturers’ data sheets. But most importantly you need to understand the tool’s user interface and what it is asking for.
All 2D or 3D field solvers will give accurate impedance predictions. The differences are the type of solvers used under the hood and complexity of the user interface. Simple 2D field solvers, used in many of today’s stackup planners, simply give predicted characteristic impedance based on material properties and trace geometries. More complex, 2.5D or 3D field solvers, allow for additional material parameters and can predict insertion loss, phase delay and impedance over frequency. Some will even export RLGC and touchstone files for further signal integrity analysis.
Standard PCBs are fabricated using cores and prepreg material. Prepreg sheets are a mixture of fiberglass (glass) cloth and resin which is partially cured. Cores are simply cured prepreg sheets with copper bonded to one or both sides of the laminate. Copper is etched away on each side of the foil to leave the circuit pattern.
In a multilayer PCB, cores and prepreg sheets are alternately stacked symmetrically above and below the middle of the layup then pressed under heat and pressure. The prepreg layers gets thinner when pressed allowing the resin to fill the voids between the copper features that were etched away on the cores.
One important parameter for accurate impedance modeling is dielectric constant (Dk). The best source is from laminate suppliers’ data sheets. But all data sheets from laminate suppliers are not the same.
“Marketing” data sheets are data sheets easily found on laminate suppliers’ websites. They are meant for quick comparison of dielectric properties to narrow your search for the right laminate for your application. They include mostly thermal and mechanical properties, which are important for the physical structure of the material and how it will perform with other material properties in the stackup during processing [3].
Marketing data sheets usually only report a typical Dk value at fifty percent resin content at two or three frequency points. Depending on glass style, resin content and thickness, Dk and dissipation factor (Df), will be different for different cores and prepreg thicknesses for the same laminate chemistry. In the end, they are not representative of what is needed to design an actual stackup, or to do impedance and loss modeling. Using these numbers will almost always lead to inaccurate impedance and signal integrity (SI) results.
Instead, you need to use the same Dk/Df construction table data sheets PCB fabricators use for the stackup. Dk/Df construction tables provide the actual core and prepreg thicknesses, resin content, and Dk/Df for the different glass styles, over different frequencies. Depending on the stackup, a combination of thicknesses is often needed to meet impedance requirements and have different Dk values.
Many engineers assume Dk published is the intrinsic property of the material. But in fact, it is the effective Dk (Dkeff) measured by a specific industry standard test method. It does not guarantee the values directly correspond to design applications. When compared against measurements from a design application, there is often a discrepancy in Dkeff due to increased phase delay caused by surface roughness [1].
Dkeff is highly dependent on the test apparatus and conditions of how it is measured. One popular test method, IPCTM650 2.5.5.5C clamped stripline resonator test method, assures consistency of product during fabrication. Due to the nature of this test method, the materials under test are not physically bonded together, air is entrapped between the various layers. These small air gaps are caused by: roughness of the copper foil plates in the fixture; roughness profile imprint left on the surface from the foil that was removed from the test samples; copper removed on the resonant element pattern card. Air entrapment results in a lower Dkeff than what is measured because in a real PCB everything is bonded together, with no air entrapment [3].
All glass weave reinforced laminates are anisotropic, which means Efield orientation, relative to the glass weave, is different depending on test method. Efields produced from tests like IPCTM650 2.5.5.5C are transverse to the glass weave and Dkeff measured is outofplane.
Efields produced by TM6502.5.5.13 split post cavity resonators, are parallel to the fiberglass weave Dkeff measured this way is inplane. Dkeff is typically higher for inplane measurements, compared to outofplane, depending on the glass resin mixtures used in the stackup.
Another source of discrepancy is not accounting for increased Dkeff due to the pressed thickness of prepreg. Since prepreg sheets have a certain percentage of resin content for the thickness, after pressing the resin content is reduced and since Dk is a function of resin and glass mixture, there will be a higher percentage of glass after pressing and thus slightly higher Dkeff.
The most common PCB trace geometries are microstrip and stripline. A simple microstriip geometry is bare copper traces over a reference plane, separated by a dielectric height H, as shown in Figure 1. Depending on the stackup, there may be a core and prepreg layer between the outer layer and reference plane with the same or different Dk values for Dk1 and Dk2.
Simple stripline geometry has copper traces between two reference planes. For singleended (SE) signals, there is only one trace used in the field solver to calculate the SE impedance. For differential pairs, there are two traces separated by a space. Because resin fills the voids between copper features the Dk_{resin} will be lower than Dk1 or Dk2, shown in Figure 1.
The last thing to note is the wider side of the trace always faces the core material. This is a very important point to remember when using any field solver. If you get it reversed, it will lead to inaccurate results.
Figure 1 Generic microstrip and stripline geometries.
Thickness of copper traces is an important parameter for accurate impedance prediction. Copper thickness is usually specified in ounces per square foot. Most common thicknesses for inner layer traces are ½ oz. and 1 oz. foil. But field solvers expect an actual thickness dimension.
Most designers assume 0.7 mils (18um) thickness and 1.4 mils (36um) for ½ oz. and 1 oz. respectively. But because of the price of copper, the copper you get from foil manufacturers will likely be the minimum thickness allowed under IPC4562A. When you factor in the typical thickness after fabrication, the typical thickness can be 0.6 mils (15um) and 1.2 mils (30um). But the minimum thickness allowed under IPCA600G3.2.4 is 0.45 mils (11.4um) and 0.98 mils (24.9 um) for ½ oz. and 1 oz. respectively.
Due to the nature of the etching process, the traces will usually be trapezoidal in shape. This is known as the etch factor (EF), as defined by IPCA600G. It is the ratio of the thickness (t) to half the difference between W1 and W2.
Thus,
Some field solvers will define EF differently so it is important to understand how to specify it properly.
Once you’ve come up with a proposed stackup, the next step is to do some impedance modeling. Normally your fab shop comes up with this, but it is a good idea to validate their proposal, to ensure you are in sync with them.
The first thing to do, is identify the layers from which to model. Next, is to use your field solver, to model characteristic impedance. Since all field solvers are different, and user interfaces can be confusing, make sure you understand the little nuances of your tool.
The next thing is to identify the core layers in the stackup and input H1 and Dk1 for the dielectric. Then, input the pressed thickness for prepreg H2 and Dk2, not the thickness found in Dk/Df construction tables. You can usually trust the pressed thickness from your fab shop. But be careful how the field solver defines H2. Most field solvers define it as shown in Figure 1, but some solvers, like Polar Si9000e, define it as (H2+t), shown in Figure 2. Usually, you can trust the pressed thickness from your board shop stackup drawing.
Finally, if your field solver allows for it, fill in Dk_{resin} between two traces if you know it. It will be lower than Dk2. Since this number is generally hard to obtain, a rough estimate to use is the lowest Dk value from the highest resin content prepreg found in Dk/Df construction tables.
Once everything is set up, optimize the line width and space, until the desired characteristic impedance is reached. One last point to remember, is that all 2D field solvers only calculate lossless characteristic impedance. But when we measure an impedance test coupon with a time domain reflectometer (TDR), we are measuring the instantaneous impedance along the PCB trace.
More often than not, impedance is different than what was predicted. This is because a 2D field solver only calculates the lossless characteristic impedance of the crosssectional geometry; while a TDR measures the instantaneous impedance of a lossy transmission line at every point along its length.
A 2D field solver has no input for conductor resistivity, dielectric loss, or how long the conductor is. Resistive loss often results in a slow monotonic rise in the impedance profile. IPCTM650 specifies the measurement zone between 3070 % and most PCB fab shops, will measure an average impedance
In this example, shown in Figure 2, for a low loss dielectric, there is a 45 ohm difference depending on where the measurement is taken. When all input parameters are included correctly for a lossy transmission line model, you can see there is excellent correlation.
Figure 2 Lossless characteristic impedance from Polar SI9000 field solver (left) vs measured TDR plot from an impedance coupon and lossy transmission line model from Polar Si9000.
Although minor differences in individual parameters may have second order affects, collectively they could add up to give poor correlation to measurements. But if you consider all the nuances discussed in this article, you can get pretty good accuracy as shown in Figure 2.
[1] Bert Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”, DesignCon 2017, Santa Clara, CA
[2] Bert Simonovich, “PCB Fabrication: What SI/PI Engineers Need to Know for First Time Modeling Success”, DesignCon 2021 Spring Break Webinar, April 12, 2021
[3] Bert Simonovich, A Tale of Two Data Sheets and How Foil Roughness Affects Dk, White paper
A Tale of Two Data Sheets Part 2: Making Sense of “Design” Dk
Originally published in Signal Integrity Journal, May 31, 2022
In part one, “A Tale of Two Data Sheets”, I explained how air entrapment, due to IPCTM6502.5.5.5 test method manual [7], is the primary reason for effective dielectric constant (Dkeff) and phase delay discrepancies between simulation and device under test (DUT) measurements. Entrapped air of the test fixture results in a lower Dk published in laminate suppliers’ Dk/Df tables than what would be measured in a real printed circuit board (PCB) application. This is because in a real PCB, everything is bonded together with no air entrapment, as shown in a crosssection view of Figure 1.
Figure 1. Example of foil bonded to core or prepreg dielectric. Rz is 10point mean roughness of foil as measured by a profilometer. Hsmooth is the thickness of the dielectric as if the foil was removed.
When copper foil with the same Rz roughness is bonded to each side of the core or prepeg, Dkeff is determined heuristically from published Dk by this simple correction factor [1]:
Equation 1.
where:
Hsmooth is the thickness of the dielectric as if the foil was removed
Dk = Dielectric constant published in laminate suppliers’ Dk/Df tables
Rz = 10point mean equivalent to Rz(JIS) or Rz(DIN) published in foil suppliers’ data sheets. This is not to be confused with Rq, which is RMS value of roughness.
Rogers Corporation [4] understands this. That’s why they provide the “design” Dk in addition to their bulk Dk, as measured by TM650 clamped stripline resonator test method [7]. Design Dk is an average number using a differential phase length method from several different tested lots of material and on the most common thickness. This method is based on measuring phase difference from two identical microstrip transmission line geometries, of different lengths on the same panel. Because this is a real microstrip application, the dielectric is fully bonded to the copper and there is no air entrapment. Knowing the phase and length difference, the effective Dk is empirically determined.
The accuracy of the resultant effective Dk depends on several factors like:


fixture design



length ratio between two transmission lines



material thickness of the sample under test



the thickness of the copper



actual roughness of the foil on the microstrip circuit.

In lieu of actual Dk/Df tables, Rogers provides a handy impedance calculator as shown in in the RO4003C example of Figure 2. There are three Dk options available to use:


Zaxis bulk Dk



Dk values for specific frequencies



Dk values for characteristic impedance

The first radio button, as shown in Figure 2, gives the zaxis bulk Dk value of 3.55, as measured by TM650 2.5.5.5 test method manual. However, the value does not change when different frequencies are selected. This makes the number suspect since clearly design Dk does change over frequency. Thus this number can be considered equivalent to marketing data sheets, and should not be used.
When the middle radio button is selected, a Dk value for a specific frequency is displayed, which corresponds to a frequency entered in the lower right frequency box of Figure 2. This is the most useful option, since it allows the user to choose the right design Dk at whatever frequency they choose for their application, including characteristic impedance. This option already factors in the foil roughness effect, so no correction factor is needed to use in your simulator.
The last radio button selects a Dk for characteristic impedance calculation. It is a “design” Dk with yet a different Dk. Similar to the Bulk Dk option, it does not change over frequency. For any simulation tool other than the Rogers’s calculator, Bulk Dk and Dk values for characteristic impedance values should not be used.
Figure 2. Example of Rogers Corporation impedance calculator. For an 8mil thick RO4003C dielectric, bulk Dk is 3.55 while design Dk over frequency is shown in bottom left window.
Under the information tab, the user can download design Dk over frequency, for a specified thickness, shown in the bottom left window of Figure 2. This data can be selected and copied to the clipboard and pasted into a spreadsheet for further processing.
Figure 3 plots design Dk vs. frequency for various thickness from 8 mils to 60 mils for RO4003C material. As can be seen, design Dk is not constant over frequency and furthermore it is different for different thicknesses, mainly due to the roughness of the foil that is already included in the measurement.
Thinner materials have a higher design Dk than thicker materials for the same roughness of foil. This is because when the foil teeth protrude into a thin dielectric material, there is a higher concentration of efields, resulting in higher capacitance between top and bottom copper layers. For thick dielectrics the foil teeth have less of an impact on capacitance and thus Dkeff, as described mathematically by Equation 1.
Since the roughness of the foil does not significantly influence the design Dk for thick laminates, we can assume the bulk Dk is roughly equivalent to design Dk over frequency for the 60mil laminate.
Figure 3. Design Dk vs. frequency for various thickness of RO4003C from 8 mils to 60 mils mainly due to the roughness of the foil. Thinner material has a higher design Dk than thicker material, for the same roughness of foil.
Heuristically, we can rearrange Equation 1 and estimate the Rz roughness of the foil used on RO4003C laminate to be 6.302 μm from Equation 2.
Equation 2.
where:
Hsmooth is the thickness of the 8 mil (203 μm) laminate
DkBulk = 3.55 at 60 GHz for 60 mil (1524 μm) laminate
Dkeff = design Dk of 8 mil (203 μm) laminate at 60 GHz
A crosssection sample from a time domain reflectometry (TDR) demo board, courtesy of Picotest [6], was measured and is shown in Figure 4. The TDR demo board was fabricated with 8mil thick Rogers RO4003C core laminate and cladded with 2 Oz copper foil.
Five highlighted random sample lengths of copper roughness, labeled Sample 1 to Sample 5 of Figure 4, were analyzed. The total length of each respective sample was then partitioned into five equal sections, similar to the blowup picture of Sample 1, to measure the maximum peak to valley height of each section. The five measurements of each sample length were then averaged to determine the Rz roughness, as described under IPC TM650 2.2.17A [8] and shown in the table of Figure 4.
The mean value of Rz for the five samples was 6.176 μm with a standard deviation (SD) of 1.090 μm. This compares favorably with the estimated roughness of 6.302 μm, determined from Equation 2.
Figure 4. A crosssection sample from a Rogers RO4003C based TDR demo board, courtesy of Picotest [6], used to determine Rz roughness of the foil.
When we use the actual roughness measured from Figure 4 and Equation 1, we can then calculate Dkeff at 60 GHz for different thicknesses, shown in Table 1. As can be seen there is, less than 1% delta compared with design Dk reported from the calculator!
Table 1. Comparison of Roger’s Design Dk vs. Dkeff when simple correction factor applied to Bulk Dk at 60 GHz.
Height 
Height 
Bulk Dk 
Design Dk 
Rz 
Dkeff 
Delta 
8.0 
203 
3.550 
3.785 
6.176 
3.780 
0.13% 
12.0 
304 
3.550 
3.702 
6.176 
3.700 
0.04% 
16.0 
406 
3.550 
3.657 
6.176 
3.661 
0.12% 
20.0 
508 
3.550 
3.625 
6.176 
3.638 
0.37% 
32.0 
812 
3.550 
3.580 
6.176 
3.605 
0.69% 
60.0 
1524 
3.550 
3.550 
6.176 
3.579 
0.82% 
Rogers Corporation provides a handy calculator in lieu of Dk/Df tables in which “design” Dk values over frequency can be used directly without correcting for roughness. When an actual crosssection was analyzed, there was excellent correlation from corrected Dkeff using heuristic methods compared to design Dk from the calculator. Therefore, “design” Dk should be used for impedance modeling and PCB stackup design when using Rogers laminates.
References:


B. Simonovich, “A Tale of Two Data Sheets and What You Need to Know About Dielectric Constant (DK),” Signal Integrity Journal article, April 2022.



L. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness,” DesignCon 2017, Santa Clara, USA.



Isola Group, 6565 West Frye, Chandler, AZ 85226.



Rogers Corporation, 2225 W. Chandler Blvd., Chandler, AZ 85224.



J. Coonrod, “Managing PCB Materials: Dielectric Constant (Dk)”, Rogers Corporation, Blog Article, Sep 11, 2018.



Picotest, Phoenix, AZ 85085.



IPCTM650, 2.2.17A, Test Methods Manual, “Surface Roughness and Profile of Metallic Foils (Contacting Stylus Technique).”



Bereskin, A. B. “Microwave Dielectric Property Measurements”, Microwave Journal, vol. 35, no.7, pp. 98 – 112.

A Tale of Two Data Sheets: Part1
Originally published SI Journal April 26, 2022
When doing printed circuit board (PCB) stackup and signal integrity (SI) impedance modeling, we need to get the dielectric material properties from the right sources. One important parameter for accurate impedance modeling is relative permittivity (ε_{r}) of the dielectric material, otherwise known as dielectric constant (Dk). The best source is from laminate suppliers’ data sheets. Though there is an issue with these I like to think of as, “a tale of two data sheets.”
Marketing data sheets, like the example shown in Figure 1 [6], are easily found on laminate suppliers’ websites. They are meant for quick comparison of dielectric properties to narrow your search for the right laminate for your application. Dielectric properties on marketing data sheets include mostly thermal and mechanical properties, which are important for the physical structure of the material and how it will perform with other material properties in the stackup during processing.
But marketing data sheets are not representative of what is needed to design an actual stackup, or to do impedance and SI loss modeling. Depending on glass style, resin content, thickness, Dk, and dissipation factor (Df) will be different for different cores and prepreg thicknesses for the same laminate. Marketing data sheets usually only report a typical Dk/Df at fifty percent resin content and two or three frequency points. Thickness is not specified. Furthermore, Dk and Df are not constant over frequency. So, using numbers from these data sheets will lead to inaccurate impedance and phase delay results.
Figure 1. Example of a “Marketing” data sheet easily obtained from laminate supplier’s web site. Source Isola Group [6].
Instead, for transmission line modeling, one needs to use the same Dk/Df table data sheets PCB fabricators use to build the stackup. An example Dk/Df table is shown in Figure 2. Dk/Df tables provide the actual core and prepreg thicknesses, resin content, and Dk/Df for the different glass styles, over different frequencies. Depending on the stackup, a combination of thicknesses is often needed to meet impedance requirements. Each thickness will have a different Dk value.
In the example of Figure 2, Dk varies from 2.92 at 10 GHz for 1080 glass style to 3.19 at 10 GHz for 2116 glass style. This represents a Dk variation of 3.3% to 5.6% when compared to a Dk of 3.02 at 10 GHz specified in Figure 1.
Figure 2. Example of a typical “Engineering” data sheet showing Dk/Df table for different glass styles and resin content over frequency. Source Isola Group [6].
Many engineers assume Dk published is the intrinsic property of the material. But, in fact, it is the effective Dk (Dkeff) measured by a specific industry standard test method. When they are compared against real measurements from a design application, there is often a discrepancy in Dkeff due to increased phase delay caused by surface roughness [1].
Dkeff is highly dependent on the test apparatus and conditions of how it is measured. One method commonly used by many laminate suppliers is the clamped stripline resonator test method, as described by IPCTM650 2.5.5.5, Rev C, Test Methods Manual [10].
Since all glass reinforced laminates are anisotropic, any stripline based test method, like TM650 2.5.5.5, or Bereskin stripline test method [13], reports Dk values in which the Efields are transverse to signal propagation. That is, if the signal propagation is in the xy axis direction, then the Dk measured by this method is when Efields are in the zaxis direction.
For Isola’s Dk/Df table [6], shown in Figure 2, Dk values were measured by TM650 2.5.5.5 test method. From that data, the values for most of the constructions are calculated. Additional verification runs are performed to gather statistical data over time and validate that the calculations are reasonable and accurate.
The measurements are done under stripline conditions using a carefully designed resonant element pattern card. It is made with the same dielectric material to be tested. As shown in Figure 3, the card is sandwiched between two sheets of uncladded dielectric material under test. Then the whole structure is clamped between two large plates; each lined with copper foil and grounded. They act as reference planes for the stripline.
Figure 3. Illustration of clamped stripline resonator test method, as described by IPCTM650, 2.5.5.5, Rev C, Test Methods Manual [10].
This test method assures consistency of product when used in fabricated boards. It does not guarantee the values directly correspond to design applications.
Here is why:
Since the resonant element pattern card and material under test are not physically bonded together, air is entrapped between the various layers. These small air gaps are caused by the:

roughness of the copper foil plates in the fixture

roughness profile imprint left on the surface from the foil that was removed from the test samples

copper removed on the resonant element pattern card
Air entrapment, due to the TM650 test method, is the primary reason for effective Dk and phase delay discrepancies between simulation using laminate suppliers’ Dk/Df tables and real measurements from a design application. The small air gaps result in a lower effective Dk than what would be measured in a real PCB because everything is pressed together with no air entrapment, as shown in a crosssection view of Figure 4.
Figure 4. Example of foil bonded to core or prepreg dielectric. Rz_{1 }is rougher than Rz_{2} and H_{smooth} is the thickness of the dielectric as if the foil was removed.
When copper roughness is different on each side of the dielectric, like the example shown in Figure 4, Dkeff is determined heuristically by this simple correction factor:
Equation 1.
where:

H_{smooth} is dielectric core thickness from laminate suppliers’ Dk/Df table data sheet or pressed prepreg thickness from the PCB stackup drawing.

Rz_{1} and Rz_{2} are the conductor roughness of the foil for the respective side of the dielectric from foil suppliers’ data sheet. Typically, Rz is the 10point mean roughness as measured by a mechanical profilometer.

Dk is dielectric constant from laminate supplier’s Dk/Df table data sheet.
In Figure 4, Rz_{1} is the roughness of the top foil, and Rz_{2} is the roughness of the bottom foil. In this example, Rz_{1} is rougher than Rz_{2}. H_{smooth} is the core thickness of the dielectric, as specified in the Dk/Df table, or pressed thickness of the prepreg, often shown on a stackup drawing. It is the thickness of the dielectric as if the foil was removed.
When copper foil with the same Rz roughness is bonded to each side of the core or prepeg, Dkeff can be simplified as:
Equation 2
Figure 5 plots Dkeff over frequency derived from S21 phase or time delay (TD); Dkeff=(TDc_{0 }∕ length)^{2} from a Megtron6 stripline case study [3]. This method is different than IPCTM650 test method in that it determines Dkeff from unwrapped phase delay rather than calculating Dk/Df from resonant peaks over the frequency range defined in the spec.
The blue plot is a simulated case based on core and prepreg Dk values from published Dk/Df tables at 12 GHz. When Dk is corrected due to roughness, using Equation 2, and resimulated, Dkeff is shown in pink. Although the Dkeff has improved, it still does not agree with the measured Dkeff from the device under test (DUT), shown in red.
Figure 5. Comparisons of simulated Dkeff over frequency vs. measured. The red plot is actual measured Dkeff from the DUT. The middle pink plot is a simulation using Dkeff corrected due to roughness. The bottom blue plot is simulated using Dk at 12 GHz as published in Dk/Df tables and noncausal roughness model. The green dashed plot is a simulation using Dkeff due to roughness; a causal HurayBracken roughness model was used. Modeled with Simbeor [11] and simulated with Keysight ADS [12].
The discrepancy between the pink and red plots is because Dkeff from Equation 2 only corrects the phase delay due to self capacitance (C_{11}) per unit length of the transmission line. But roughness of the foil also increases the self inductance (L_{11}) per unit length of the transmission line, which adds additional phase or time delay [4].
This is counter intuitive and can be confusing since we usually relate Dkeff to capacitance only. By definition, Dkeff is the ratio of the actual structure’s capacitance to the capacitance when the dielectric is replaced by air. But this is only true for static electric fields. For timevariant electromagnetic fields, Dkeff becomes frequencydependent [14].
If the propagation delay (tpd) for a single transmission line, in seconds per unit length, is determined by:
Equation 3.
and c_{0} is the speed of light (~3.0E8 m/s) =1/sqrt(μ_{0} ε_{0} ); μ_{0} (4πE−7 H/m) and ε_{0 }(8.8542E−12 F/m) is permeability and permittivity of free space respectively, then:
Equation 4.
where: L_{11}; C_{11} are self inductance in Henries per unit length and self capacitance in Farads per unit length respectively.
Equation 4 clearly shows that with an increase in self inductance there will be a proportional increase in Dkeff. This means for PCB transmission lines, calculating Dkeff=(TDc_{0 }∕ length)^{2} cannot be trusted to be the same as relative permittivity (ε_{r}) of the dielectric material. The consequence for doing so leads to inaccurate impedance predictions and noncausal time domain simulations, resulting in poor correlation to measurements.
A causal model, when simulated, does not produce any change in its output signal before there is a change in its input signal. When field solvers properly correct the self inductance, by applying the roughness correction factor to the imaginary portion of the complex impedance of the metal [4][5], the model is then causal. When combined with the corrected Dkeff for cores and prepregs from Equation 2, there is excellent correlation, as shown by the dashed green plot in Figure 5. Unfortunately, not all field solvers have causal roughness models to correct the inductance in the simulation.
Since there is no simple way to backtrack from a phase measurement to establish the right Dkeff to use for your modeling, especially for lossy stripline constructions, heuristic methods are an alternative.
Using the right Dkeff for your modeling ensures a correct time domain reflectometer (TDR) impedance prediction, as shown in Figure 6. The red plot is measured differential TDR from [3]. When core and prepreg Dk from Dk/Df tables were used along with a noncausal roughness model in the simulation, the blue plot shows an overestimate for impedance. When Dkeff from Equation 2, and a noncausal roughness model was used in the simulation, the pink plot shows an underestimate in the impedance plot.
It is only when we apply a causal HurayBracken roughness model from [11], along with Dkeff from Equation 2, that we see the effect of the increased self inductance, shown by the green dashed line plot in Figure 6.
At first glance of Figure 6, one might interpret the pink plot as having better correlation to the measured red plot. But because the measured plot has an impedance ripple along its length, it is difficult to conclude which is the correct model from the TDR plots alone. It is only when we compare Dkeff derived from the green dashed phase delay plot from Figure 5 that we can conclude the green dashed line TDR plot is the correct impedance.
Figure 6. Simulated vs. measured differential TDR plots when different Dkeff was used in the model. The blue plot overestimates impedance when Dk from data sheets was used. The pink plot underestimates the impedance when Dkeff (Equation 2) and noncausal roughness model was used. The green dashed line plot is when Dkeff (Equation 2) and a causal HurayBracken roughness model were used. Modeled with Simbeor [11] and simulated with Keysight ADS [12].
Summary:
Dielectric constants from marketing data sheets cannot be trusted to properly design PCB stackups and model transmission lines for impedance and phase delay. Instead, laminate suppliers’ Dk/Df tables should be used.
Many laminate suppliers provide Dk/Df tables derived from a clamped stripline resonator test method [10] or similar Bereskin test method [13]. But the numbers do not factor the actual roughness of the foil. When a simple correction factor, based on the thickness of laminate and Rz foil roughness is considered, a more accurate value for Dkeff along with a causal roughness model can be used for impedance and transmission line modeling.
For PCB transmission lines, calculating Dkeff from phase or time delay measurement method cannot be trusted to be the relative permittivity of the dielectric material. Using this value will lead to inaccurate simulation results.
References:
1. L. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness“, DesignCon 2017, Santa Clara, USA.
2. B. Simonovich, “Stackup Beware: Case Study of the Effects on Transmission Line Losses Due to Mixed Reference Plane Roughness”, Signal Integrity Journal article, August 10, 2021.
3. B. Simonovich, “PCB Fabrication: What SI/PI Engineers Need to Know for First Time Modeling Success”, DesignCon 2021 Spring Break Webinar Series, April 1216, 2021.
4. V. DmitrievZdorov, B. Simonovich, Igor Kochikov, “A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics“, DesignCon 2018, Santa Clara, USA.
5. J.E. Bracken, “A Causal Huray Model for Surface Roughness”, DesignCon 2012, Santa Clara, USA.
6. Isola Group, 6565 West Frye, Chandler, AZ 85226.
7. Circuit Foil, 6 Salzbaach, 9559 Wiltz, Grand Duchy of Luxembourg.
8. Rogers Corporation, 2225 W. Chandler Blvd., Chandler, AZ 85224.
9. J. Coonrod, “Managing PCB Materials: Dielectric Constant (Dk)”, Rogers Corporation, Blog Article, Sep 11, 2018
10. IPCTM650, 2.5.5.5, Rev C, Test Methods Manual
11. Simbeor THz [computer software].
12. Keysight ADS Keysight Advanced Design System (ADS) [computer software].
13. Bereskin, A. B. “Microwave Dielectric Property Measurements”, Microwave Journal, vol. 35, no.7, pp. 98 – 112
14. Wikipedia contributors. (2022, January 12). Relative permittivity. In Wikipedia, The Free Encyclopedia. Retrieved 18:14, January 14, 2022.
Characteristic Impedance – Where SI/PI Worlds Collide
Originally published Signal Integrity Journal, February 23, 2021
Signal and power integrity (SI/PI) simulations, measurements, and analysis usually live in two different worlds, but occasionally these worlds collide. One such collision occurs when we refer to characteristic impedance, Z_{0}. Traditionally the PI world lives in the frequency domain while the SI world lives in the time domain.
When designing a power distribution network (PDN) in the PI world, we are mostly interested in engineering a flat impedance below a target impedance from DC to the highest frequency components of the transient current. Practically this is achieved with a network of capacitors with different values connected to the respective power planes as shown in Figure 1.
Figure 1 A simplified model of a typical PDN courtesy [1].
In the real world, there is no such thing as an ideal capacitor. There are always parasitic elements known as equivalent series inductance (ESL) and equivalent series resistance (ESR). Physical characteristics of the PCB, like component mounting inductance, plane spreading inductance, via and BGA ball inductance, along with voltage regulator module (VRM) characteristics also contribute to the impedance profile. When connected together, the interaction of capacitors and parasitic inductance and resistance create a transfer impedance profile with resonant peaks and antiresonant nulls as shown in Figure 2.
The transfer impedance between the VRM and the load is calculated and plotted in the frequency domain with a loglog scale. The resulted impedance curve is then compared to the target impedance (Z_{target}), which is estimated based on the allowed noise ripple and maximum transient current. The flat target impedance is frequency independent in the analysis.
Figure 2 Impedance profile of the PDN as viewed from the pads on the die power rail courtesy [1].
Resonant peaks are due to ESL of one capacitor connected in parallel with another capacitor. Antiresonant nulls are due to the series combination of ESR, ESL, and C for each capacitor. Different capacitor values will have antiresonant nulls at different frequencies.
But in the PI world, there is a rarely talked about characteristic impedance, Z_{0}. In this case, it refers to the geometric average of the reactive impedance of a capacitor (XC) and reactive impedance of an inductor (XL).
Equation 1
At resonance, XL and XC intersect at the characteristic impedance and are equal as shown in Figure 3.
Figure 3 Inductive and capacitive reactance plot of ideal inductor and capacitor versus frequency. At resonance, XL and XC are equal and intersect at the characteristic impedance, Z_{0}. Simulated with Pathwave ADS [6].
This is a very important observation, and it is where the SI/PI worlds collide.
In the SI world, characteristic impedance, Z_{0 }refers to the instantaneous ratio of the voltage to current of a wave front traveling along a uniform transmission line without reflections. For an infinitely long uniform transmission line, Z_{0 }equals the input impedance.
The characteristic impedance of a lossy transmission line is defined as:
Equation 2
Where R is resistance per unit length; G is conductance per unit length; L is inductance per unit length; and C is capacitance per unit length. For a lossless uniform transmission line, R and G are assumed to be zero and thus the characteristic impedance is reduced to:
Equation 3
Time Domain Reflectometer
In the SI world, we usually use a time domain reflectometer (TDR) to measure characteristic impedance, but more often than not, the measured impedance we get is not what we predicted with a 2D field solver. Many 2D field solvers used by most PCB FAB shops only calculate the lossless characteristic impedance of the crosssectional geometry at a single frequency, defined by the dielectric constant (D_{k}). It has no input for conductor resistivity, dielectric loss, or how long the conductor(s) is.
So the issue is: we design the stackup, then do our SI modeling analysis based on stackup parameters and matching characteristic impedance. But the PCB FAB shop will often adjust the line width(s), over and above normal process variation, so that when measured, the impedance will fall within the specified tolerance, usually +/10 percent.
Part of the problem lies with the method used to take the measurements. Most PCB FAB shops follow IPCTM650 Test Methods Manual [2]. But it has limitations because Z_{0 }measured is derived and cannot be directly measured. The reason is the measurements include resistive and dielectric losses, up to the point where the measurement takes place along the TDR plot.
Resistive loss often results in a slow monotonic rise in the impedance profile, shown in the example TDR plot of Figure 4. IPCTM650 specifies a measurement zone between 3070 percent to avoid probing induced ringing affecting the measurements. Most PCB FAB shops will measure an average impedance over this range, usually in the center region.
Depending on the linewidth, thickness and dielectric dissipation factor (D_{f}), the slope of the monotonic rise will vary.
Figure 4 Example TDR plot showing slow monotonic rise in impedance due to resistive losses and IPCTM650 measurement zone.
The problem is that the IPCTM650 test method was last updated back in 2004, when higher dielectric loss, along with wider line widths and thicker copper weights, were used more often. A higher D_{f} tends to compensate for resistive loss by flattening the slope as shown in Figure 5.
On the bottom left is a simulated TDR plot using a high loss dielectric with D_{f} = 0.024. The right side has the exact same geometry properties except D_{f} = 0.004. The average impedance, when measured at the 50 percent point, is 49.8 Ohms on the left side vs. 51.4 Ohms on the right side. We also confirm flatter slope for high loss material.
The actual characteristic impedance predicted by a Polar SI9000 2D field solver [5] in Figure 5 is 49 Ohms. For higher loss material, measuring within the measurement zone would pass without any issues. But for lower loss material, the resistive loss dominates and measuring within the measurement zone will give ~5 percent higher impedance reading compared to the higher loss material. The correct measurement point for Z_{0 }is, in fact, the initial dip, equivalent to the field solver prediction. Depending on the tolerance specified, this may affect yield and cost.
Figure 5 Characteristic impedance prediction by Polar SI9000 2D field solver [5] (top). Simulated 2 inch TDR plots using a high loss dielectric (bottom left) vs. low loss dielectric with exactly the same geometry (bottm right). A higher Df compensates for higher resistive loss thereby flattening the curve. Simulated with Pathwave ADS [6].
Today, with the push to low loss dielectric and finer line widths with thinner copper weights, measuring the true transmission line characteristic impedance using a TDR becomes more challenging. This is even more so when measuring differential impedance, because a change in line width space geometry can have a more profound effect on measured differential impedance.
Using the first article build of a new design, as an example, let’s assume the correct characteristic impedance, when measured at the beginning of the slow monotonic rise of a TDR plot, is on the high end of nominal +10 percent tolerance. Let’s say it’s 54 Ohms. But because of the low loss dielectric and high resistive loss, the TDR measurement at the midpoint is now reading 5% higher at 57 Ohms. This would imply the impedance is now out of spec over nominal and the board would be scrapped.
The PCB fab shop will then go back and adjust the linewidth accordingly for the next build to bring the measurement within range to their measurement set up. Doing this effectively lowers the true nominal characteristic impedance!
If subsequent manufacturing variations pushes the measured impedance within the measurement zone on the low end of the 10 percent tolerance, say 44 Ohms, then the true characteristic impedance, if measured at the initial dip, will be 5 percent lower at 42 Ohms and be out of spec. But the board will pass because it was measured following IPCTM650 test method.
2port Shunt Measurement
But what if there were another way? What if we could borrow impedance measuring techniques from the PI world to determine the true transmission line characteristic impedance in the SI world? Well there is. Enter the 2port shunt measurement technique.
For example, in the PI world, to measure ESL and ESR of a chip capacitor, of a device under test (DUT), a 2port shunt measurement is often used. It is much like the 4point Kelvin measurement technique used to measure very low DC resistance.
The 2port shunt measurement is usually done with a 2port vector network analyzer (VNA). Port 1 of the VNA sends out a calibrated signal, and port 2 measures the voltage signal across the DUT. Often an isolation transformer is also used to break the inherent ground loop when measuring ultralow impedances [3].
Once the measurements have been completed and Sparameters saved in touchstone format, further analysis can be done in your favorite SPICE simulator. Figure 6 is a generic schematic using popular Pathwave ADS [5] that can be used for 2port shunt analysis.
When port 1 and port 2 are connected to port 1 of the DUT and port 2 of the DUT is grounded, the impedance of the DUT can be determined by [3];
Equation 4
Figure 6 Generic Pathwave ADS [6] schematic used for 2port shunt analysis on a S2P file for DUT.
If we replace the DUT in Figure 6 with a capacitor and inductor, we get an impedance plot shown in Figure 7. As we saw earlier, when we take the geometric average of the inductive and capacitive reactance using Equation 1, we get the characteristic impedance. If we apply Equation 4 to the results of a 2port shunt measurements of a capacitor and inductor, we get exactly the same results as shown in the top of Figure 7.
When we replace the capacitor and inductor with a Sparameter file of a transmission line model from Figure 5, we get the plot shown at the bottom of Figure 7. Except for the resonant nulls and peaks, up to a certain frequency, the impedance of a transmission line looks like the impedance of a capacitor when the farend is open, and looks like the impedance of an inductor when the farend is shorted. And because of that, this is where the two worlds collide!
If we take the geometric average of the impedance when the farend is open (Z_{open}) or shorted (Z_{short}), we get the characteristic impedance at that frequency. We note where the red and blue impedance lines first intersect, is exactly the geometric average characteristic impedance at that frequency.
Also worth noting, the lines intersect at half of the frequency between the peaks and valleys at higher frequencies as well.
Figure 7 Impedance of inductive and capacitive reactance vs. frequency (top) and impedance of a transmission line vs. frequency (bottom) when the farend is open (solid red) compared to when the farend is shorted (solid blue). The intersection of the red and blue lines is exactly the characteristic impedance. Simulated with Pathwave ADS [5].
We can see this more clearly if we replot Figure 7 bottom using a linear scale for the xaxis, as shown in Figure 8. This is a very powerful observation. What this means is that when we measure the impedance half way between a peak and adjacent valley, of either the red or blue plot, it is the characteristic impedance of the transmission line at that frequency.
Thus, only an open or shorted end measurement is all that is needed to determine the characteristic impedance. For example, if we look at the red curve alone, then measure the first resonant null (m14) and adjacent peak (m15), the characteristic impedance (mag(Zopen) is measured exactly at one half the frequency between the two (m16).
Figure 8 Impedance of a transmission line vs. frequency on a linear scale when the farend is open (solid red) compared to when the farend is shorted (solid blue). The intersection of the red and blue lines half way between respective peaks and valleys is the characteristic impedance. Simulated with Pathwave ADS [6].
The first resonant red null and blue peak represent the quarterwave resonant frequency due to open and shorted end. Each respective red null and blue peak following are the odd harmonics of the first quarterwave resonant frequency.
Knowing this, we can now determine the phase or time delay (TD) of the transmission line as being one quarter of the period of the resonant frequency (f_{0}).
Equation 5
Because resonant nulls and peaks occur at the resonant frequency, we can also determine the effective dielectric constant (D_{keff}). Given the speed of light (c) = 11.8 in. per nanosecond, the length of the transmission line (len) in in. and quarterwave resonant frequency (f_{0}), D_{keff} can be determined by:
Equation 6
CMP28 Case Study
Figure 9 Photo of a portion of CMP28 test platform courtesy of Wildriver Technology [8] used for measurement validation.
To test the accuracy of this method, measured data from a CMP28 test platform, shown in Figure 9, was used for measurement validation. Sparameter (s2p) files from 2 inch and 8 inch singleended stripline traces were provided as part of CMP28 design kit courtesy of Wildriver Technologies [8]. The 6inch transmission line segment Sparameter data was deembedded courtesy of AtaiTec Corporation [9].
The characteristic impedance, based on trace geometry and stackup parameters, was modeled in Polar SI9000 [5]. Using D_{k }from data sheet tables @ 10GHz, and correcting for conductor roughness [10], the characteristic impedance predicted was 49.66 Ohms, as shown in Figure 10.
Figure 10 Polar SI9000 fieldsolver [5] characteristic impedance prediction of CMP28 trace geometry.
Touchstone Sparameter DUT files were connected with farend open, shorted, and terminated as shown in Figure 11. The TDR plot, with farend terminated, shows an impedance of 50.57 Ohms, when measured at the initial peak. Then it takes an immediate dip to approximately 50 Ohms before continuing with a slow monotonic rise with some ripples. If the DUT was a uniform trace, with connector discontinuity deembedded, we would not see the initial peak followed by the dip. This signature strongly suggests that the DUT is not uniform and thus it is very difficult to determine the actual characteristic impedance using IPCTM650 test method alone.
But only after taking 2port shunt measurements can we confirm the true characteristic impedance. As shown, Zoavg is 50.68 Ohms where the red and blue curves cross at 122.5 MHz, and confirms the true measurement point in the TDR plot is the initial peak. Both are about 1 Ohm higher compared with 2D field solver results in Figure 10.
If the length of the transmission line simulated above is 6 in. and f_{0 }=248.2 MHz, then TD = 1 ns and D_{keff} = 3.92, using Equation 5 and Equation 6 respectively.
Figure 11 Measured results from a CMP28 test platform design kit, courtesy of Wildriver Technology [8].
But wait a minute. Why is D_{keff} is higher than what was used in the 2D field solver in Figure 10?
One reason is due to process variation of the material and fabrication. The actual D_{keff} is determined by the final thickness of dielectric and the roughness of the copper, which also increases inductance affecting TD [10] [11]. But the main reason is D_{k }is frequency dependent and the value used in the field solver was at 10 GHz, based on laminate supplier’s D_{k}/D_{f} tables.
Since TD, ultimately determines D_{keff}, it does not represent the intrinsic property of the dielectric material. Because D_{keff} varies with frequency, it was calculated at the first resonant null of 248.2 MHz, which is at a much lower frequency for D_{k} than the frequency originally used to select D_{k }in the field solver.
As can be seen in Figure 12, a simulated vs. measured 2port shunt frequency plot, with farend open and shorted, we get exactly the same information, compared to the traditional method used to validate characteristic impedance and D_{keff}.
If we measure the 39^{th} odd harmonic frequency (H) at 9.884GHz for the resonant null closest to 10GHz, equating to the value of D_{k} used in Polar Si9000 2D field solver, D_{keff} can be calculated with Equation 7:
Equation 7
The bottom right plot of Figure 12, shows D_{keff} simulated (blue) vs. measured (red). As we can see, the measured D_{keff} at 248.7 MHz is 3.94; pretty much agreeing with our earlier calculation of 3.92 using Equation 6. Furthermore, when we compare D_{keff} = 3.76 at 9.884 GHz, it agrees with our calculation for the 39^{th} harmonic frequency from Equation 7. The reason there is still a slight difference in D_{keff} is because the added delay due to inductance due to roughness [11] was not factored into the simulated model.
The bottom left is a TDR plot that shows measured impedance (red) vs. simulated (blue) over time. The marker at the beginning of the initial dip (m6) represents the characteristic impedance with highest frequency harmonics included in the incident step edge of TDR waveform. The marker at the end (m16) represents the impedance at twice the TD with high frequency harmonics attenuated due to dispersion of the lossy dielectric and resistance of trace length.
When we measure Zoavg_meas impedance of DUT at 9.884GHz, at the top plot of Figure 12, it agrees pretty well with the simulated and measured TDR plot at the initial step.
Figure 12 Comparison of PI world 2port shunt measurement results for transmission line characteristic impedance and D_{keff} compared to traditional SI world measurement results. Top plot is the 2port shunt simulated vs. DUT impedance measurements at the fundamental and 39^{th} harmonic frequencies. Bottom left is beginning and end impedance measurements on TDR plot. Bottom right measuring equivalent D_{keff} at fundamental and 39^{th} harmonic frequencies.
Summary and Conclusion
Sometimes, when SI and PI worlds collide, we get the best of both worlds. By borrowing a simple 2port shunt impedance measuring technique from the PI world, we have another tool at our disposal to measure true characteristic impedance, TD, and effective D_{k} from a uniformly designed transmission line in the SI world. The advantage is, unlike a TDR measurement, measuring true characteristic impedance using 2port shunt method is not influenced by resistive or dielectric losses.
References

L. Smith, S. Sandler, E. Bogatin, “Target Impedance Is Not Enough,” Signal Integrity Journal, Vol. 1, Issue 1, January 2019; URL: https://www.signalintegrityjournal.com/ext/resources/MEDIAKIT2019/January2019PrintIssue/SIJJanuary2019Issue_eBook_V2.pdf

IPCTM650 Test methods Manual, Number 2.5.5.7, “Characteristic Impedance of Lines on Printed Boards by TDR”, Rev. A, March, 2004

I. Novak, J. Millar, “FrequencyDomain Characterization of Power Distribution Networks,” Artech House, 685 Canton St., Norwood, MA, 02062, 2007.

Pathwave Advanced Design System (ADS) [computer software], Version 2021, URL: http://www.keysight.com/en/pc1297113/advanceddesignsystemads?nid=34346.0&cc=CA&lc=eng

Polar Instruments Si9000e [computer software], Version 2018, URL: https://www.polarinstruments.com/index.html

Keysight Pathwave Advanced Design System (ADS) [computer software], Version 2021, URL: http://www.keysight.com/en/pc1297113/advanceddesignsystemads?cc=US&lc=eng.

E. Bogatin, “Bogatin’s Practical Guide to Transmission Line Design and Characterization for Signal Integrity”, Artech House, 685 Canton St., Norwood, MA, 02062, 2020

Wild River Technology LLC 8311 SW Charlotte Drive Beaverton, OR 97007. URL: https://wildrivertech.com/

AtaiTec Corporation, URL: http://ataitec.com/products/isd/

B. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness“, DesignCon 2017 proceedings, Santa Clara CA.

V. DmitrievZdorov, B. Simonovich, I. Kochikov, “A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics”, DesignCon 2018 proceedings, Santa Clara, CA.

I. Novak et al, “Determining PCB Trace Impedance by TDR: Challenges and Possible Solutions”, DesignCon 2013 proceedings, Santa Clara, CA.

S. Sandler, “Easy trick to measure plane impedance with VNA”, EDN Asia, 2014, URL: https://archive.ednasia.com/www.ednasia.com/STATIC/PDF/201410/EDNAOL_2014OCT21_TEST_TA_01.pdf%3FSOURCES=DOWNLOAD
Practical Modeling of Highspeed Channels
As Dave Dunham from Molex Corp. likes to say, “When designing highspeed serial links beyond 10 GB/s, everything matters”. In order to ensure first time success at these speeds, accurate channel modeling is a prerequisite. This is especially true for long backplane channels.
Although many EDA tools include the latest and greatest models for conductor surface roughness and wideband dielectric properties, obtaining the right parameters to feed the models is always a challenge. Often the only sources are from data sheets alone. But in most cases, the numbers do not translate directly into parameters needed for the EDA tools. So how do we get these parameters?
One way is to follow the design feedback method which involves designing, building and measuring a test coupon, then extracting the parameters through tuning simulation to measurement. Although this method is pretty practical and accurate, a significant amount of expertise and equipment is required to design, build and measure the test coupon, which takes significant amount of time and money.
But, as Eric Bogatin often likes to say, “Sometimes an OK answer NOW! is better than a good answer late.” As a highspeed signal integrity practitioner and backplane architect, I often have to come up with an answer sooner, rather than later because of the impact to time and cost to my clients. And that’s why I have been motivated over the last few years to research and develop simple methodologies to accurately determine parameters to feed into modern EDA tools.
If you went to this year`s EDICon 2017 in Boston, and attended the Highspeed Digital Symposium session, you would have heard me speak on a “Practical Modeling of Highspeed Channels Based on Data Sheet Input”, which was the title of my presentation.
For those of you who could not attend, I have made available an annotated slide deck. You can download a copy from my web site.
What you will learn:

How to use my Cannonball model to determine Huray roughness parameters from data sheet alone

How to determine effective dielectric constant due to roughness from data sheets alone

How to apply these parameters in the latest version of Polar Si9000e Field Solver

How to pull it all together using Keysight ADS software
And this is an example of simulation results compared to measurements you can expect to see:
Via Stubs Demystified
We worry about via stubs in highspeed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot (IL) of the channel. But are all via stubs bad? Well, as with most answers relating to signal integrity, “It depends.”
If one of these frequency nulls happen to line up at or near the Nyquist frequency of the bit rate (i.e. 1/2 of the bitrate), the received eye will be devastated, resulting in a high biterrorratio (BER), or even link failure.
Figure 1 shows simulation results of two backplane channels. On the left are measured SDD21 insertion loss and eye diagram of a 10 GB/s, nonreturntozero (NRZ) signal, with short through vias and long stubs ~ 270 mils. On the right, shows measured SDD21 IL and eye diagram of a channel with long through vias and shorter stubs ~ 65 mils
Because the ¼ wave resonant null occurs at a frequency ~ 4. 4 GHz, this is near the Nyquist frequency for 10 GB/s. As can be seen, the eye is totally closed for the long stub case. But when the shorter stub case is simulated, the eye is open with plenty of margin.
So how does a via stub cause ¼ wave resonance? This question can be explained with the aid of Figure 2. Starting on the left, we see a via with two sections. The through (thru) part is the top portion connecting a device pin to an inner layer trace of a printed circuit board (PCB). The stub portion is the lower portion and is an open circuit.
On the right a sinusoidal signal is injected into the pin at the top of the via and travels along the thru portion until it reaches the junction of the internal trace and stub. At that point, the signal splits. Some of it travels along the trace, and the rest continues down the stub. Once it reaches the bottom, it reflects back up. When it reaches the trace junction, it splits again with a portion traveling along the trace and the rest back to the source.
If f_{ }is the frequency of a sine wave, and the time delay (TD) through the stub portion equals a ¼ wavelength, then when it reflects at the bottom and reaches the junction again, it will be delayed by ½ a cycle and cancels most of the original signal.
Figure 2 Illustration of a ¼ wave resonance of a stub. If f = frequency where TD = ¼ wavelength, then when 2TD = ½ cycle minimum signal received.
Resonance nulls occurs at the fundamental frequency ( f_{o}) and at every odd harmonic. If you know the length of the stub (in inches) and the effective dielectric constant (Dk_{eff}), surrounding the via hole structure, the resonant frequency can be predicted by:
Equation 1
Where: f_{o} is the ¼ wave resonant frequency (GHz); c is the speed of light (~11.8 in/ns); Stub_length is inches.
You will find that Dk_{eff} is not the same as the bulk Dk published in laminate manufacturers’ data sheets. It is typically higher. A higher Dk_{eff} increases phase delay through the via resulting in a lower resonant frequency.
One reason is excess capacitance from the via pads as well as the via barrel’s proximity to the clearance hole openings (also known as antipads) in plane layers. The other is because of the anisotropic nature of the laminate material.
For the example in Figure 1, the ¼ wave resonant frequency of the long via stub is ~ 4.4 GHz. With a stub length of ~ 270 mils, this gives a Dk_{eff} of 6.16, which is considerably higher than the published bulk Dk of 3.65. When you model a via in an electromagnetic (EM) 3D field solver, it automatically accounts for the excess capacitance, but you will still need to compensate for the anisotropic nature of the dielectric.
A material is anisotropic when there are different values for parallel (xy) vs perpendicular (z) measured values for dielectric constant. Dielectric constant and loss tangent, as published in manufacturers’ data sheets, report perpendicular measured values. For FR4 fiberglass reinforced laminates, anisotropy can range from 15% 25% higher. The bad news is these numbers are not readily available from data sheets.
For differentially driven vias with plane layers evenly distributed throughout the entire stackup, Dk_{eff} can be roughly estimated by:
Equation 2
Where: Dk_{xy} is the dielectric constant adjusted for anisotropy (15%25% higher); Dk_{z} is the bulk dielectric constant from data sheets; s is viavia spacing; drillØ is drill diameter; H and W are antipad shape dimensions as shown in Figure 3 .
Figure 3 Antipad parameters for Equation 2.
The effects of via stubs can be mitigated by: using blind or buried vias; backdrilling; or by using thru vias only (i.e. from top layer to bottom layer). Practically, the shortest stub that can be achieved by backdrilling is on the order of 5 to 10 mils.
As a rule of thumb, we usually strive to have an interconnect bandwidth (BW) to be five times the Nyquist frequency of the bitrate. Since a ¼wave resonant null behaves somewhat like a notch filter, depending on the highfrequency rolloff due to Qfactor, frequencies near resonance will be attenuated. For that reason a good rule of thumb to follow is making sure the first null should occur at the 7^{th} harmonic, or higher, of the Nyquist frequency to maintain the integrity of the 5^{th} harmonic frequency component that makes up the risetime of a signal.
With this in mind, for a given baudrate (Baud) in GBd, the maximum stub length (l_{max}), in inches can be estimated by:
Equation 3
For NRZ signaling, the baudrate is equal to the bit rate. But for pulseamplitude modulation (PAM4) signaling, which has 2 symbols per bit time, the baudrate is ½ of that. Thus a 56 GB/s PAM4 signal has a baudrate of 28 GBd, and the Nyquist frequency is 14 GHz, which happens to be the same as 28 GB/s NRZ signalling.
Figure 4 presents a chart of maximum stub length vs baudrate based on Equation 3, using a Dk_{eff} = 6.16 (blue) vs 3.65 (red). It shows us the higher the baudrate, the more the stub length becomes an issue, especially past 10 GBd. We also get a feel for the sensitivity of stub length to Dk_{eff }. Even though there is ~ 70% difference in Dk_{eff}, there is only ~ 30% delta in stub lengths for the same baudrate. This means that even if we use the bulk Dk published in data sheets, we are probably not dead in the water.
If the respective stub length is greater than this, it does not mean there is a show stopper. Depending on how much longer means the eye opening at the receiver will be degraded and we lose margin. We see this by the example in Figure 1. Even though the stub lengths in the channel were almost double the value at 10 GBd from the chart, there is still plenty of eye opening.
Figure 4 Chart showing estimated maximum stub length vs baudrate with Dk_{eff} of 6.16 (red) vs 3.65 (blue) based on Equation 3
To further explore design space and test out the rule of thumb, a generic circuit model was built using Keysight ADS with the ability to vary the via stub lengths
Referring to the chart, at 28 GBd, the maximum stub length should be 12 mils, assuming a Dk_{eff} of 6.16. Figure 5 shows simulation results for NRZ signalling. As can be seen, there was a difference of only 17 mV in eye height (1.5%), and no extra jitter for 12 mil stubs compared to 5 mil stubs.
Figure 5 Eye diagrams comparison with BER at 10E12 for stub lengths of 5 mils vs 12 mils. Modeled and simulated with Keysight ADS.
But if we use the exact same channel model, and use the generic PAM4 IBIS AMI model from Keysight Technologies, we can see the results plotted in Figure 6. On the left are the eye openings with 5 mil stubs and the right with 12 mil stubs. In this case, there was an average reduction of ~7 mV (6%) in eye heights, and 0.24 ps (2%) in eye widths at BER 10E12 across all three eyes.
Figure 6 PAM4, 28 GBd (56 GB/s) eye height and width comparison at BER of 10E12 for 5 mil vs 12 mil stub lengths. Modeled and simulated with Keysight ADS.
Because PAM4 signalling has three smaller eyes, that are onethird the size of an NRZ eye for the same amplitude, it is more sensitive to channel impairments. From the above examples, we can see NRZ had only 1.5% reduction in eye height compared to 6% for PAM4. Similarly there was no increase in jitter for NRZ compared to 2% increase for PAM4 when stub lengths changed from 5 mils to 12 mils.
What this says is maintaining a BW to 5 times Nyquist rule of thumb, when estimating via stub lengths, is quite conservative for NRZ signalling. There is almost the same BW as the channel with 5 mil stub, which was the original objective. But because PAM4 is more sensitive to impairments, it shows there is less margin.
In summary then, rules of thumb and related equations are a good way to reinforce your intuitions or to give you an answer sooner rather than later. They help you know what to expect before you take any measurements or perform any simulations. But they should never be used to sign off on any highspeed design.
Because every system will have different impairments affecting BER, the only way to know how much margin you have is by modeling the via with a 3D EM field solver, based on the actual stackup and simulating the entire channel complete with crosstalk, if margins are tight. This is even more critical for data rates above 10 GBd.
So to answer the original question, “are all via stubs bad”? Well, the answer is it still depends. For NRZ signalling, there is more leeway than for PAM4. But you now have a practical way to quickly quantify the answer if you know the stub length, baudrate and delay through the via.
Obsessions with Conductor Surface Roughness – What’s the Dk Because of it?
You know you have an obsession when you are flying 6 miles over Colorado; look out your window at the beautiful scenery; and all you can think about is how the rocky mountain topology reminds you of conductor surface roughness! Well call me obsessed because that’s exactly what I thought on my way to DesignCon 2017 in Santa Clara, CA.
For those of you who know me, you know that I have been researching practical methods to model conductor surface roughness, and its effect on insertion loss (IL). I have presented several papers on the subject over the last couple of years. It’s one of my pet projects. This year, at DesignCon, I presented a paper titled, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness” .
Everyone involved in the design and manufacture of printed circuit boards (PCBs) knows one of the most important properties of the dielectric material is the relative permittivity (ε_{r}), commonly referred to as dielectric constant (D_{k}). But in reality, D_{k} is not constant at all. It varies over frequency as you will see later.
We often assume the value reported in manufacturers’ data sheets is the intrinsic property of the material. But in actual fact, it is the effective dielectric constant (D_{keff}) generated by a specific test method. When you compare simulation against measurements, you will often see a discrepancy in Dkeff and IL, due to increased phase delay caused by surface roughness. This has always bothered me. For a long time I was always looking for ways to come up with Dkeff from data sheet numbers alone. Thus the obsession and motivation for my recent research work.
Since phase delay, also known as time delay (TD), is proportional to Dkeff of the material, my theory was that the surface roughness profile decreases the effective separation between parallel plates, thereby increasing the electric field (efield) strength, resulting in additional capacitance, which accounts for an increase in effective D_{k} and TD.
The main focus of my paper was to prove the theory and to show a practical method to model Dkeff and TD due to surface roughness. By referencing Gauss’s Law for charged parallel plates, I confirmed mathematically, and through simulation, how the dielectric thickness and permittivity are interrelated to efield and capacitance. I also revealed how the 10point mean (R_{z}) roughness parameter can be applied to finally estimate effective Dkeff due to roughness. Finally I tested the method via case studies.
In his book, “Transmission Line Design Handbook”, Wadell defines D_{keff} as the ratio of the actual structure’s capacitance to the capacitance when the dielectric is replaced by air.
D_{keff} is highly dependent on the test apparatus and conditions of how it is measured. There are several methods used in the industry. One method that is commonly used by many laminate suppliers is called the clamped stripline resonator test method. It is described by IPCTM650, section 2.5.5.5, Rev C.
In short, this method rapidly tests dielectric material for permittivity and loss tangent, over an Xband frequency range of 812.4 GHz, in a production environment. It does not guarantee the values are accurate for design applications.
Here’s why:
The measurements are made under stripline conditions, using a carefully designed resonant element pattern card, made out of the same dielectric material to be tested. The card is sandwiched between two sheets of unclad dielectric material under test. The whole structure is then clamped between two large plates, lined with copper foils that are grounded.
Since the resonant element pattern card and material under test are not physically bonded together, there are small air gaps between the various layers affecting measured results. These air gaps are caused in part by:
 Removing the copper from the material under test, leaving the bare substrate, complete with the micro void imprint of the copper roughness.
 The air gap between resonant element pattern card and material under test, due to the copper thickness of the etch pattern.
 The roughness profile of the copper, on the resonant element pattern card and fixture’s grounded foil reference planes, are different than would be in practice, unless the same foil type is used.
If D_{keff} and R_{z} roughness parameters from the manufacturers’ data sheets are known, then the effective D_{k} due to roughness (D_{keff}_{_rough}) of the fabricated core laminate can now be easily estimated by:
Where: H_{smooth} is the thickness of dielectric from data sheet; R_{z} is 10point mean roughness from data sheet; and D_{keff} is the D_{k} from data sheet.
With reference to Figure 1, using D_{keff} with rough copper model, as shown on the left, is equivalent to using D_{keff}_{_rough}, with smooth copper model, as shown on the right. Therefore all you need to do is use D_{keff}_{_rough} for impedance calculations, and any other numerical simulations based on surface roughness, instead of D_{k} published in data sheets.
It is as simple as that.
Figure 1 Effective D_{k }due to roughness model. Using D_{keff} with rough copper model (left) is equivalent to using D_{keff}_{_rough }with smooth copper model (right).
For example, one case study I presented used measurements from a CMP28 modeling platform from Wild River Technology. The PCB was fabricated with FR408HR material and reverse treated foil (RTF). Keysight EEsof EDA ADS software was used for modeling and simulation. The results are shown in Figure 2.
The left graph shows results when data sheet values for core and prepreg were used. D_{keff} measured (red) was 3.761, compared to simulated D_{keff} (blue) of 3.626, at 10 GHz. This gave a delta of ~ 4%. But when the D_{keff_rough} was used for core and prepreg the delta was within 1%.
Figure 2 Measured vs simulated D_{keff} using FR408HR data sheet values for core and prepreg (left) and using D_{keff_rough} (right). Modeled and simulated with Keysight EEsof EDA ADS software.
The paper shows in more detail how Equation 1 was derived, based on Gauss’ Law. In addition, I show how IL and phase delay is also improved when D_{keff_rough} is used instead of data sheet values. You can download the paper titled, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”, and other papers on modeling conductor loss due to roughness from my web site.
The Poor Man’s PCB Via Modeling Methodology
You are a backplane designer and have been assigned to engineer a new highspeed, multigigabit serial link architecture from several line cards to multiple fabric switch cards across a backplane. These links must operate at 6GB/s day one and be 10GB/s (IEEE 802.3KR) ready for product evolution. The schedule is tight, and you need to come up with a backplane architecture to allow the rest of the program to progress on schedule.
You come up with a concept you think will work, but the backplane is thick with over 30 layers. There are some long traces over 30 inches and some short traces of less than 2 inches between card slots. There is strong pressure to reuse the same connector you used in your last design, but your gut tells you its design may not be good enough for this higher speed application.
Finally, you are worried about the size and design of the differential via footprint used for the backplane connectors because you know they can be devastating to the quality of the received signal. You want to maximize the routing channel through the connector field, which requires you to shrink the antipad dimensions, so the tracks will be covered by the reference planes, but you can’t easily quantify the consequences on the via of doing so.
You have done all you can think of, based on experience, to make the vias as transparent as possible without simulating. Removal of nonfunctional pads on the inner layers, and planning to backdrill the connector via stubs will help, but is it enough? You know in the back of your mind the best way to answer these questions, and to help you sleep at night, is to put in the numbers.
So you decide to model and simulate the channel. But to do so, you need accurate models of the vias to plug into your favorite circuit simulator. But how do you get these? You have heard it all before; “for highspeed, the best way to model a via is with a 3D electromagnetic field solver”. Although this might be true, what if you don’t have access to such a tool, because the cost is more than your company wants to spend, or because you don’t have the expertise nor the time to learn how to build a model you can trust to make a timely decision?
On top of that, 3D field solvers typically produce Sparameter behavioral models. Since they represent only one sample of a given construction, it is impossible to perform whatif, worst case, min/max analysis with a single behavioral model. Because of this, many iterations of the model are required; causing further delay in getting your answer.
A circuit model on the other hand, is a schematic representation of the actual device. For any physical structure, there can be more than one circuit model to describe it. All can give the same performance, up to some bandwidth. When run in a circuit simulator, it predicts a measurable performance of the structure. These models can be parameterized so that worst case analysis can be explored quickly.
The problem with a circuit model is that you often need a behavioral model to calibrate it, or need to use analytical equations to estimate the parameters. But, as my friend Eric Bogatin often says, “an OK answer NOW! is better than a great answer late”.
In the past, it was next to impossible to develop a circuit model of a differential via structure without a behavioral model to calibrate it. These behavioral models were developed through empirical formulas, measured data, or through the use of 3D EM field solvers.
Now, there is another way. I have nicknamed it, “The Poor Man’s PCB Via Modeling Methodology”. Here’s how it works.
Anatomy of a Differential Via Structure:
An example of a differential via structure, shown in Figure 1, is representative of vias used to connect surface mounted components or backplane connectors to internal layer traces.
The via barrel is a plated through hole extending the entire length of a PCB stackup. The outside diameter equals the drill diameter. The inside diameter is the finished hole size (FHS) after plating. Pads are used on layers to ensure there is sufficient copper for track attachment after drilling operation. When used in this fashion, they are referred to as functional pads. Antipads are the clearance holes in the plane layers allowing the via barrel to pass through them without shorting.
The via portion is the length of the barrel connecting one signal layer to another. It is often referred to as the through via since it is part of the signal net. The stub portion is the rest of the barrel extending to the outer layer of the PCB. In highspeed designs, a good rule of thumb to remember is that a via stub should be less than 300mils/BR in length; where BR is the bit rate in Gb/s.
Building a Simple Scalable Circuit Model:
On close examination of Figure 2, a differential via structure can be represented by a twinrod transmission line geometry with excess capacitance (shown in red) distributed over its entire length. The smaller the antipad diameter, the greater the excess capacitance. This ultimately results in lower via impedance, causing higher reflections.
In all highspeed serial link designs, it is common practice to remove all nonfunctional pads and to maximize the antipad clearance as much as practically possible. Oval antipads are often used in this regard to further mitigate excess via capacitance.
Figure 3 illustrates the equivalent circuit for a differential via that could be used in a channel topology simulation. Here it is modeled with Keysight ADS software using a coupled line transmission line model for each section. This equivalent circuit model can be scaled for any combination of layer transitions and integrated in any channel simulation scenario.
Since the crosssection of the via is constant throughout its length, the differential impedance of all sections of the via are the same. We only need to know the physical length of each segment and the effective dielectric constant (Dkeff) to get the time delay of each segment.
When driven differentially, the oddmode parameters of each via are of major importance. Since the evenmode parameters have no impact on differential performance, both odd and evenmode parameters are set to the same values in the model.
The challenge then is to calculate the odd mode impedance (Zodd), representing the individual via impedance (Zvia), of a differential via structure and the effective dielectric constant (Dkeff) based on its geometry. Simple equations are used to determine these parameters.
Developing the Equations:
Antipads can vary in size and shape. They can be anything from round, to oval around each via, or even a large oval surrounding both vias as illustrated in Figure 4. Square, or rectangular variations (not shown) are similar.
Referring back to Figure 2, we see the structure of each via looks a lot like two coaxial transmission lines with the inner layer reference planes acting like a shield. Electrostatically this is a good approximation, but because the shield is not continuous, the magnetic fields are not contained like they are in a coaxial structure. Instead they behave more like magnetic fields around a twinrod structure.
So here lies the secret in modeling a differential via. We take the best of both geometries to calculate the oddmode impedance representing Zvia.
For inductance, we will use the oddmode inductance formula from the twinrod transmission line geometry to calculate Lvia :
Referring to Figure 4, we then calculate the oddmode capacitance for Cvia derived from an approximate formula for an elliptic coaxial structure developed by M.A.R. Gunston in his book, “Microwave Transmission Line Impedance Data” . In the original formula, both shield (W’+b) and inner conductor (w+t) are elliptical in shape and are dimensioned as shown. When the antipads are circular, then ln[(W’+b) /(w+t)] reduces to just ln[b/t)]; which is the denominator in the Coax equation. If we use Gunston’s approximation to calculate Cvia, then the equation becomes:
Since conventional FR4 type laminates are fabricated with a weave of glass fiber yarns and resin, they are anisotropic in nature. Because of this, the dielectric constant value depends on the direction of the electric fields. In a multilayer PCB, there are effectively two directions of electric fields.
The one we are most familiar with has the electric fields perpendicular to the surface of the PCB; as is the case of stripline shown here in Figure 5. The dielectric constant, designated as Dkz in this case, is normally the bulk value of the dielectric specified by the laminate manufacturer’s data sheet.
The other case has the electric fields running parallel to the surface of the PCB, as is the case when a signal propagates through a differential via structure. In this situation, the dielectric constant, designated as Dkxy, can be1520% higher than Dkz .
Therefore, assuming a nominal 18% anisotropic factor, Dkxy = 1.18(Dkz)
Now that we have defined Lvia, Cvia and Dkavg, Zvia can be estimated using the following equation:
But we are not finished yet. We still need to determine the effective dielectric constant (Dkeff) in order to accurately model the delay through the via and stub portion. Without the correct value, the quarterwave resonant nulls in the insertion loss plot, due to the stub length, cannot be accurately predicted. The value for Dkeff is determined based on how much the via’s oddmode impedance is decreased due to the distributed capacitive loading of the antipads.
To help us with this task, we start with the twinrod formula. The oddmode impedance (Zodd) is half the differential impedance (Ztwin), and is expressed as:
By substituting Equation 1 for Zodd into the equation above, and solving for Dkeff we eventually come up with the following equation:
Validating the Model:
A simple 26 layer test vehicle was fabricated to compare the accuracy of the differential via circuit model to real vias. It consisted of two differential via pairs separated by 6 inches of 100 Ohm stripline differential pairs. Three sample via structures representing long, medium and short via stubs, as summarized in Figure 6, were measured using an Agilent N5230A VNA.
The differential vias had the following common parameters:
Via drill diameter; D = 28 mils
Center to center pitch; s = 59 mils
Oval antipads= 53 mils x 73 mils
Dk of the laminate = 3.65
Anisotropy in Dkxy = 18%
Zvia = Zstub = 31.7 Ohms (per Equation 1)
Dkeff = 6.8 (per Equation 2)
Agilent ADS software was used to model and facilitate simulation correlation of the measured data as captured in Figure 7. This simple model accounts for the discontinuity of the long through section and the long stub section. The top half is the measured channel using an Sparameter file. The bottom half is a circuit model of the channel. Since the probes were not calibrated out, they are part of the device under test. The balun transformers are used to facilitate the display of the Sparameter and TDR results.
The comparison between the measured and simulated results of the insertion loss and TDR response for the three via stub cases using this simple approximation methodology is summarized in Figure 8. The insertion loss plots, in the frequency domain, are shown on the left, while the TDR plots are shown on the right.
The resonant nulls in the SDD21 plots are due to the stub lengths. As you can see, the longer the stub, the lower the resonant frequency null. If this null happens at the Nyquist frequency of the bit rate, the eye will be totally closed. This is why we backdrill them out after the board has been fabricated.
The simulation correlation is excellent up to about 12 GHz. The TDR plots show excellent impedance matching and delay for all three cases, while the simulated stub resonant frequencies match the measured frequencies very well. As you can see, these simple approximations for Dkeff and Zvia are perfectly adequate in providing a quick and accurate circuit model for differential through hole vias typically used in backplane applications.
Summary:
As illustrated, a simple twinrod model (Figure 2) is used as the basis for a practical differential via circuit modeling methodology. By using Equation 1 and Equation 2, you can quickly determine the oddmode impedance and effective dielectric constant needed for the circuit model.
Of course, you should use this methodology first as a rough starting point to quickly estimate the performance of your differential via design. If your worst case topology simulations show the performance is marginal, then it is worth while to invest the time and money to develop a 3D full wave model to perform a more accurate analysis.
On the other hand, if you find this approximation shows the vias have little impact on the channel performance, it may be of greater value for you to invest your time and money in resolving other critical issues with your design.
Try it the next time you are losing sleep over your design challenges.
For more Information:
If you liked this design note and want to learn more, or get more details on this innovative via modeling methodology, you can visit my web site, LAMSIM Enterprises.com , and download a copy of the white paper I wrote along with Eric Bogatin and Yazi Cao titled, “Method of Modeling Differential Vias” .
While you are there, feel free to investigate my other white papers and publications.
If you would like more information on our signal integrity and backplane services, or how we can help you achieve your next highspeed design challenge, email us at: info@lamsimenterprises.com.
UPDATE: In collaboration with Saturn PCB, I am pleased to announce my differential via equations above have been incorporated in a new impedance calculator available now in Saturn PCB Tool Kit software suite.
PCB Vias – An Overview
Vias make electrical connections between layers on a printed circuit board. They can carry signals or power between layers. For backplane designs, the most common form of vias use plated through hole (PTH) technology. They connect the pins of connectors to inner signal layers. A PTH via is formed by drilling a hole through the layers to be connected and then copper plating it.
High Density Interconnects (HDI) is another via technology used to form very small vias where drilling holes, using a conventional drill bit, is impractical. Also known as microvias, this technology creates the hole with a laser before plating.
Via Aspect Ratio
Via aspect ratio is defined as the ratio of the circuit board thickness to the smallest unplated drilled hole diameter. It is an important metric you need to be aware of when specifying the minimum via hole size for your design, and designing your stackup. For example, an unplated via with a drill diameter of 0.020 inches and a board thickness of 0.200, would have an aspect ratio of 10:1. The smaller the aspect ratio, the more consistent the plating is throughout the length of the via. It is desirable to have 2 mil plating thickness for the via walls. Large aspect ratio vias tend to have more plating at each end compared to the middle. This increases the chance of cracked via barrels due to zaxis expansion while soldering.
An aspect ratio of 6:1 pretty much ensures your board can be fabricated anywhere. Most highend board shops have the capability of fabricating boards with 10:1 aspect ratio; for drill diameters of less than 0.020 inches. Practically, the smallest drill diameter used for a through holed via is 0.013 inches. At 10:1, the maximum board thickness would be 0.130 inches.
For drill diameters larger than 0.020 inches, the max aspect ratio can be anywhere from 15:1 to over 20:1; depending on the board shop. Since backplane via hole size is driven by the compliant pins of the connector, it is best to work with your board shop to determine the maximum board thickness they can fabricate with the minimum finished hole size (FHS) specified in the design.
Via Configurations
The following lists the various via configurations you might expect to find on any multilayer PCB design:

Stub Via

Through Via
 Blind or Microvia

Buried Via

Backdrilled Via
Stub Via
The Stub Via is the most common via configuration found in PCBs today. As illustrated, there are two variations; Stub Via A and Stub Via B.
For the Stub Via A example, it shows the through portion starting from the top layer and ending at some inner layer. The stub portion is the remaining portion continuing from the inner layer junction to the bottom layer.
The Stub Via B example shows the through portion originating from one internal signal layer and terminating on another internal signal layer. In this scenario, there are two stubs. The first stub is from the first internal layer junction to the top layer; the second stub is from the second internal layer junction to the bottom layer.
Through Via
Through vias are the oldest and simplest via configurations originally used in 24 layer PCB designs. Since the signals originate and terminate from the outer layers of the PCB, there are no stubs. In multilayer PCB applications, they are an inexpensive way to eliminate the resonance effects caused by stubs where other mitigation techniques are not practical or are too expensive.
Blind/Buried Via
Blind and buried vias are just like any other via, except they do not go all the way through the PCB. A Blind Via connects one or more internal layers to only one external layer. Controlleddepth drilling is used to form the holes prior to plating.
A buried via, on the other hand, is a plated hole which is completely buried within the board. It connects one or more internal layers and does not connect to an external layer. Using buried via technology is costly because the inner layers being interconnected need to be fully fabricated and plated before final lamination of the entire PCB.
A microvia is a form of blind via. Because the holes are so small (0.006 inches or less), they are formed using lasers, and cannot penetrate more than one or two layers at a time. They are most commonly used in highdensity PCB designs like cell phones, or in FPGA and custom ASIC chip packaging.
Backdrilled Via
High speed pointpoint serial link based backplanes are often thick structures; due to the system architecture and cardcard interconnect requirements. Backdrilling the via stub is common practice on thick PCBs to minimize stub length for bitrates greater than 3Gb/s.
Backdrilling is a process to remove the stub portion of a PTH via. It is a postfabrication drilling process where the backdrilled hole is of larger diameter than the original PTH. This technology is often used instead of blindvia technology to remove the stubs of connector vias in very thick highspeed backplane designs. State of the art board fabrication shops are able to backdrill to within 8 mils of the signal layer to keep, so there will always be a small stub portion attached to the via.
Backdrilling is not without limitations. Smaller vias and tighter pitch driven by large pin count BGA packages makes backdrilling impractical in these applications; due to drill bit size and tolerance issues. Fortunately, smaller via diameters limit the maximum PCB thickness due to aspect ratio; thereby limiting the length of the stub to the board thickness. Careful planning the highspeed layers within the stackup is one way to control stub length.
We worry about stubs in highspeed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot of the channel. If one of these frequency nulls happen to line up at or near the Nyquist frequency of the bit rate, the received eye will be devastated resulting in a high biterrorrate; even link failure. A shorter stub length means these resonances will be pushed out further in frequency; ideally past the 5th harmonic of the Nyquist frequency as a rule of thumb.
Rules of thumb, in general, are no substitute for actual modeling and simulation. You should never depend on them to signoff the final design; but you can use them to gain some intuition before hand. With that in mind, you can estimate the maximum stub length in inches using the following equation:
Where:
L _{Stub_max }= maximum stub length in inches.
Dkeff = effective dielectric constant of the material surrounding the via hole structure.
BR = Bit rate in GB/s.
For example, the maximum stub length at 5GB/s should be less than 0.120 inches in FR4 material with a Dkeff of 4.0 to ensure the first resonant frequency null is greater than 5 times the Nyquist frequency of the bit rate. If the stub length is greater than this, it does not mean the design will not work at 5GB/s. Depending on just how much longer it is means there will be less than optimum eye opening at the receiver.
If you know the length of the stub, you can predict the fundamental resonant frequency, using the following equation:
Where:
Stub_len = stub length in inches.
f_{o} = fundamental resonant frequency in GHz
So, using the same Dkeff of 4.0, and stub length of 0.120 inches, we calculated in the above example, the first resonant frequency null would occur at approximately 12.3 GHz. If we assume this is the 5th harmonic, then the Nyquist frequency is approximately 2.5GHz and the bit rate is 5Gb/s; which is where we started.