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A Tale of Two Data Sheets Part 2: Making Sense of “Design” Dk

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Originally published in Signal Integrity Journal, May 31, 2022

In part one, “A Tale of Two Data Sheets”, I explained how air entrapment, due to IPC-TM-650- test method manual [7], is the primary reason for effective dielectric constant (Dkeff) and phase delay discrepancies between simulation and device under test (DUT) measurements. Entrapped air of the test fixture results in a lower Dk published in laminate suppliers’ Dk/Df tables than what would be measured in a real printed circuit board (PCB) application. This is because in a real PCB, everything is bonded together with no air entrapment, as shown in a cross-section view of Figure 1.


Figure 1. Example of foil bonded to core or prepreg dielectric. Rz is 10-point mean roughness of foil as measured by a profilometer. Hsmooth is the thickness of the dielectric as if the foil was removed.

When copper foil with the same Rz roughness is bonded to each side of the core or prepeg, Dkeff is determined heuristically from published Dk by this simple correction factor [1]:

Equation 1.



Hsmooth is the thickness of the dielectric as if the foil was removed

Dk = Dielectric constant published in laminate suppliers’ Dk/Df tables

Rz = 10-point mean equivalent to Rz(JIS) or Rz(DIN) published in foil suppliers’ data sheets. This is not to be confused with Rq, which is RMS value of roughness.

Rogers Corporation [4] understands this. That’s why they provide the “design” Dk in addition to their bulk Dk, as measured by TM650 clamped stripline resonator test method [7]. Design Dk is an average number using a differential phase length method from several different tested lots of material and on the most common thickness. This method is based on measuring phase difference from two identical microstrip transmission line geometries, of different lengths on the same panel. Because this is a real microstrip application, the dielectric is fully bonded to the copper and there is no air entrapment. Knowing the phase and length difference, the effective Dk is empirically determined.

The accuracy of the resultant effective Dk depends on several factors like:

    • fixture design
    • length ratio between two transmission lines
    • material thickness of the sample under test
    • the thickness of the copper
    • actual roughness of the foil on the microstrip circuit.

In lieu of actual Dk/Df tables, Rogers provides a handy impedance calculator as shown in in the RO4003C example of Figure 2. There are three Dk options available to use:

    • Z-axis bulk Dk
    • Dk values for specific frequencies
    • Dk values for characteristic impedance

The first radio button, as shown in Figure 2, gives the z-axis bulk Dk value of 3.55, as measured by TM650 test method manual. However, the value does not change when different frequencies are selected. This makes the number suspect since clearly design Dk does change over frequency. Thus this number can be considered equivalent to marketing data sheets, and should not be used. 

When the middle radio button is selected, a Dk value for a specific frequency is displayed, which corresponds to a frequency entered in the lower right frequency box of Figure 2. This is the most useful option, since it allows the user to choose the right design Dk at whatever frequency they choose for their application, including characteristic impedance. This option already factors in the foil roughness effect, so no correction factor is needed to use in your simulator.

The last radio button selects a Dk for characteristic impedance calculation. It is a “design” Dk with yet a different Dk. Similar to the Bulk Dk option, it does not change over frequency. For any simulation tool other than the Rogers’s calculator, Bulk Dk and Dk values for characteristic impedance values should not be used. 


Figure 2. Example of Rogers Corporation impedance calculator. For an 8-mil thick RO4003C dielectric, bulk Dk is 3.55 while design Dk over frequency is shown in bottom left window.

Under the information tab, the user can download design Dk over frequency, for a specified thickness, shown in the bottom left window of Figure 2. This data can be selected and copied to the clipboard and pasted into a spreadsheet for further processing.

Figure 3 plots design Dk vs. frequency for various thickness from 8 mils to 60 mils for RO4003C material. As can be seen, design Dk is not constant over frequency and furthermore it is different for different thicknesses, mainly due to the roughness of the foil that is already included in the measurement.

Thinner materials have a higher design Dk than thicker materials for the same roughness of foil. This is because when the foil teeth protrude into a thin dielectric material, there is a higher concentration of e-fields, resulting in higher capacitance between top and bottom copper layers. For thick dielectrics the foil teeth have less of an impact on capacitance and thus Dkeff, as described mathematically by Equation 1.

Since the roughness of the foil does not significantly influence the design Dk for thick laminates, we can assume the bulk Dk is roughly equivalent to design Dk over frequency for the 60-mil laminate. 


Figure 3. Design Dk vs. frequency for various thickness of RO4003C from 8 mils to 60 mils mainly due to the roughness of the foil. Thinner material has a higher design Dk than thicker material, for the same roughness of foil.

Heuristically, we can rearrange Equation 1 and estimate the Rz roughness of the foil used on RO4003C laminate to be 6.302 μm from Equation 2.

Equation 2.



Hsmooth is the thickness of the 8 mil (203 μm) laminate

DkBulk = 3.55 at 60 GHz for 60 mil (1524 μm) laminate

Dkeff = design Dk of 8 mil (203 μm) laminate at 60 GHz

A cross-section sample from a time domain reflectometry (TDR) demo board, courtesy of Picotest [6], was measured and is shown in Figure 4. The TDR demo board was fabricated with 8-mil thick Rogers RO4003C core laminate and cladded with 2 Oz copper foil.

Five highlighted random sample lengths of copper roughness, labeled Sample 1 to Sample 5 of Figure 4, were analyzed. The total length of each respective sample was then partitioned into five equal sections, similar to the blow-up picture of Sample 1, to measure the maximum peak to valley height of each section. The five measurements of each sample length were then averaged to determine the Rz roughness, as described under IPC TM650 2.2.17A [8] and shown in the table of Figure 4.

The mean value of Rz for the five samples was 6.176 μm with a standard deviation (SD) of 1.090 μm. This compares favorably with the estimated roughness of 6.302 μm, determined from Equation 2.


Figure 4. A cross-section sample from a Rogers RO4003C based TDR demo board, courtesy of Picotest [6], used to determine Rz roughness of the foil.

When we use the actual roughness measured from Figure 4 and Equation 1, we can then calculate Dkeff  at 60 GHz for different thicknesses, shown in Table 1. As can be seen there is, less than 1% delta compared with design Dk reported from the calculator!

Table 1. Comparison of Roger’s Design Dk vs. Dkeff when simple correction factor applied to Bulk Dk at 60 GHz.



Bulk Dk
@ 60 GHz

Design Dk
@ 60 GHz


@ 60GHz












































Rogers Corporation provides a handy calculator in lieu of Dk/Df tables in which “design” Dk values over frequency can be used directly without correcting for roughness. When an actual cross-section was analyzed, there was excellent correlation from corrected Dkeff using heuristic methods compared to design Dk from the calculator. Therefore, “design” Dk should be used for impedance modeling and PCB stackup design when using Rogers laminates.


    1. B. Simonovich, “A Tale of Two Data Sheets and What You Need to Know About Dielectric Constant (DK),” Signal Integrity Journal article, April 2022.
    1. Isola Group, 6565 West Frye, Chandler, AZ 85226.
    1. Rogers Corporation, 2225 W. Chandler Blvd., Chandler, AZ 85224.
    1. J. Coonrod, “Managing PCB Materials: Dielectric Constant (Dk)”, Rogers Corporation, Blog Article, Sep 11, 2018.
    1. Picotest, Phoenix, AZ 85085.
    1. Bereskin, A. B. “Microwave Dielectric Property Measurements”, Microwave Journal, vol. 35, no.7, pp. 98 – 112.

Written by Bert Simonovich

June 11, 2022 at 12:09 pm

A Tale of Two Data Sheets

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Originally published SI Journal April 26, 2022

When doing printed circuit board (PCB) stackup and signal integrity (SI) impedance modeling, we need to get the dielectric material properties from the right sources. One important parameter for accurate impedance modeling is relative permittivity (εr) of the dielectric material, otherwise known as dielectric constant (Dk). The best source is from laminate suppliers’ data sheets. Though there is an issue with these I like to think of as, “a tale of two data sheets.”

Marketing data sheets, like the example shown in Figure 1 [6], are easily found on laminate suppliers’ websites. They are meant for quick comparison of dielectric properties to narrow your search for the right laminate for your application. Dielectric properties on marketing data sheets include mostly thermal and mechanical properties, which are important for the physical structure of the material and how it will perform with other material properties in the stackup during processing.

But marketing data sheets are not representative of what is needed to design an actual stackup, or to do impedance and SI loss modeling. Depending on glass style, resin content, thickness, Dk, and dissipation factor (Df) will be different for different cores and prepreg thicknesses for the same laminate. Marketing data sheets usually only report a typical Dk/Df at fifty percent resin content and two or three frequency points. Thickness is not specified. Furthermore, Dk and Df are not constant over frequency. So, using numbers from these data sheets will lead to inaccurate impedance and phase delay results.

Figure 1. Example of a “Marketing” data sheet easily obtained from laminate supplier’s web site. Source Isola Group [6].

Instead, for transmission line modeling, one needs to use the same Dk/Df table data sheets PCB fabricators use to build the stackup. An example Dk/Df table is shown in Figure 2. Dk/Df tables provide the actual core and prepreg thicknesses, resin content, and Dk/Df for the different glass styles, over different frequencies. Depending on the stackup, a combination of thicknesses is often needed to meet impedance requirements. Each thickness will have a different Dk value.

In the example of Figure 2, Dk varies from 2.92 at 10 GHz for 1080 glass style to 3.19 at 10 GHz for 2116 glass style. This represents a Dk variation of -3.3% to 5.6% when compared to a Dk of 3.02 at 10 GHz specified in Figure 1.  

Figure 2. Example of a typical “Engineering” data sheet showing Dk/Df table for different glass styles and resin content over frequency. Source Isola Group [6].

Many engineers assume Dk published is the intrinsic property of the material. But, in fact, it is the effective Dk (Dkeff) measured by a specific industry standard test method. When they are compared against real measurements from a design application, there is often a discrepancy in Dkeff due to increased phase delay caused by surface roughness [1].

Dkeff is highly dependent on the test apparatus and conditions of how it is measured. One method commonly used by many laminate suppliers is the clamped stripline resonator test method, as described by IPC-TM-650, Rev C, Test Methods Manual [10].

Since all glass reinforced laminates are anisotropic, any stripline based test method, like TM-650, or Bereskin stripline test method [13], reports Dk values in which the E-fields are transverse to signal propagation. That is, if the signal propagation is in the x-y axis direction, then the Dk measured by this method is when E-fields are in the z-axis direction.

For Isola’s Dk/Df table [6], shown in Figure 2, Dk values were measured by TM-650 test method. From that data, the values for most of the constructions are calculated. Additional verification runs are performed to gather statistical data over time and validate that the calculations are reasonable and accurate.

The measurements are done under stripline conditions using a carefully designed resonant element pattern card. It is made with the same dielectric material to be tested. As shown in Figure 3, the card is sandwiched between two sheets of uncladded dielectric material under test. Then the whole structure is clamped between two large plates; each lined with copper foil and grounded. They act as reference planes for the stripline.

Figure 3. Illustration of clamped stripline resonator test method, as described by IPC-TM-650,, Rev C, Test Methods Manual [10].

This test method assures consistency of product when used in fabricated boards. It does not guarantee the values directly correspond to design applications.

Here is why:

Since the resonant element pattern card and material under test are not physically bonded together, air is entrapped between the various layers. These small air gaps are caused by the:

  • roughness of the copper foil plates in the fixture 

  • roughness profile imprint left on the surface from the foil that was removed from the test samples

  • copper removed on the resonant element pattern card

Air entrapment, due to the TM-650 test method, is the primary reason for effective Dk and phase delay discrepancies between simulation using laminate suppliers’ Dk/Df tables and real measurements from a design application. The small air gaps result in a lower effective Dk than what would be measured in a real PCB because everything is pressed together with no air entrapment, as shown in a cross-section view of Figure 4.

Figure 4. Example of foil bonded to core or prepreg dielectric. Rz1 is rougher than Rz2 and Hsmooth is the thickness of the dielectric as if the foil was removed.

When copper roughness is different on each side of the dielectric, like the example shown in Figure 4, Dkeff is determined heuristically by this simple correction factor:

Equation 1.



  • Hsmooth is dielectric core thickness from laminate suppliers’ Dk/Df table data sheet or pressed prepreg thickness from the PCB stackup drawing.

  • Rz1 and Rz2 are the conductor roughness of the foil for the respective side of the dielectric from foil suppliers’ data sheet. Typically, Rz is the 10-point mean roughness as measured by a mechanical profilometer.

  • Dk is dielectric constant from laminate supplier’s Dk/Df table data sheet.

In Figure 4, Rz1 is the roughness of the top foil, and Rz2 is the roughness of the bottom foil. In this example, Rz1 is rougher than Rz2. Hsmooth is the core thickness of the dielectric, as specified in the Dk/Df table, or pressed thickness of the prepreg, often shown on a stackup drawing. It is the thickness of the dielectric as if the foil was removed.

When copper foil with the same Rz roughness is bonded to each side of the core or prepeg, Dkeff can be simplified as:

Equation 2


Figure 5 plots Dkeff over frequency derived from S21 phase or time delay (TD); Dkeff=(TDc0  ∕ length)2  from a Megtron-6 stripline case study [3]. This method is different than IPC-TM-650 test method in that it determines Dkeff from unwrapped phase delay rather than calculating Dk/Df from resonant peaks over the frequency range defined in the spec.

The blue plot is a simulated case based on core and prepreg Dk values from published Dk/Df tables at 12 GHz. When Dk is corrected due to roughness, using Equation 2, and resimulated, Dkeff is shown in pink. Although the Dkeff  has improved, it still does not agree with the measured Dkeff from the device under test (DUT), shown in red.

Figure 5. Comparisons of simulated Dkeff over frequency vs. measured. The red plot is actual measured Dkeff from the DUT. The middle pink plot is a simulation using Dkeff corrected due to roughness. The bottom blue plot is simulated using Dk at 12 GHz as published in Dk/Df tables and non-causal roughness model. The green dashed plot is a simulation using Dkeff due to roughness; a causal Huray-Bracken roughness model was used. Modeled with Simbeor [11] and simulated with Keysight ADS [12].

The discrepancy between the pink and red plots is because Dkeff from Equation 2 only corrects the phase delay due to self capacitance (C11) per unit length of the transmission line. But roughness of the foil also increases the self inductance (L11) per unit length of the transmission line, which adds additional phase or time delay [4].

This is counter intuitive and can be confusing since we usually relate Dkeff to capacitance only. By definition, Dkeff is the ratio of the actual structure’s capacitance to the capacitance when the dielectric is replaced by air. But this is only true for static electric fields. For time-variant electromagnetic fields, Dkeff becomes frequency-dependent [14].

If the propagation delay (tpd) for a single transmission line, in seconds per unit length, is determined by:

Equation 3.


and c0 is the speed of light (~3.0E8 m/s) =1/sqrt(μ0 ε0 ); μ0 (4πE−7 H/m) and ε(8.8542E−12 F/m) is permeability and permittivity of free space respectively, then:

Equation 4.


where: L11; C11 are self inductance in Henries per unit length and self capacitance in Farads per unit length respectively.

Equation 4 clearly shows that with an increase in self inductance there will be a proportional increase in Dkeff. This means for PCB transmission lines, calculating Dkeff=(TDc0  ∕ length)2  cannot be trusted to be the same as relative permittivity (εr) of the dielectric material. The consequence for doing so leads to inaccurate impedance predictions and non-causal time domain simulations, resulting in poor correlation to measurements.

A causal model, when simulated, does not produce any change in its output signal before there is a change in its input signal. When field solvers properly correct the self inductance, by applying the roughness correction factor to the imaginary portion of the complex impedance of the metal [4][5], the model is then causal. When combined with the corrected Dkeff for cores and prepregs from Equation 2, there is excellent correlation, as shown by the dashed green plot in Figure 5. Unfortunately, not all field solvers have causal roughness models to correct the inductance in the simulation.

Since there is no simple way to backtrack from a phase measurement to establish the right Dkeff to use for your modeling, especially for lossy stripline constructions, heuristic methods are an alternative.

Using the right Dkeff for your modeling ensures a correct time domain reflectometer (TDR) impedance prediction, as shown in Figure 6. The red plot is measured differential TDR from [3]. When core and prepreg Dk from Dk/Df tables were used along with a non-causal roughness model in the simulation, the blue plot shows an overestimate for impedance. When Dkeff from Equation 2, and a non-causal roughness model was used in the simulation, the pink plot shows an underestimate in the impedance plot.

It is only when we apply a causal Huray-Bracken roughness model from [11], along with Dkeff from Equation 2, that we see the effect of the increased self inductance, shown by the green dashed line plot in Figure 6. 

At first glance of Figure 6, one might interpret the pink plot as having better correlation to the measured red plot. But because the measured plot has an impedance ripple along its length, it is difficult to conclude which is the correct model from the TDR plots alone. It is only when we compare Dkeff derived from the green dashed phase delay plot from Figure 5 that we can conclude the green dashed line TDR plot is the correct impedance.

Figure 6. Simulated vs. measured differential TDR plots when different Dkeff was used in the model. The blue plot overestimates impedance when Dk from data sheets was used. The pink plot underestimates the impedance when Dkeff (Equation 2) and non-causal roughness model was used. The green dashed line plot is when Dkeff (Equation 2) and a causal Huray-Bracken roughness model were used. Modeled with Simbeor [11] and simulated with Keysight ADS [12].


Dielectric constants from marketing data sheets cannot be trusted to properly design PCB stackups and model transmission lines for impedance and phase delay. Instead, laminate suppliers’ Dk/Df tables should be used.

Many laminate suppliers provide Dk/Df tables derived from a clamped stripline resonator test method [10] or similar Bereskin test method [13]. But the numbers do not factor the actual roughness of the foil. When a simple correction factor, based on the thickness of laminate and Rz foil roughness is considered, a more accurate value for Dkeff along with a causal roughness model can be used for impedance and transmission line modeling.

For PCB transmission lines, calculating Dkeff from phase or time delay measurement method cannot be trusted to be the relative permittivity of the dielectric material. Using this value will lead to inaccurate simulation results.


1. L. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness“, DesignCon 2017, Santa Clara, USA.

2. B. Simonovich, “Stackup Beware: Case Study of the Effects on Transmission Line Losses Due to Mixed Reference Plane Roughness”, Signal Integrity Journal article, August 10, 2021.

3. B. Simonovich, “PCB Fabrication: What SI/PI Engineers Need to Know for First Time Modeling Success”, DesignCon 2021 Spring Break Webinar Series, April 12-16, 2021.

4. V. Dmitriev-Zdorov, B. Simonovich, Igor Kochikov, “A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics“, DesignCon 2018, Santa Clara, USA.

5. J.E. Bracken, “A Causal Huray Model for Surface Roughness”, DesignCon 2012, Santa Clara, USA.

6. Isola Group, 6565 West Frye, Chandler, AZ 85226.

7. Circuit Foil, 6 Salzbaach, 9559 Wiltz, Grand Duchy of Luxembourg.

8. Rogers Corporation, 2225 W. Chandler Blvd., Chandler, AZ 85224.

9. J. Coonrod, “Managing PCB Materials: Dielectric Constant (Dk)”, Rogers Corporation, Blog Article, Sep 11, 2018

10. IPC-TM-650,, Rev C, Test Methods Manual

11. Simbeor THz [computer software].

12. Keysight ADS Keysight Advanced Design System (ADS) [computer software].

13. Bereskin, A. B. “Microwave Dielectric Property Measurements”, Microwave Journal, vol. 35, no.7, pp. 98 – 112

14. Wikipedia contributors. (2022, January 12). Relative permittivity. In Wikipedia, The Free Encyclopedia. Retrieved 18:14, January 14, 2022.


    Written by Bert Simonovich

    May 14, 2022 at 10:21 am

    Characteristic Impedance – Where SI/PI Worlds Collide

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    Originally published Signal Integrity Journal, February 23, 2021

    Signal and power integrity (SI/PI) simulations, measurements, and analysis usually live in two different worlds, but occasionally these worlds collide. One such collision occurs when we refer to characteristic impedance, Z0. Traditionally the PI world lives in the frequency domain while the SI world lives in the time domain.

    When designing a power distribution network (PDN) in the PI world, we are mostly interested in engineering a flat impedance below a target impedance from DC to the highest frequency components of the transient current. Practically this is achieved with a network of capacitors with different values connected to the respective power planes as shown in Figure 1.


    Figure 1 A simplified model of a typical PDN courtesy [1].

    In the real world, there is no such thing as an ideal capacitor. There are always parasitic elements known as equivalent series inductance (ESL) and equivalent series resistance (ESR). Physical characteristics of the PCB, like component mounting inductance, plane spreading inductance, via and BGA ball inductance, along with voltage regulator module (VRM) characteristics also contribute to the impedance profile. When connected together, the interaction of capacitors and parasitic inductance and resistance create a transfer impedance profile with resonant peaks and anti-resonant nulls as shown in Figure 2.

    The transfer impedance between the VRM and the load is calculated and plotted in the frequency domain with a log-log scale. The resulted impedance curve is then compared to the target impedance (Ztarget), which is estimated based on the allowed noise ripple and maximum transient current. The flat target impedance is frequency independent in the analysis.


    Figure 2 Impedance profile of the PDN as viewed from the pads on the die power rail courtesy [1].

    Resonant peaks are due to ESL of one capacitor connected in parallel with another capacitor. Anti-resonant nulls are due to the series combination of ESR, ESL, and C for each capacitor. Different capacitor values will have anti-resonant nulls at different frequencies.

    But in the PI world, there is a rarely talked about characteristic impedance, Z0. In this case, it refers to the geometric average of the reactive impedance of a capacitor (XC) and reactive impedance of an inductor (XL).

    Equation 1


    At resonance, XL and XC intersect at the characteristic impedance and are equal as shown in Figure 3.


    Figure 3 Inductive and capacitive reactance plot of ideal inductor and capacitor versus frequency. At resonance, XL and XC are equal and intersect at the characteristic impedance, Z0. Simulated with Pathwave ADS [6].

    This is a very important observation, and it is where the SI/PI worlds collide.

    In the SI world, characteristic impedance, Z0 refers to the instantaneous ratio of the voltage to current of a wave front traveling along a uniform transmission line without reflections. For an infinitely long uniform transmission line, Z0 equals the input impedance.

    The characteristic impedance of a lossy transmission line is defined as:

    Equation 2


    Where R is resistance per unit length; G is conductance per unit length; L is inductance per unit length; and C is capacitance per unit length. For a lossless uniform transmission line, R and G are assumed to be zero and thus the characteristic impedance is reduced to:

    Equation 3


    Time Domain Reflectometer

    In the SI world, we usually use a time domain reflectometer (TDR) to measure characteristic impedance, but more often than not, the measured impedance we get is not what we predicted with a 2D field solver. Many 2D field solvers used by most PCB FAB shops only calculate the lossless characteristic impedance of the cross-sectional geometry at a single frequency, defined by the dielectric constant (Dk). It has no input for conductor resistivity, dielectric loss, or how long the conductor(s) is.

    So the issue is: we design the stackup, then do our SI modeling analysis based on stackup parameters and matching characteristic impedance. But the PCB FAB shop will often adjust the line width(s), over and above normal process variation, so that when measured, the impedance will fall within the specified tolerance, usually +/-10 percent.  

    Part of the problem lies with the method used to take the measurements. Most PCB FAB shops follow IPC-TM-650 Test Methods Manual [2]. But it has limitations because Z0 measured is derived and cannot be directly measured. The reason is the measurements include resistive and dielectric losses, up to the point where the measurement takes place along the TDR plot.

    Resistive loss often results in a slow monotonic rise in the impedance profile, shown in the example TDR plot of Figure 4. IPC-TM-650 specifies a measurement zone between 30-70 percent to avoid probing induced ringing affecting the measurements. Most PCB FAB shops will measure an average impedance over this range, usually in the center region.

    Depending on the linewidth, thickness and dielectric dissipation factor (Df), the slope of the monotonic rise will vary.


    Figure 4 Example TDR plot showing slow monotonic rise in impedance due to resistive losses and IPC-TM-650 measurement zone.

    The problem is that the IPC-TM-650 test method was last updated back in 2004, when higher dielectric loss, along with wider line widths and thicker copper weights, were used more often. A higher Df tends to compensate for resistive loss by flattening the slope as shown in Figure 5.

    On the bottom left is a simulated TDR plot using a high loss dielectric with Df = 0.024. The right side has the exact same geometry properties except Df = 0.004. The average impedance, when measured at the 50 percent point, is 49.8 Ohms on the left side vs. 51.4 Ohms on the right side. We also confirm flatter slope for high loss material.

    The actual characteristic impedance predicted by a Polar SI9000 2D field solver [5] in Figure 5 is 49 Ohms. For higher loss material, measuring within the measurement zone would pass without any issues. But for lower loss material, the resistive loss dominates and measuring within the measurement zone will give ~5 percent higher impedance reading compared to the higher loss material. The correct measurement point for Z0 is, in fact, the initial dip, equivalent to the field solver prediction. Depending on the tolerance specified, this may affect yield and cost.


    Figure 5 Characteristic impedance prediction by Polar SI9000 2D field solver [5] (top). Simulated 2 inch TDR plots using a high loss dielectric (bottom left) vs. low loss dielectric with exactly the same geometry (bottm right). A higher Df compensates for higher resistive loss thereby flattening the curve. Simulated with Pathwave ADS [6].

    Today, with the push to low loss dielectric and finer line widths with thinner copper weights, measuring the true transmission line characteristic impedance using a TDR becomes more challenging. This is even more so when measuring differential impedance, because a change in line width space geometry can have a more profound effect on measured differential impedance.

    Using the first article build of a new design, as an example, let’s assume the correct characteristic impedance, when measured at the beginning of the slow monotonic rise of a TDR plot, is on the high end of nominal +10 percent tolerance. Let’s say it’s 54 Ohms.  But because of the low loss dielectric and high resistive loss, the TDR measurement at the midpoint is now reading 5% higher at 57 Ohms. This would imply the impedance is now out of spec over nominal and the board would be scrapped.

    The PCB fab shop will then go back and adjust the linewidth accordingly for the next build to bring the measurement within range to their measurement set up. Doing this effectively lowers the true nominal characteristic impedance!

    If subsequent manufacturing variations pushes the measured impedance within the measurement zone on the low end of the -10 percent tolerance, say 44 Ohms, then the true characteristic impedance, if measured at the initial dip, will be 5 percent lower at 42 Ohms and be out of spec. But the board will pass because it was measured following IPC-TM-650 test method.   

    2-port Shunt Measurement

    But what if there were another way? What if we could borrow impedance measuring techniques from the PI world to determine the true transmission line characteristic impedance in the SI world?  Well there is. Enter the 2-port shunt measurement technique.

    For example, in the PI world, to measure ESL and ESR of a chip capacitor, of a device under test (DUT), a 2-port shunt measurement is often used. It is much like the 4-point Kelvin measurement technique used to measure very low DC resistance.

    The 2-port shunt measurement is usually done with a 2-port vector network analyzer (VNA). Port 1 of the VNA sends out a calibrated signal, and port 2 measures the voltage signal across the DUT. Often an isolation transformer is also used to break the inherent ground loop when measuring ultra-low impedances [3].

    Once the measurements have been completed and S-parameters saved in touchstone format, further analysis can be done in your favorite SPICE simulator. Figure 6 is a generic schematic using popular Pathwave ADS [5] that can be used for 2-port shunt analysis.

    When port 1 and port 2 are connected to port 1 of the DUT and port 2 of the DUT is grounded, the impedance of the DUT can be determined by [3];

    Equation 4



    Figure 6 Generic Pathwave ADS [6] schematic used for 2-port shunt analysis on a S2P file for DUT.

    If we replace the DUT in Figure 6 with a capacitor and inductor, we get an impedance plot shown in Figure 7.  As we saw earlier, when we take the geometric average of the inductive and capacitive reactance using Equation 1, we get the characteristic impedance. If we apply Equation 4 to the results of a 2-port shunt measurements of a capacitor and inductor, we get exactly the same results as shown in the top of Figure 7.

    When we replace the capacitor and inductor with a S-parameter file of a transmission line model from Figure 5, we get the plot shown at the bottom of Figure 7. Except for the resonant nulls and peaks, up to a certain frequency, the impedance of a transmission line looks like the impedance of a capacitor when the far-end is open, and looks like the impedance of an inductor when the far-end is shorted. And because of that, this is where the two worlds collide!

    If we take the geometric average of the impedance when the far-end is open (Zopen) or shorted (Zshort), we get the characteristic impedance at that frequency. We note where the red and blue impedance lines first intersect, is exactly the geometric average characteristic impedance at that frequency.

    Also worth noting, the lines intersect at half of the frequency between the peaks and valleys at higher frequencies as well.


    Figure 7 Impedance of inductive and capacitive reactance vs. frequency (top) and impedance of a transmission line vs. frequency (bottom) when the far-end is open (solid red) compared to when the far-end is shorted (solid blue). The intersection of the red and blue lines is exactly the characteristic impedance. Simulated with Pathwave ADS [5].

    We can see this more clearly if we replot Figure 7 bottom using a linear scale for the x-axis, as shown in Figure 8. This is a very powerful observation. What this means is that when we measure the impedance half way between a peak and adjacent valley, of either the red or blue plot, it is the characteristic impedance of the transmission line at that frequency.

    Thus, only an open or shorted end measurement is all that is needed to determine the characteristic impedance. For example, if we look at the red curve alone, then measure the first resonant null (m14) and adjacent peak (m15), the characteristic impedance (mag(Zopen) is measured exactly at one half the frequency between the two (m16). 


    Figure 8 Impedance of a transmission line vs. frequency on a linear scale when the far-end is open (solid red) compared to when the far-end is shorted (solid blue). The intersection of the red and blue lines half way between respective peaks and valleys is the characteristic impedance. Simulated with Pathwave ADS [6].

    The first resonant red null and blue peak represent the quarter-wave resonant frequency due to open and shorted end. Each respective red null and blue peak following are the odd harmonics of the first quarter-wave resonant frequency.

    Knowing this, we can now determine the phase or time delay (TD) of the transmission line as being one quarter of the period of the resonant frequency (f0).

    Equation 5


    Because resonant nulls and peaks occur at the resonant frequency, we can also determine the effective dielectric constant (Dkeff). Given the speed of light (c) = 11.8 in. per nanosecond, the length of the transmission line (len) in in. and quarter-wave resonant frequency (f0), Dkeff can be determined by:

    Equation 6


    CMP28 Case Study


    Figure 9 Photo of a portion of CMP-28 test platform courtesy of Wildriver Technology [8] used for measurement validation.

    To test the accuracy of this method, measured data from a CMP28 test platform, shown in Figure 9, was used for measurement validation. S-parameter (s2p) files from 2 inch and 8 inch single-ended stripline traces were provided as part of CMP-28 design kit courtesy of Wildriver Technologies [8]. The 6-inch transmission line segment S-parameter data was de-embedded courtesy of AtaiTec Corporation [9].

    The characteristic impedance, based on trace geometry and stackup parameters, was modeled in Polar SI9000 [5]. Using Dk from data sheet tables @ 10GHz, and correcting for conductor roughness [10], the characteristic impedance predicted was 49.66 Ohms, as shown in Figure 10.


    Figure 10 Polar SI9000 field-solver [5] characteristic impedance prediction of CMP28 trace geometry.

    Touchstone S-parameter DUT files were connected with far-end open, shorted, and terminated as shown in Figure 11. The TDR plot, with far-end terminated, shows an impedance of 50.57 Ohms, when measured at the initial peak. Then it takes an immediate dip to approximately 50 Ohms before continuing with a slow monotonic rise with some ripples. If the DUT was a uniform trace, with connector discontinuity de-embedded, we would not see the initial peak followed by the dip.  This signature strongly suggests that the DUT is not uniform and thus it is very difficult to determine the actual characteristic impedance using IPC-TM-650 test method alone. 

    But only after taking 2-port shunt measurements can we confirm the true characteristic impedance. As shown, Zoavg is 50.68 Ohms where the red and blue curves cross at 122.5 MHz, and confirms the true measurement point in the TDR plot is the initial peak. Both are about 1 Ohm higher compared with 2-D field solver results in Figure 10.

    If the length of the transmission line simulated above is 6 in. and f0 =248.2 MHz, then TD = 1 ns and Dkeff = 3.92, using Equation 5 and Equation 6 respectively.


    Figure 11 Measured results from a CMP28 test platform design kit, courtesy of Wildriver Technology [8].

    But wait a minute. Why is Dkeff is higher than what was used in the 2-D field solver in Figure 10?

    One reason is due to process variation of the material and fabrication. The actual Dkeff is determined by the final thickness of dielectric and the roughness of the copper, which also increases inductance affecting TD [10] [11]. But the main reason is Dk is frequency dependent and the value used in the field solver was at 10 GHz, based on laminate supplier’s Dk/Df tables.

    Since TD, ultimately determines Dkeff, it does not represent the intrinsic property of the dielectric material. Because Dkeff varies with frequency, it was calculated at the first resonant null of 248.2 MHz, which is at a much lower frequency for Dk than the frequency originally used to select Dk in the field solver.

    As can be seen in Figure 12, a simulated vs. measured 2-port shunt frequency plot, with far-end open and shorted, we get exactly the same information, compared to the traditional method used to validate characteristic impedance and Dkeff.

    If we measure the 39th odd harmonic frequency (H) at 9.884GHz for the resonant null closest to 10GHz, equating to the value of Dk used in Polar Si9000 2D field solver, Dkeff can be calculated with Equation 7:

    Equation 7


    The bottom right plot of Figure 12, shows Dkeff simulated (blue) vs. measured (red). As we can see, the measured Dkeff at 248.7 MHz is 3.94; pretty much agreeing with our earlier calculation of 3.92 using Equation 6. Furthermore, when we compare Dkeff = 3.76 at 9.884 GHz, it agrees with our calculation for the 39th harmonic frequency from Equation 7. The reason there is still a slight difference in Dkeff is because the added delay due to inductance due to roughness [11] was not factored into the simulated model.

    The bottom left is a TDR plot that shows measured impedance (red) vs. simulated (blue) over time. The marker at the beginning of the initial dip (m6) represents the characteristic impedance with highest frequency harmonics included in the incident step edge of TDR waveform. The marker at the end (m16) represents the impedance at twice the TD with high frequency harmonics attenuated due to dispersion of the lossy dielectric and resistance of trace length.

    When we measure Zoavg_meas impedance of DUT at 9.884GHz, at the top plot of Figure 12, it agrees pretty well with the simulated and measured TDR plot at the initial step.


    Figure 12 Comparison of PI world 2-port shunt measurement results for transmission line characteristic impedance and Dkeff compared to traditional SI world measurement results. Top plot is the 2-port shunt simulated vs. DUT impedance measurements at the fundamental and 39th harmonic frequencies. Bottom left is beginning and end impedance measurements on TDR plot. Bottom right measuring equivalent Dkeff at fundamental and 39th harmonic frequencies.  

    Summary and Conclusion

    Sometimes, when SI and PI worlds collide, we get the best of both worlds. By borrowing a simple 2-port shunt impedance measuring technique from the PI world, we have another tool at our disposal to measure true characteristic impedance, TD, and effective Dk from a uniformly designed transmission line in the SI world. The advantage is, unlike a TDR measurement, measuring true characteristic impedance using 2-port shunt method is not influenced by resistive or dielectric losses.


    1. L. Smith, S. Sandler, E. Bogatin, “Target Impedance Is Not Enough,” Signal Integrity Journal, Vol. 1, Issue 1, January 2019; URL:
    2. IPC-TM-650 Test methods Manual, Number, “Characteristic Impedance of Lines on Printed Boards by TDR”, Rev. A, March, 2004
    3. I. Novak, J. Millar, “Frequency-Domain Characterization of Power Distribution Networks,” Artech House, 685 Canton St., Norwood, MA, 02062, 2007.
    4. Pathwave Advanced Design System (ADS) [computer software], Version 2021, URL:
    5. Polar Instruments Si9000e [computer software], Version 2018, URL:
    6. Keysight Pathwave Advanced Design System (ADS) [computer software], Version 2021, URL:
    7. E. Bogatin, “Bogatin’s Practical Guide to Transmission Line Design and Characterization for Signal Integrity”, Artech House, 685 Canton St., Norwood, MA, 02062, 2020
    8. Wild River Technology LLC 8311 SW Charlotte Drive Beaverton, OR 97007. URL:
    9. AtaiTec Corporation, URL:
    10. V. Dmitriev-Zdorov, B. Simonovich, I. Kochikov, “A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics”, DesignCon 2018 proceedings, Santa Clara, CA.
    11. I. Novak et al, “Determining PCB Trace Impedance by TDR: Challenges and Possible Solutions”, DesignCon 2013 proceedings, Santa Clara, CA.
    12. S. Sandler, “Easy trick to measure plane impedance with VNA”, EDN Asia, 2014, URL:

    Written by Bert Simonovich

    May 2, 2021 at 4:24 pm

    Practical Modeling of High-speed Channels

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    As Dave Dunham from Molex Corp. likes to say, “When designing high-speed serial links beyond 10 GB/s, everything matters”. In order to ensure first time success at these speeds, accurate channel modeling is a prerequisite. This is especially true for long backplane channels.

    imageAlthough many EDA tools include the latest and greatest models for conductor surface roughness and wide-band dielectric properties, obtaining the right parameters to feed the models is always a challenge. Often the only sources are from data sheets alone. But in most cases, the numbers do not translate directly into parameters needed for the EDA tools. So how do we get these parameters?

    One way is to follow the design feedback method which involves designing, building and measuring a test coupon, then extracting the parameters through tuning simulation to measurement. Although this method is pretty practical and accurate, a significant amount of expertise and equipment is required to design, build and measure the test coupon, which takes significant amount of time and money.

    But, as Eric Bogatin often likes to say, “Sometimes an OK answer NOW! is better than a good answer late.” As a high-speed signal integrity practitioner and backplane architect, I often have to come up with an answer sooner, rather than later because of the impact to time and cost to my clients. And that’s why I have been motivated over the last few years to research and develop simple methodologies to accurately determine parameters to feed into modern EDA tools.

    If you went to this year`s EDICon 2017 in Boston, and attended the High-speed Digital Symposium session, you would have heard me speak on a “Practical Modeling of High-speed Channels Based on Data Sheet Input”, which was the title of my presentation.

    For those of you who could not attend, I have made available an annotated slide deck. You can download a copy from my web site.

    What you will learn:

    • How to use my Cannonball model to determine Huray roughness parameters from data sheet alone
    • How to determine effective dielectric constant due to roughness from data sheets alone
    • How to apply these parameters in the latest version of Polar Si9000e Field Solver
    • How to pull it all together using Keysight ADS software

    And this is an example of simulation results compared to measurements you can expect to see:


    Written by Bert Simonovich

    October 20, 2017 at 10:19 am

    Via Stubs Demystified

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    imageWe worry about via stubs in high-speed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot (IL) of the channel. But are all via stubs bad? Well, as with most answers relating to signal integrity, “It depends.”

    If one of these frequency nulls happen to line up at or near the Nyquist frequency of the bit- rate (i.e. 1/2 of the bit-rate), the received eye will be devastated, resulting in a high bit-error-ratio (BER), or even link failure.

    Figure 1 shows simulation results of two backplane channels. On the left are measured SDD21 insertion loss and eye diagram of a 10 GB/s, non-return-to-zero (NRZ) signal, with short through vias and long stubs ~ 270 mils. On the right, shows measured SDD21 IL and eye diagram of a channel with long through vias and shorter stubs ~ 65 mils

    Because the ¼ -wave resonant null occurs at a frequency ~ 4. 4 GHz, this is near the Nyquist frequency for 10 GB/s. As can be seen, the eye is totally closed for the long stub case. But when the shorter stub case is simulated, the eye is open with plenty of margin.

    So how does a via stub cause ¼ -wave resonance? This question can be explained with the aid of Figure 2. Starting on the left, we see a via with two sections. The through (thru) part is the top portion connecting a device pin to an inner layer trace of a printed circuit board (PCB). The stub portion is the lower portion and is an open circuit.

    On the right a sinusoidal signal is injected into the pin at the top of the via and travels along the thru portion until it reaches the junction of the internal trace and stub. At that point, the signal splits. Some of it travels along the trace, and the rest continues down the stub. Once it reaches the bottom, it reflects back up. When it reaches the trace junction, it splits again with a portion traveling along the trace and the rest back to the source.

    If f  is the frequency of a sine wave, and the time delay (TD) through the stub portion equals a ¼ -wavelength, then when it reflects at the bottom and reaches the junction again, it will be delayed by ½ a cycle and cancels most of the original signal.


    Figure 2 Illustration of a ¼ -wave resonance of a stub. If f = frequency where TD = ¼ wavelength, then when 2TD = ½ cycle minimum signal received.

    Resonance nulls occurs at the fundamental frequency ( fo) and at every odd harmonic. If you know the length of the stub (in inches) and the effective dielectric constant (Dkeff), surrounding the via hole structure, the resonant frequency can be predicted by:

    Equation 1


    Where: fo is the ¼ -wave resonant frequency (GHz); c is the speed of light (~11.8 in/ns); Stub_length is inches.

    You will find that Dkeff is not the same as the bulk Dk published in laminate manufacturers’ data sheets. It is typically higher. A higher Dkeff increases phase delay through the via resulting in a lower resonant frequency.

    One reason is excess capacitance from the via pads as well as the via barrel’s proximity to the clearance hole openings (also known as anti-pads) in plane layers. The other is because of the anisotropic nature of the laminate material.

    For the example in Figure 1, the ¼ -wave resonant frequency of the long via stub is ~ 4.4 GHz. With a stub length of ~ 270 mils, this gives a Dkeff of 6.16, which is considerably higher than the published bulk Dk of 3.65. When you model a via in an electro-magnetic (EM) 3D field solver, it automatically accounts for the excess capacitance, but you will still need to compensate for the anisotropic nature of the dielectric.

    A material is anisotropic when there are different values for parallel (x-y) vs perpendicular (z) measured values for dielectric constant. Dielectric constant and loss tangent, as published in manufacturers’ data sheets, report perpendicular measured values. For FR-4 fiberglass reinforced laminates, anisotropy can range from 15% -25% higher. The bad news is these numbers are not readily available from data sheets.

    For differentially driven vias with plane layers evenly distributed throughout the entire stackup, Dkeff can be roughly estimated by:

    Equation 2


    Where: Dkxy is the dielectric constant adjusted for anisotropy (15%-25% higher); Dkz is the bulk dielectric constant from data sheets; s is via-via spacing; drillØ is drill diameter; H and W are anti-pad shape dimensions as shown in Figure 3 .


    Figure 3 Anti-pad parameters for Equation 2.

    The effects of via stubs can be mitigated by: using blind or buried vias; back-drilling; or by using thru vias only (i.e. from top layer to bottom layer). Practically, the shortest stub that can be achieved by back-drilling is on the order of 5 to 10 mils.

    As a rule of thumb, we usually strive to have an interconnect bandwidth (BW) to be five times the Nyquist frequency of the bit-rate. Since a ¼-wave resonant null behaves somewhat like a notch filter, depending on the high-frequency roll-off due to Q-factor, frequencies near resonance will be attenuated. For that reason a good rule of thumb to follow is making sure the first null should occur at the 7th harmonic, or higher, of the Nyquist frequency to maintain the integrity of the 5th harmonic frequency component that makes up the risetime of a signal.

    With this in mind, for a given baud-rate (Baud) in GBd, the maximum stub length (lmax), in inches can be estimated by:

    Equation 3


    For NRZ signaling, the baud-rate is equal to the bit rate. But for pulse-amplitude modulation (PAM-4) signaling, which has 2 symbols per bit time, the baud-rate is ½ of that. Thus a 56 GB/s PAM-4 signal has a baud-rate of 28 GBd, and the Nyquist frequency is 14 GHz, which happens to be the same as 28 GB/s NRZ signalling.

    Figure 4 presents a chart of maximum stub length vs baud-rate based on Equation 3, using a Dkeff = 6.16 (blue) vs 3.65 (red). It shows us the higher the baud-rate, the more the stub length becomes an issue, especially past 10 GBd. We also get a feel for the sensitivity of stub length to Dkeff . Even though there is ~ 70% difference in Dkeff, there is only ~ 30% delta in stub lengths for the same baud-rate. This means that even if we use the bulk Dk published in data sheets, we are probably not dead in the water.

    If the respective stub length is greater than this, it does not mean there is a show stopper. Depending on how much longer means the eye opening at the receiver will be degraded and we lose margin. We see this by the example in Figure 1. Even though the stub lengths in the channel were almost double the value at 10 GBd from the chart, there is still plenty of eye opening.


    Figure 4 Chart showing estimated maximum stub length vs baud-rate with Dkeff of 6.16 (red) vs 3.65 (blue) based on Equation 3

    To further explore design space and test out the rule of thumb, a generic circuit model was built using Keysight ADS with the ability to vary the via stub lengths

    Referring to the chart, at 28 GBd, the maximum stub length should be 12 mils, assuming a Dkeff of 6.16. Figure 5 shows simulation results for NRZ signalling. As can be seen, there was a difference of only 17 mV in eye height (1.5%), and no extra jitter for 12 mil stubs compared to 5 mil stubs.


    Figure 5 Eye diagrams comparison with BER at 10E-12 for stub lengths of 5 mils vs 12 mils. Modeled and simulated with Keysight ADS.

    But if we use the exact same channel model, and use the generic PAM-4 IBIS AMI model from Keysight Technologies, we can see the results plotted in Figure 6. On the left are the eye openings with 5 mil stubs and the right with 12 mil stubs. In this case, there was an average reduction of ~7 mV (6%) in eye heights, and 0.24 ps (2%) in eye widths at BER 10E-12 across all three eyes.


    Figure 6 PAM-4, 28 GBd (56 GB/s) eye height and width comparison at BER of 10E-12 for 5 mil vs 12 mil stub lengths. Modeled and simulated with Keysight ADS.

    Because PAM-4 signalling has three smaller eyes, that are one-third the size of an NRZ eye for the same amplitude, it is more sensitive to channel impairments. From the above examples, we can see NRZ had only 1.5% reduction in eye height compared to 6% for PAM-4. Similarly there was no increase in jitter for NRZ compared to 2% increase for PAM-4 when stub lengths changed from 5 mils to 12 mils.

    What this says is maintaining a BW to 5 times Nyquist rule of thumb, when estimating via stub lengths, is quite conservative for NRZ signalling. There is almost the same BW as the channel with 5 mil stub, which was the original objective. But because PAM-4 is more sensitive to impairments, it shows there is less margin.

    In summary then, rules of thumb and related equations are a good way to reinforce your intuitions or to give you an answer sooner rather than later. They help you know what to expect before you take any measurements or perform any simulations. But they should never be used to sign off on any high-speed design.

    Because every system will have different impairments affecting BER, the only way to know how much margin you have is by modeling the via with a 3-D EM field solver, based on the actual stackup and simulating the entire channel complete with crosstalk, if margins are tight. This is even more critical for data rates above 10 GBd.

    So to answer the original question, “are all via stubs bad”? Well, the answer is it still depends. For NRZ signalling, there is more leeway than for PAM-4. But you now have a practical way to quickly quantify the answer if you know the stub length, baud-rate and delay through the via.

    Written by Bert Simonovich

    March 8, 2017 at 2:35 pm

    Obsessions with Conductor Surface Roughness – What’s the Dk Because of it?

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    clip_image002You know you have an obsession when you are flying 6 miles over Colorado; look out your window at the beautiful scenery; and all you can think about is how the rocky mountain topology reminds you of conductor surface roughness! Well call me obsessed because that’s exactly what I thought on my way to DesignCon 2017 in Santa Clara, CA.

    For those of you who know me, you know that I have been researching practical methods to model conductor surface roughness, and its effect on insertion loss (IL). I have presented several papers on the subject over the last couple of years. It’s one of my pet projects. This year, at DesignCon, I presented a paper titled, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness” .

    Everyone involved in the design and manufacture of printed circuit boards (PCBs) knows one of the most important properties of the dielectric material is the relative permittivity (εr), commonly referred to as dielectric constant (Dk). But in reality, Dk is not constant at all. It varies over frequency as you will see later.

    We often assume the value reported in manufacturers’ data sheets is the intrinsic property of the material. But in actual fact, it is the effective dielectric constant (Dkeff) generated by a specific test method. When you compare simulation against measurements, you will often see a discrepancy in Dkeff and IL, due to increased phase delay caused by surface roughness. This has always bothered me. For a long time I was always looking for ways to come up with Dkeff from data sheet numbers alone. Thus the obsession and motivation for my recent research work.

    Since phase delay, also known as time delay (TD), is proportional to Dkeff of the material, my theory was that the surface roughness profile decreases the effective separation between parallel plates, thereby increasing the electric field (e-field) strength, resulting in additional capacitance, which accounts for an increase in effective Dk and TD.

    The main focus of my paper was to prove the theory and to show a practical method to model Dkeff and TD due to surface roughness. By referencing Gauss’s Law for charged parallel plates, I confirmed mathematically, and through simulation, how the dielectric thickness and permittivity are interrelated to e-field and capacitance. I also revealed how the 10-point mean (Rz) roughness parameter can be applied to finally estimate effective Dkeff due to roughness. Finally I tested the method via case studies.

    In his book, “Transmission Line Design Handbook”, Wadell defines Dkeff as the ratio of the actual structure’s capacitance to the capacitance when the dielectric is replaced by air.

    Dkeff is highly dependent on the test apparatus and conditions of how it is measured. There are several methods used in the industry. One method that is commonly used by many laminate suppliers is called the clamped stripline resonator test method. It is described by IPC-TM-650, section, Rev C.

    In short, this method rapidly tests dielectric material for permittivity and loss tangent, over an X-band frequency range of 8-12.4 GHz, in a production environment. It does not guarantee the values are accurate for design applications.

    Here’s why:

    The measurements are made under stripline conditions, using a carefully designed resonant element pattern card, made out of the same dielectric material to be tested. The card is sandwiched between two sheets of unclad dielectric material under test. The whole structure is then clamped between two large plates, lined with copper foils that are grounded.

    Since the resonant element pattern card and material under test are not physically bonded together, there are small air gaps between the various layers affecting measured results. These air gaps are caused in part by:

    • Removing the copper from the material under test, leaving the bare substrate, complete with the micro void imprint of the copper roughness.
    • The air gap between resonant element pattern card and material under test, due to the copper thickness of the etch pattern.
    • The roughness profile of the copper, on the resonant element pattern card and fixture’s grounded foil reference planes, are different than would be in practice, unless the same foil type is used.

    If Dkeff and Rz roughness parameters from the manufacturers’ data sheets are known, then the effective Dk due to roughness (Dkeff_rough) of the fabricated core laminate can now be easily estimated by:

    Equation 1


    Where: Hsmooth is the thickness of dielectric from data sheet; Rz is 10-point mean roughness from data sheet; and Dkeff is the Dk from data sheet.

    With reference to Figure 1, using Dkeff with rough copper model, as shown on the left, is equivalent to using Dkeff_rough, with smooth copper model, as shown on the right. Therefore all you need to do is use Dkeff_rough for impedance calculations, and any other numerical simulations based on surface roughness, instead of Dk published in data sheets.

    It is as simple as that.


    Figure 1 Effective Dk due to roughness model. Using Dkeff with rough copper model (left) is equivalent to using Dkeff_rough with smooth copper model (right).

    For example, one case study I presented used measurements from a CMP28 modeling platform from Wild River Technology. The PCB was fabricated with FR408HR material and reverse treated foil (RTF). Keysight EEsof EDA ADS software was used for modeling and simulation. The results are shown in Figure 2.

    The left graph shows results when data sheet values for core and prepreg were used. Dkeff measured (red) was 3.761, compared to simulated Dkeff (blue) of 3.626, at 10 GHz. This gave a delta of ~ 4%. But when the Dkeff_rough was used for core and prepreg the delta was within 1%.


    Figure 2 Measured vs simulated Dkeff using FR408HR data sheet values for core and prepreg (left) and using Dkeff_rough (right). Modeled and simulated with Keysight EEsof EDA ADS software.

    The paper shows in more detail how Equation 1 was derived, based on Gauss’ Law. In addition, I show how IL and phase delay is also improved when Dkeff_rough is used instead of data sheet values. You can download the paper titled, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”, and other papers on modeling conductor loss due to roughness from my web site.

    Written by Bert Simonovich

    February 21, 2017 at 10:48 am

    The Poor Man’s PCB Via Modeling Methodology

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    You are a backplane designer and have been assigned to engineer a  new high-speed, multi-gigabit serial link architecture from several line cards to multiple fabric switch cards across a backplane. These links must operate at 6GB/s day one and be 10GB/s (IEEE 802.3KR) ready for product evolution. The schedule is tight, and you need to come up with a backplane architecture to allow the rest of the program to progress on schedule.

    imageYou come up with a concept you think will work, but the backplane is thick with over 30 layers. There are some long traces over 30 inches and some short traces of less than 2 inches between card slots. There is strong pressure to reuse the same connector you used in your last design, but your gut tells you its design may not be good enough for this higher speed application.

    Finally, you are worried about the size and design of the differential via footprint used for the backplane connectors because you know they can be devastating to the quality of the received signal.  You want to maximize the routing channel through the connector field, which requires you to shrink the anti-pad dimensions, so the tracks will be covered by the reference planes, but you can’t easily quantify the consequences on the via of doing so.

    You have done all you can think of, based on experience, to make the vias as transparent as possible without simulating. Removal of non-functional pads on the inner layers, and planning to back-drill the connector via stubs will help,  but is it enough? You know in the back of your mind the best way to answer these questions, and to help you sleep at night,  is to put in the numbers.

    So you decide to model and simulate the channel. But to do so, you need accurate models of the vias to plug into your favorite circuit simulator. But how do you get these? You have heard it all before; “for high-speed, the best way to model a via is with a 3D electro-magnetic field solver”.  Although this might be true, what if you don’t have access to such a tool, because the cost is more than your company wants to spend, or because you don’t have the expertise nor the time to learn how to build a model you can trust to make a timely decision?

    On top of that, 3D field solvers typically produce S-parameter behavioral models. Since they represent only one sample of a given construction, it is impossible to perform what-if, worst case, min/max analysis with a single behavioral model. Because of this,  many iterations of the model are required; causing further delay in getting your answer.

    A circuit model on the other hand, is a schematic representation of the actual device. For any physical structure, there can be more than one circuit model to describe it. All can give the same performance, up to some bandwidth. When run in a circuit simulator, it predicts a measurable performance of the structure. These models can be parameterized so that worst case analysis can be explored quickly.

    The problem with a circuit model is that you often need a behavioral model to calibrate it, or need to use analytical equations to estimate the parameters. But, as my friend Eric Bogatin often says, “an OK answer NOW! is better than a great answer late”.

    In the past, it was next to impossible to develop a circuit model of a differential via structure without a behavioral model to calibrate it. These behavioral models were developed through empirical formulas, measured data, or through the use of 3D EM field solvers.

    Now, there is another way. I have nicknamed it, “The Poor Man’s PCB Via Modeling Methodology”. Here’s how it works.

    Anatomy of a Differential Via Structure:

    imageAn example of a differential via structure, shown in Figure 1, is representative of vias used to connect surface mounted components or backplane connectors to internal layer traces.

    The via barrel is a plated through hole extending the entire length of a PCB stack-up. The outside diameter equals the drill diameter. The inside diameter is the finished hole size (FHS) after plating. Pads are used on layers to ensure there is sufficient copper for track attachment after drilling operation. When used in this fashion, they are referred to as functional pads. Anti-pads are the clearance holes in the plane layers allowing the via barrel to pass through them without shorting.

    The via portion is the length of the barrel connecting one signal layer to another. It is often referred to as the through via since it is part of the signal net. The stub portion is the rest of the barrel extending to the outer layer of the PCB. In high-speed designs, a good rule of thumb to remember is that a via stub should be less than 300mils/BR in length; where BR is the bit rate in Gb/s.

    Building a Simple Scalable Circuit Model:

    imageOn close examination of Figure 2, a differential via structure can be represented by a twin-rod transmission line geometry with excess capacitance (shown in red) distributed over its entire length. The smaller the anti-pad diameter, the greater the excess capacitance. This ultimately results in lower via impedance, causing higher reflections.

    In all high-speed serial link designs, it is common practice to remove all non-functional pads and to maximize the anti-pad clearance as much as practically possible. Oval anti-pads are often used in this regard to further mitigate excess via capacitance.

    Figure 3 illustrates the equivalent circuit for a differential via that could be used in a channel topology simulation. Here it is modeled with Keysight ADS software using a coupled line transmission line model for each section. This equivalent circuit model can be scaled for any combination of layer transitions and integrated in any channel simulation scenario.

    imageSince the cross-section of the via is constant throughout its length, the differential impedance of all sections of the via are the same. We only need to know the physical length of each segment and the effective dielectric constant (Dkeff) to get the time delay of each segment.

    When driven differentially, the odd-mode parameters of each via are of major importance. Since the even-mode parameters have no impact on differential performance, both odd and even-mode parameters are set to the same values in the model.

    The challenge then is to calculate the odd mode impedance (Zodd), representing the individual via impedance (Zvia), of a differential via structure and the effective dielectric constant (Dkeff) based on its geometry. Simple equations are used to determine these parameters.

    Developing the Equations:

    Anti-pads can vary in size and shape. They can be anything from round, to oval around each via, or even a large oval surrounding both vias as illustrated in Figure 4. Square, or rectangular variations (not shown) are similar. image

    Referring back to Figure 2, we see the structure of each via looks a lot like two coaxial transmission lines with the inner layer reference planes acting like a shield. Electrostatically this is a good approximation, but because the shield is not continuous, the magnetic fields are not contained like they are in a coaxial structure. Instead they behave more like magnetic fields around a twin-rod structure.

    So here lies the secret in modeling a differential via. We take the best of both geometries to calculate the odd-mode impedance representing Zvia.

    For inductance, we will use the odd-mode inductance formula from the twin-rod transmission line geometry to calculate Lvia :


    Referring to Figure 4, we then calculate the odd-mode capacitance for Cvia derived from an approximate formula for an elliptic coaxial structure developed by M.A.R. Gunston in his book, “Microwave Transmission Line Impedance Data” . In the original formula, both shield (W’+b) and inner conductor (w+t) are elliptical in shape and are dimensioned as shown. When the anti-pads are circular, then ln[(W’+b) /(w+t)] reduces to just ln[b/t)]; which is the denominator in the Coax equation. If we use Gunston’s approximation to calculate Cvia, then the equation becomes:










    Since conventional FR4 type laminates are fabricated with a weave of glass fiber yarns and resin, they are anisotropic in nature. Because of this, the dielectric constant value depends on the direction of the electric fields. In a multi-layer PCB, there are effectively two directions of electric fields.

    The oneimage we are most familiar with has the electric fields perpendicular to the surface of the PCB; as is the case of stripline shown here in Figure 5. The dielectric constant, designated as Dkz in this case, is normally the bulk value of the dielectric specified by the laminate manufacturer’s data sheet.

    The other case has the electric fields running parallel to the surface of the PCB, as is the case when a signal propagates through a differential via structure. In this situation, the dielectric constant, designated as Dkxy, can be15-20% higher than Dkz .

    Therefore, assuming a nominal 18% anisotropic factor, Dkxy = 1.18(Dkz)

    Now that we have defined Lvia, Cvia and Dkavg, Zvia can be estimated using the following equation:


    But we are not finished yet. We still need to determine the effective dielectric constant (Dkeff) in order to accurately model the delay through the via and stub portion. Without the correct value, the quarter-wave resonant nulls in the insertion loss plot, due to the stub length, cannot be accurately predicted. The value for Dkeff is determined based on how much the via’s odd-mode impedance is decreased due to the distributed capacitive loading of the anti-pads.

    To help us with this task, we start with the twin-rod formula. The odd-mode impedance (Zodd) is half the differential impedance (Ztwin), and is expressed as:


    By substituting Equation 1 for Zodd into the equation above, and solving for Dkeff we eventually come up with the following equation:


    Validating the Model:image

    A simple 26 layer test vehicle was fabricated to compare the accuracy of the differential via circuit model to real vias. It consisted of two differential via pairs separated by 6 inches of 100 Ohm stripline differential pairs. Three sample via structures representing long, medium and short via stubs, as summarized in Figure 6, were measured using an Agilent N5230A VNA.

    The differential vias had the following common parameters:

    imageVia drill diameter; D = 28 mils
    Center to center pitch; s = 59 mils
    Oval anti-pads= 53 mils x 73 mils
    Dk of the laminate = 3.65
    Anisotropy in Dkxy = 18%
    Zvia = Zstub = 31.7 Ohms (per Equation 1)
    Dkeff = 6.8 (per Equation 2)

    Agilent ADS software was used to model and facilitate simulation correlation of the measured data as captured in Figure 7. This simple model accounts for the discontinuity of the long through section and the long stub section. The top half is the measured channel using an S-parameter file. The bottom half is a circuit model of the channel. Since the probes were not calibrated out, they are part of the device under test. The balun transformers are used to facilitate the display of the S-parameter and TDR results.image

    The comparison between the measured and simulated results of the insertion loss and TDR response for the three via stub cases using this simple approximation methodology is summarized in Figure 8.  The insertion loss plots, in the frequency domain, are shown on the left, while the TDR plots are shown on the right.

    The resonant nulls in the SDD21 plots are due to the stub lengths. As you can see, the longer the stub, the lower the resonant frequency null. If this null happens at the Nyquist frequency of the bit rate, the eye will be totally closed. This is why we back-drill them out after the board has been fabricated.

    The simulation correlation is excellent up to about 12 GHz. The TDR plots show excellent impedance matching and delay for all three cases, while the simulated stub resonant frequencies match the measured frequencies very well. As you can see, these simple approximations for Dkeff and Zvia are perfectly adequate in providing a quick and accurate circuit model for differential through hole vias typically used in backplane applications.image


    As illustrated, a simple twin-rod model (Figure 2) is used as the basis for a practical differential via circuit modeling methodology. By using Equation 1 and Equation 2, you can quickly determine the odd-mode impedance and effective dielectric constant needed for the circuit model.

    Of course, you should use this methodology first as a rough starting point to quickly estimate the performance of your differential via design. If your worst case topology simulations show the performance is marginal, then it is worth while to invest the time and money to develop a 3D full wave model to perform a more accurate analysis.

    On the other hand, if you find this approximation shows the vias have little impact on the channel performance, it may be of greater value for you to invest your time and money in resolving other critical issues with your design.

    Try it the next time you are losing sleep over your design challenges.

    For more Information:


    If you liked this design note and want to learn more, or get more details on this innovative via modeling methodology, you can visit my web site, LAMSIM , and download a copy of the white paper I wrote along with Eric Bogatin and Yazi Cao titled, “Method of Modeling Differential Vias” .

    While you are there, feel free to investigate my other white papers and publications.

    If you would like more information on our signal integrity and backplane services, or how we can help you achieve your next high-speed design challenge, email us at:



    UPDATE: In collaboration with Saturn PCB, I am pleased to announce my differential via equations above have been incorporated in a new impedance calculator available now in Saturn PCB Tool Kit software suite.


    Written by Bert Simonovich

    March 14, 2011 at 11:23 am

    PCB Vias – An Overview

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    imageVias make electrical connections between layers on a printed circuit board. They can carry signals or power between layers. For backplane designs, the most common form of vias use plated through hole (PTH) technology. They connect the pins of connectors to inner signal layers. A PTH via is formed by drilling a hole through the layers to be connected and then copper plating it.

    High Density Interconnects (HDI) is another via technology used to form very small vias where drilling holes, using a conventional drill bit, is impractical. Also known as micro-vias, this technology creates the hole with a laser before plating.

    Via Aspect Ratio

    Via aspect ratio is defined as the ratio of the circuit board thickness to the smallest unplated drilled hole diameter. It is an important metric you need to be aware of when specifying the minimum via hole size for your design, and designing your stack-up. For example, an unplated via with a drill diameter of 0.020 inches and a board thickness of 0.200, would have an aspect ratio of 10:1. The smaller the aspect ratio, the more consistent the plating is throughout the length of the via. It is desirable to have 2 mil plating thickness for the via walls. Large aspect ratio vias tend to have more plating at each end compared to the middle. This increases the chance of cracked via barrels due to z-axis expansion while soldering.

    An aspect ratio of 6:1 pretty much ensures your board can be fabricated anywhere. Most high-end board shops have the capability of fabricating boards with 10:1 aspect ratio; for drill diameters of less than 0.020 inches. Practically, the smallest drill diameter used for a through holed via is 0.013 inches. At 10:1, the maximum board thickness would be 0.130 inches.

    For drill diameters larger than 0.020 inches, the max aspect ratio can be anywhere from 15:1 to over 20:1; depending on the board shop. Since backplane via hole size is driven by the compliant pins of the connector, it is best to work with your board shop to determine the maximum board thickness they can fabricate with the minimum finished hole size (FHS) specified in the design.

    Via Configurations

    The following lists the various via configurations you might expect to find on any multi-layer PCB design:

    • Stub Via
    • Through Via
    • Blind or Micro-via
    • Buried Via
    • Back-drilled Via

    Stub Via

    imageThe Stub Via is the most common via configuration found in PCBs today. As illustrated, there are two variations; Stub Via A and Stub Via B.

    For the Stub Via A example, it shows the through portion starting from the top layer and ending at some inner layer. The stub portion is the remaining portion continuing from the inner layer junction to the bottom layer.

    The Stub Via B example shows the through portion  originating from one internal signal layer and terminating on another internal signal layer. In this scenario, there are two stubs. The first stub is from the first internal layer junction to the top layer; the second stub is from the second internal layer junction to the bottom layer.

    Through Via

    imageThrough vias are the oldest and simplest via configurations originally used in 2-4 layer PCB designs. Since the signals originate and terminate from the outer layers of the PCB, there are no stubs. In multi-layer PCB applications, they are an inexpensive way to eliminate the resonance effects caused by stubs where other mitigation techniques are not practical or are too expensive.


    Blind/Buried Via

    imageBlind and buried vias are just like any other via, except  they do not go all the way through the PCB. A Blind Via connects one or more internal layers to only one external layer. Controlled-depth drilling is used to form the holes prior to plating.

    A buried via, on the other hand, is a plated hole which is completely buried within the board. It connects one or more internal layers and does not connect to an external layer. Using buried via technology is costly because the inner layers being interconnected need to be fully fabricated and plated before final lamination of the entire PCB.

    A micro-via is a form of blind via. Because the holes are so small (0.006 inches or less), they are formed using lasers, and cannot penetrate more than one or two layers at a time. They are most commonly used in high-density PCB designs like cell phones, or in FPGA and custom ASIC chip packaging.

    Back-drilled Via

    imageHigh speed point-point serial link based backplanes are often thick structures; due to the system architecture and card-card interconnect requirements. Back-drilling the via stub is common practice on thick PCBs to minimize stub length for bit-rates greater than 3Gb/s.

    Back-drilling is a process to remove the stub portion of a PTH via. It is a post-fabrication drilling process where the back-drilled hole is of larger diameter than the original PTH. This technology is often used instead of blind-via technology to remove the stubs of connector vias in very thick high-speed backplane designs. State of the art board fabrication shops are able to back-drill to within 8 mils of the signal layer to keep, so there will always be a small stub portion attached to the via.

    Back-drilling is not without limitations. Smaller vias and tighter pitch driven by large pin count BGA packages makes back-drilling impractical in these applications; due to drill bit size and tolerance issues. Fortunately, smaller via diameters limit the maximum PCB thickness due to aspect ratio; thereby limiting the length of the stub to the board thickness. Careful planning the high-speed layers within the stack-up is one way to control stub length.

    imageWe worry about stubs in high-speed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot of the channel. If one of these frequency nulls happen to line up at or near the Nyquist frequency of the bit rate, the received eye will be devastated resulting in a high bit-error-rate; even link failure.  A shorter stub length means these resonances will be pushed out further in frequency; ideally past the 5th harmonic of the Nyquist frequency as a rule of thumb.

    Rules of thumb, in general, are no substitute for actual modeling and simulation. You should never depend on them to sign-off the final design; but you can use them to gain some intuition before hand. With that in mind, you can estimate the maximum stub length in inches using the following equation:



    L Stub_max = maximum stub length in inches.

    Dkeff = effective dielectric constant of the material surrounding the via hole structure.

    BR = Bit rate in GB/s.

    For example, the maximum stub length at 5GB/s should be less than 0.120 inches in FR4 material with a Dkeff of 4.0 to ensure the first resonant frequency null is greater than 5 times the Nyquist frequency of the bit rate. If the stub length is greater than this, it does not mean the design will not work at 5GB/s. Depending on just how much longer it is means there will be less than optimum eye opening at the receiver.

    If you know the length of the stub, you can predict the fundamental resonant frequency, using the following equation:



    Stub_len = stub length in inches.

    fo = fundamental resonant frequency in GHz

    So, using the same  Dkeff of 4.0, and stub length of 0.120 inches, we calculated in the above example, the first resonant frequency null would occur at approximately 12.3 GHz. If we assume this is the 5th harmonic, then the Nyquist frequency is approximately 2.5GHz and the bit rate is 5Gb/s; which is where we started.

    Written by Bert Simonovich

    February 15, 2011 at 1:29 pm

    PCB Cross-sectional Geometries

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    PCB cross-sectional geometries describe the details of the dielectric substrates, traces and reference planes within a PCB stack-up.  Their physical relationship with one another can then be used to predict the characteristic impedance of the respective traces. There are only three generic cross-sectional geometries with variations within each. They are:

    • Coplanar
    • Microstripline
    • Stripline


    imageCoplanar geometry, or sometimes called coplanar waveguide (CPW), is a signal conductor sandwiched between two coplanar reference conductors or planes. These reference planes are usually ground. The characteristic impedance is controlled by the signal trace width and the gap between it and reference planes. This is a common transmission line structure for RF and microwave designs using single-sided printed circuit board technology. As a rule of thumb, the width of the reference plane on each side of the signal trace should be at least five times the distance between the left and right plane.

    Microstrip line:

    The microstrip line is the most popular transmission line geometry used in two or four layer printed circuit boards. The characteristic impedance is controlled by the signal trace width, on one side of the substrate, and the thickness of the substrate to the reference plane below it. The embedded microstrip line has the signal trace covered with prepreg or other dielectric material.

    Cross section views below showing Microstrip line (left) and embedded microstrip line (right).



    Cross section views below shows an example of single stripline (left) and dual stripline (right) geometries. These are geometries are typically found in multi-layer PCBs of 6 layers or more.  The characteristic impedance is controlled by the trace width, thickness and its proximity to the reference planes above and below.

    Single stripline has one signal layer sandwiched between two reference planes. If the signal layer is exactly spaced between the two reference planes, the geometry is called a symmetrical stripline; as opposed to an asymmetrical stripline, where the signal trace is offset from the center of the cross-section.

    Dual stripline geometries have two signal layers sandwiched between reference planes, and are mainly used to save layers; caveat is a trace on one layer is routed orthogonal to the trace on the other  to mitigate crosstalk.


    Differential Pair Geometry:

    Differential signaling is when a signal and its complement are transmitted on two separate conductors. These conductors are called a differential pair. In a PCB, both traces are routed together with a constant space between them as edge-coupled or broadside-coupled.

    imageEdge-coupled routes the traces side-by-side on the same layer as microstrip or stripline. The advantage is that any noise on the reference plane(s) is common to both traces and thus cancelled at the receiver. Most differential pairs are routed this way.

    Broadside-coupled routes one trace exactly over the other on 2 separate layers as dual stripline. Since each trace is more tightly coupled to its adjacent reference plane than the opposite reference plane, any noise on the planes will not be common to both traces and thus, will not be cancelled at the receiver. Because of this, and the fact that it usually results in a thicker PCB, this geometry is rarely used.

    Odd-Mode Impedance:

    imageConsider a pair of equal width microstrip line traces, labeled 1 and 2, with a constant spacing between them. Each individual trace, when driven in isolation, will have a characteristic impedance Zo, defined by the self-loop inductance and self-capacitance of the trace with respect to the reference plane.

    When a pair of traces are driven differentially, the mode of propagation is odd. If the spacing between the transmission lines is close, there will be electromagnetic coupling between the two traces. This coupling is defined by the mutual inductance and capacitance.

    The proximity of the traces to a reference plane(s) influences the amount of electromagnetic coupling between traces. The closer the traces are to the reference plane(s), the lower the self-loop inductance and stronger self-capacitance to the plane(s); resulting in a lower mutual inductance, and weaker mutual capacitance between traces. The result is a lower differential impedance.

    A 2D field solver is usually used to extract the parameters for a given geometry. Once the RLGC parameters are extracted, an L C matrix can be set up as follows:


    The self-loop inductance and self-capacitance for trace 1 and 2 are L11, C11, L22, C22 respectively. The off diagonal terms in each matrix, L12, L21, C12, C21, are the mutual inductance and mutual capacitance. We use the LC matrix to determine the odd-mode impedance.

    The odd-mode impedance is the impedance of one trace, of a differential pair, when driven differentially. It can be calculated by the following equation:



    Zodd = odd mode impedance

    Lo = self-loop inductance = L11 = L22

    Co = self-capacitance = C11 = C22

    Lm = mutual inductance = L12 = L21

    Cm = mutual capacitance = |C12 |=|C21|

    Even Mode Impedance:

    When current flows down both traces, of the same polarity, the mode of propagation is even and the coupling is positive. The even mode impedance can be calculated using the following equation:


    Differential Impedance:

    The differential impedance is twice the odd-mode impedance:


    Average Impedance:

    When current flows down two traces randomly, as if they were single-ended, the mode of propagation is a combination of odd and even. The average impedance of each trace is affected by its proximity to the adjacent trace(s); calculated by the following equation:


    Coupling Coefficient:

    The coupling coefficient, Kcc, is a number that conveys the amount of electromagnetic coupling between two traces. Knowing the odd and even mode impedance, Kcc can be calculated by the following equation:


    Backward Crosstalk Coefficient:

    Two traces near one another will couple a portion of its own signal to the other. If we consider one trace as the aggressor, and the other as the victim, the amount of coupled noise travelling backwards on the victim’s trace, opposite to the aggressor’s direction, is called Near-End crosstalk (NEXT) or backwards crosstalk. The amount of coupled noise, travelling in the same direction as the aggressor’s direction, is called Far-End crosstalk (FEXT).

    In stripline, there is little to no FEXT, but backwards crosstalk will saturate to a fraction of the amplitude of the aggressor’s voltage for the length of time the traces are coupled. This fraction of the aggressor’s voltage is  called the backward crosstalk coupling coefficient Kb. It is equal to one half of the coupling coefficient Kcc :



    A 8-9-8 mil differential pair; with 12mil core; 12 mil prepreg; Dk=4; stripline geometry; 1/2 oz copper; has the following R L G C matrix extracted from a 2D field solver:








    If the two traces are driven differentially, then the differential impedance is 100 Ohms and there is 13% coupling of the two traces. On the other hand, if the traces are driven single-ended then the characteristic impedance of each trace is 53 Ohms. With 9 mils of space between them, the backward crosstalk is 7%.

    If you increase the spacing between traces until Zodd equals approximately Zeven, the coupling will reduce to near zero, and there will be little backward crosstalk. Depending on your design and your noise budget, you may be able to live with a certain amount of backwards crosstalk. The only way to know the spacing between traces to achieve the budget is to plug in the numbers.


    I would like to thank my old Nortel colleague, the late Dick Goulette, for sharing these equations many years ago. They have served me well over the years.

    Written by Bert Simonovich

    February 7, 2011 at 8:52 pm

    Via Stub Termination -Brought to You by “The Stubinator”

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    Thick backplanes with long via stubs will cause unwanted resonances in the channel insertion loss compared to vias with little or no stub length as shown by the red and green traces in the plot of Figure 1. If these resonances occur at or near the Nyquist frequency of the bit rate, there will be little or no eye-opening left at the receiver.


    Figure 1 Topology circuit model of 2 differential vias with 30 inches of PCB etch. Insertion loss plot of Long via-no stub (green); short via-long stub (red); stub terminated (blue).  Received eye diagrams after optimized FFE receive equalization at 10GB/s. Modeled and simulated using Agilent ADS.

    In a typical backplane application, the signal entering the via structure from the top will travel along the through portion until it reaches the junction of the internal track and stub. At that point, the signal splits with some of the signal continuing along the trace, and the rest continuing along the stub. If the signal was Arnold Schwarzenegger, he would say, “I’ll be back!”. Having done this gig before, he knows that when he reaches the end of the stub it’s like hitting a brick wall; there’s no where to go but back up the stub. Like Arnold, when the signal reaches the end of the stub, it reflects back up the stub. When it arrives at the same junction, a portion combines with the original signal and the rest continues back toward the source. If the round trip delay is half a cycle, the two waves are completely 180 degrees out of phase and there is cancellation of the original signal. The frequency where maximum cancellation occurs is called the ¼ wave resonant frequency, fo. Resonance nulls due to stubs in an insertion loss plot, like the one shown in Figure 1, occurs at the fundamental frequency fo and at every odd harmonic.

    If you know the length of the stub (in inches) and the effective dielectric constant Dkeff, the resonant frequency can be predicted with the following formula:





    It is common practice to reduce stub lengths in high-speed backplane designs by back-drilling the stubs as close as possible to the active internal signal layer. This is a complex and costly process involving setting individual drill depths on a per board basis. Special design features must be designed into the artwork to set correct back-drill depth. Furthermore, it is difficult to verify ALL back-drilled holes were drilled correctly. I know of a case where a backplane came back and one via (that they knew of) had a significantly longer stub than was specified. The problem showed up by accident when they were characterizing the channel using a VNA and saw an unexpected resonant null in the SDD21 insertion loss plot. When all was said and done, it turned out there was a glitch in the fabricator’s software controlling the back-drilling process. There is no practical way to find these faults; short of doing VNA measurements on 100% of the back-drilled holes. With hundreds of them in a typical high-speed backplane, the cost would be prohibitive. Thus we have to trust the fabrication process of the vendor(s).

    If only there was a way to terminate the stub and get rid of all this back-drilling. Well there just might be a solution. After returning from last year’s DesignCon2010, I was intrigued by a paper presented by Dr. Nicholas Biunno on a new matched terminated stub technology  developed by Sanmina-SCI Corporation. They call this technology MTSviaTM and it allows the embedding of metal thin-film or polymer thick film resistors within a PCB stack-up during its fabrication. I like to call it “The Stubinator”. They developed this technology as an alternative to back-drilling. The beauty of this is you can terminate all the high-speed via stubs on just one resistive layer at the bottom of the PCB.

    Of course, for this to work, we need to terminate the vias with a resistance equal to the differential via impedance to be most effective. But how do we determine the via differential impedance without going through a bunch of trial and error builds?  In a DesignCon2009 paper titled, “Practical Analysis of Backplane Vias” I coauthored with Eric Bogatin from Bogatin Enterprises L.L.C., Sanjeev Gupta and Mike Resso from Agilent Technologies, we showed how you can model and simulate differential vias as simple twin-rod transmission line structures using simple transmission line circuit models as shown in Figure 1. You can download a copy of this award-winning paper from my web site at: .

    After determining  fo (either by measurement of a real structure or through 3D modeling) and solving for Dkeff by rearranging equation (1), the differential via impedance calculated using the following equation:







    s = the center to center spacing of the vias

    D = Drill diameter.


    The differential vias used in the model of Figure 1 has the following parameters:

    s = 0.059 in.

    D = 0.028 in.

    stub_length = 0.269 in.

    Dkeff = 6.14 by Equation (1) and fo=4.4GHz ;

    Zdiff = 66 Ohms by Equation (2).

    By adding a 66 Ohm resistor across the bottom of each via stub in the model, the blue trace in the plot shows the stub resonance has completely disappeared at the expense of an additional flat loss of about -10dB. The eye has opened up nicely.

    This “Stubinator” technology looks like it could be a promising alternative to back-drilling. It resolves many of the issues and limitations highlighted above. Combined with silicon that can accommodate the additional signal loading, it may extend the life of traditional copper interconnections for next generation of Ethernet standards beyond 10GB/s.

    Written by Bert Simonovich

    January 27, 2011 at 11:39 pm

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