Archive for the ‘Useful Equations’ Category
Singleended to MixedMode Conversions
Originally published in Signal Integrity Journal Magazine, July 2020
Signal Integrity (SI) engineers almost always have to work with Sparameters. If you haven’t had to work with them yet, then chances are you will sometime in your SI career. As speed moves up in the doubledigit GB/s regime, many industry standards are moving to serial linkbased architectures and are using frequency domain compliance limits based on Sparameter measurements.
A vector network analyzer (VNA) is the test instrument of choice to measure Sparameters from a device under test (DUT). By definition, each Sparameter (S_{ij}) is the ratio of the sine wave voltage coming out of a port to the sine wave voltage that was going in to a port (Equation 1). Each Sparameter is complex with a magnitude and a phase.
Equation 1
Sufficed to say, for mathematical reasons, the indexes refer to the port in which the voltages are coming or going. This is counter intuitive to our normal train of thought and is important to be cognisant of this relationship when working with Sparameters.
Singleended Sparameters
Figure 1 shows an example of a 1Port, 2Port and 4Port DUTs and their respective Sparameter matrices representing uniform transmission lines with respective port index labelling. Each Sparameter in the matrix are singleended measurements from one port to another.
A 1Port DUT has one Sparameter (S_{11}) shown in red. It is the ratio of the voltage coming out of Port 1 to the voltage going into Port 1. As a measure of reflected energy out of Port 1, it is also known as return loss (RL)
A 2Port DUT has 4 Sparameters shown in blue. Sparameters with the same index subscript numbers, i.e. S_{11,} S_{22} are RL. Sparameters with alternate index subscript numbers, are a measure of transmitted energy and is the ratio of the voltage coming out of a Port to the voltage going into the opposite Port. It is also known as insertion loss (IL). For example, S_{12} is the ratio of the voltage coming out of Port 1 to the voltage going into Port 2, whereas S_{21} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 1.
Figure 1 From left to right examples of 1Port (Red), 2Port (Blue), 4Port (Black) DUTs and their respective Sparameter matrices.
A 4Port DUT has 16 Sparameters, divided into 4 quadrants, shown in black. As you can see the number of Sparameter combinations is the square of the number of ports. In this example, the top left quadrant 1 and bottom right quadrant 4 are the same as individual 2Port DUTs with different port indices. They are described as:
Quadrant 1:

S_{11} is the ratio of the voltage coming out of Port 1 to the voltage going into Port 1. It is the RL out of Port 1.

S_{12} is the IL and is the ratio of the voltage coming out of Port 1 to the voltage going into Port 2. It is the IL from Port 2 to Port 1.

S_{21} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 1. It is the IL from Port 1 to Port 2. For a uniform transmission line, S_{21} = S_{12}.

S_{22} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 2. It is the RL out of Port 2. For a uniform transmission line, S_{22} = S_{11}.
Quadrant 4:

S_{33} is the ratio of the voltage coming out of Port 3 to the voltage going into Port 3. It is the RL out of Port 3

S_{34} is the ratio of the voltage coming out of Port 3 to the voltage going into Port 4. It is the IL from Port 4 to Port 3

S_{43} is the ratio of the voltage coming out of Port 4 to the voltage going into Port 3. It is the IL from Port 3 to Port 4. For a uniform transmission line, S_{43} = S_{34}.

S_{44} is the ratio of the voltage coming out of Port 4 to the voltage going into Port 4. It is the RL out of Port 4. For a uniform transmission line, S_{44} = S_{33}
Sparameters in the top right quadrant 2 and bottom left quadrant 3 describe the nearend and farend coupling of the respective ports. When unwanted coupling happens at the nearend, it is referred to as nearend cross talk, or NEXT. When it happens at the farend, it is known as farend crosstalk, or FEXT.
Quadrant 2:

S_{13} is the ratio of the voltage coming out of Port 1 to the voltage going into Port 3. It is the coupling or NEXT from Port 3 to Port 1.

S_{14} is the ratio of the voltage coming out of Port 1 to the voltage going into Port 4. It is coupling or FEXT from Port 4 to Port 1.

S_{23} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 3. It is coupling or FEXT from Port 3 to Port 2.

S_{24} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 4. It is coupling or NEXT from Port 4 to Port 2.
Quadrant 3:

S_{31} is the ratio of the voltage coming out of Port 3 to the voltage going into Port 1. It is the coupling or NEXT from Port 1 to Port 3.

S_{32} is the ratio of the voltage coming out of Port 3 to the voltage going into Port 2. It is coupling or FEXT from Port 2 to Port 3.

S_{41} is the ratio of the voltage coming out of Port 4 to the voltage going into Port 1. It is coupling or FEXT from Port 1 to Port 4.

S_{42} is the ratio of the voltage coming out of Port 4 to the voltage going into Port 2. It is coupling or NEXT from Port 2 to Port 4.
Although there is no industry standard for labeling a 4 or more port DUT, a practical way is to use the port order shown so that the 2Port DUT is a subset of the top left quadrant of the 4Port DUT. When you do this, the port order labeling is consistent as you increase the number of ports; with odd ports on the left and even ports on the right. S_{12} and S_{21} always describe the IL terms; while S_{13 }and S_{31} define the NEXT terms.
But sometimes 3^{rd} party 4port Sparameters are labeled with ports 1 and 2 are on the left side, while ports 3 and 4 are on the right side. In this configuration, S_{31} and S_{42} are now the IL terms. This is counter intuitive when moving from 2Port to 4 or more Port DUT and leading to potential confusion when cascading Sparameters to build a channel model, or converting to mixedmode Sparameters. Whenever you get Sparameter files from 3^{rd} party, it is always prudent to test it and compare IL plots against port order to ensure you are using them correctly.
Typically, 4port Sparameters are saved in Touchstone format with a .snp extension, where n is the number of ports. Many Electronic Design Automation (EDA) and circuit simulation software tools allows you to view and plot Sparameters from Touchstone files.
Figure 2 is a schematic of a 4port Sparameter component used in Keysight ADS. When the component is linked to appropriate .s4p touchstone file and ports connected as shown, the 16port Sparameter matrix can be plotted and analyzed.
Figure 2 Keysight ADS schematic used to plot 4Port singleended Sparameters.
The 1port and 2port Sparameters are included in the same plot as the 4port Sparameters plotted in Figure 3. The top left (red) and bottom right (green) quadrants plot the return loss (RL) and insertion loss (IL), while the top right (blue) and bottom left (magenta) quadrants plot the NEXT and FEXT.
Figure 3 An example of 4Port Sparameter singleended plots of a uniform transmission line.
Mixedmode Sparameters
SI engineers often have to check channel models and Sparameter measurements against industry standard compliance plots. Many of those plots are in terms of mixedmode Sparameters, which means the singleended measurements need to be converted to mixedmode matrix.
Two singleended transmission lines with coupling are also known as a differential pair, as shown in Figure 4. When we talk about singleended transmission lines with coupling, we are usually interested in their singleended properties like characteristic impedance (Zo), phase delay, and NEXT/FEXT relationships as described above.
But when we talk about a differential pair, we are interested in the mixedmode Sparameters like differential and common signals and how they interact within the pair. Because we are describing the exact same interconnect, they are equivalent.
When describing a differential pair, there are only four possible outcomes in response to an input signal as defined by the mixedmode Sparameter matrix:

A differential signal enters the differential pair and a differential signal comes out

A differential signal enters the differential pair and a common signal comes out

A common signal enters the differential pair and a differential signal comes out

A common signal enters the differential pair and a common signal comes out
Figure 4 Singleended vs mixedmode Sparameter matrices of two coupled transmission lines.
Mixedmode Sparameters in each quadrant are described as:
SDD Quadrant (Red):

SDD_{11} is the ratio of the differential signal coming out of Port 1 to the differential signal going into Port 1. It is the differential RL out of Port 1.

SDD_{12} is the ratio of the differential signal coming out of Port 1 to the differential signal going into Port 2. It is the differential IL from Port 2 to Port 1.

SDD_{21} is the ratio of the differential signal coming out of Port 2 to the differential signal going into Port 1. It is the differential IL from Port 1 to Port 2.

SDD_{22} is the ratio of the differential signal coming out of Port 2 to the differential signal going into Port 2. It is the differential RL out of Port 2.
SDC Quadrant (Blue):

SDC_{11} is the ratio of the differential signal coming out of Port 1 to the common signal going into Port 1.

SDC_{12} is the ratio of the differential signal coming out of Port 1 to the common signal going into Port 2.

SDC_{21} is the ratio of the differential signal coming out of Port 2 to the common signal going into Port 1.

SDC_{22} is the ratio of the differential signal coming out of Port 2 to the common signal going into Port 2.
SCD Quadrant (Magenta):

SCD_{11} is the ratio of the common signal coming out of Port 1 to the differential signal going into Port 1.

SCD_{12} is the ratio of the common signal coming out of Port 1 to the differential signal going into Port 2.

SCD_{21} is the ratio of the common signal coming out of Port 2 to the differential signal going into Port 1.

SCD_{22} is the ratio of the common signal coming out of Port 2 to the differential signal going into Port 2.
SCC Quadrant (Green):

SCC_{11} is the ratio of the common signal coming out of Port 1 to the common signal going into Port 1.

SCC_{12} is the ratio of the common signal coming out of Port 1 to the common signal going into Port 2.

SCC_{21} is the ratio of the common signal coming out of Port 2 to the common signal going into Port 1.

SCC_{22} is the ratio of the common signal coming out of Port 2 to the common signal going into Port 2.
Singleended Sparameters, with port order shown in Figure 4, can be mathematically converted into mixedmode Sparameters using equations shown in Table 1.
Alternatively, Keysight ADS can simplify this process using equations on 4Port singleended or using 4port Balun components, as shown in Figure 5.
Figure 5 Keysight ADS schematic used to convert from 4Port singleended to 2Port mixedmode Sparameters using equations or 4Port Balun components. Differential and common port numbering as D1, D2, C1, C2 respectively.
Figure 6 plots mixedmode Sparameters from equations in Table 1. Each quadrant is color coded to coincide with the respective table quadrants.
Figure 6 An example of 4Port Sparameter mixedmode plots of a differential transmission line.
References:
[1] M. Resso, E. Bogatin, “Signal Integrity Characterization Techniques”, International Engineering Consortium, 300 West Adams Street, Suite 1210, Chicago, Illinois 606065114, USA, ISBN: 9781931695930
https://www.amazon.com/SignalIntegrityCharacterizationTechniquesBogatinebook/dp/B07P9277WY/ref=sr_1_fkmr0_1?keywords=bogaitn+resso&qid=1581289220&sr=81fkmr0
[2] A. Huynh, M. Karlsson, S. Gong (2010). MixedMode SParameters and Conversion Techniques, Advanced Microwave Circuits and Systems, Vitaliy Zhurbenko (Ed.), ISBN: 9789533070872,InTech, Available from: http://www.intechopen.com/books/advancedmicrowavecircuitsandsystems/mixedmodesparametersandconversiontechniques.
[3] Alfred P. Neves, Mike Resso, and ChunTing Wang Lee, “Sparameters: Signal Integrity Analysis in the Blink of an Eye”, Signal Integrity Journal, https://www.signalintegrityjournal.com/articles/432sparameterssignalintegrityanalysisintheblinkofaneye
Keysight Advanced Design System (ADS) [computer software], (Version 2020). URL: http://www.keysight.com/en/pc1297113/advanceddesignsystemads?cc=US&lc=eng.
Differential Impedance and Why We Care
Originally published in Signal Integrity Journal April 14,2020
What is Differential Impedance and Why do We Care?
Simply put, differential impedance is the instantaneous impedance of a pair of transmission lines when two complimentary signals are transmitted with opposite polarity. For a printed circuit board (PCB) this is a pair of traces, also known as a differential pair. We care about maintaining the same differential impedance for the same reason we care about maintaining the same instantaneous impedance of a singleended (SE) transmission line: to avoid reflections.
There is really nothing special about differential pairs, other than maintaining the correct differential impedance. But you must understand the implications of the spacing between the traces in a pair.
The differential impedance is simply twice the oddmode impedance of each trace. SE impedance is the impedance of a single trace and only equals the oddmode impedance when there is little or no intrapair coupling between them. When the traces are brought closer together, the differential impedance is reduced, unless the line widths are adjusted to compensate. (More about this later.)
Figure 1 shows the effect on intrapair coupling of a pair of edgecoupled stripline traces driven differentially. The top figure shows electromagnetic fields surrounding a loosely coupled pair of traces 3.5 linewidths apart. The bottom figure shows a closely coupled pair at 1.5 linewidths apart. The red plus trace is current flowing into the page while the minus blue trace is current flowing out of the page.
The circular lines surrounding each trace are the magnetic fields representing loop inductance. The direction of rotation is based on current direction, using the righthand rule. The electric field (efield) lines are perpendicular to the magnetic field lines. They are a measure of capacitance.
Figure 1. Effect on intrapair coupling of a pair of edgecoupled stripline traces driven differentially. Top figure shows electromagnetic fields surrounding a loosely coupled pair of traces 3.5 linewidths apart. Bottom figure shows a closely coupled pair at 1.5 linewidths apart.
When the traces are loosely coupled, the electric and magnetic field lines are fairly symmetrical around each trace, and are mirror images of one another about the center line between them. Most of the respective efield coupling is to the reference ground planes. As the traces are moved closer to one another, the counterrotating rings compress about the centerline, lowering the inductance. At the same time, more of the efield lines along the inside edge of each trace tend to couple to one another, increasing the capacitance.
Because of the way the EMfields interact along the centerline, we can think of it as a virtual ground (VGND) reference plane. They behave exactly the same way as if there is a solid reference plane between them.
OddMode Impedance
Consider a pair of equal width microstrip line traces, labeled 1 and 2, with a constant spacing between them as shown in Figure 2. Assuming lossless transmission lines, each individual trace, when driven in isolation, will have a SE characteristic impedance Zo, defined by the selfloop inductance (L11, L22) and selfcapacitance (C11, C22) with respect to the GND reference plane.
When the pair of traces are driven differentially, the mode of propagation is odd. The electromagnetic field interaction is shown in Figure 1. When the intrapair spacing is close, there will be electromagnetic coupling defined by the mutual inductance (Lm) and mutual capacitance (Cm).
The proximity of the traces to a reference plane influences the amount of electromagnetic coupling between traces. The closer the traces are to the reference plane, the lower the selfloop inductance and stronger selfcapacitance; resulting in a lower mutual inductance, and weaker mutual capacitance between traces. The end result is a lower differential impedance.
Figure 2. Pair of microstrip traces showing selfloop inductance (L11, L22), selfcapacitance (C11, C22), mutual capacitance (Cm) and mutual inductance (Lm) when line 1 and line 2 are driven differentially.
A 2D field solver is usually used to extract the parameters for a given geometry. Once the resistance, inductance, conductance, and capacitance (RLGC) parameters are extracted, an L C matrix can be set up as follows:
L11 L12 C11 C12
L21 L22 C21 C22
The selfloop inductance and selfcapacitance for trace 1 and 2 are L11, C11, L22, C22 respectively. In a perfectly symmetrical differential pair, the offdiagonal (12, 21) terms in each matrix are the mutual inductance and mutual capacitance respectively. The LC matrix can be used to determine the oddmode impedance. It can be calculated by the following equation [1]:
Equation 1
Where:
Zodd = odd mode impedance
Ls = selfloop inductance = L11 = L22
Cs = selfcapacitance = C11 = C22
Lm = mutual inductance = L12 = L21
Cm = mutual capacitance = C12 =C21
Example
A Polar SI9000 field solver is used to compare a loosely coupled pair, with 4 mil traces, separated by 20 mil space, vs. a SE transmission line with the same dielectric thickness (see Figure 3). The LC matrix was extracted at 10GHz. As can be seen, the oddmode impedance of the loosely coupled pair equals the characteristic impedance of the SE trace, and thus differential impedance would be the same.
Figure 3. Comparison of a loosely coupled pair (left), with 4 mil traces, separated by 20 mil space, vs. a SE transmission line (right) with the same dielectric thickness. Oddmode impedance of the loosely coupled pair equals the characteristic impedance of the SE trace.
But if you route a pair of traces with close coupling, the oddmode impedance is less than the SE impedance for the same trace width (unless you adjust the line width). For example, on the left side of Figure 4, a 444 mil geometry has a differential impedance of 91 Ohms. In order to get 100 Ohms differential, the line width must be reduced to 3.35 mils and space adjusted to 4.65 mils to keep the same 12 mil centercenter pitch, shown on right.
Figure 4. Comparison of 444 mil geometry (left) vs. 3.354.653.35 geometry (right) to achieve 100 Ohm differential impedance for the same centercenter pitch.
But it doesn’t end there.
For some industry standards, there is usually a very short reach (VSR) spec which has a maximum channel loss defined. For example, the IEEE 802.3 CAUI4 chipmodule (C2M) spec budgets 7.5 dB at 12.89 GHz Nyquist frequency from the chip’s pins to a faceplate module’s pins, e.g. small formfactor pluggable (SFP) module. Because of modern topofrack routers and switches, it is not unusual to have 10 or more inches between the main switch chip and SFP module, the differential pair geometry design becomes important to satisfy both differential impedance and insertion loss (IL).
Reduced line width and tighter coupling results in higher loss over the length of the channel. Using the above examples, differential IL is plotted in Figure 5 for all three differential pairs. Loose coupling is shown in green; tight coupling without line width adjustment (Tight1) is shown in red, while tight coupling with line width adjustment (Tight2) is shown in blue.
As you can see, there is about a half dB difference at 12.89 GHz between loose coupling and both tight coupling examples over 10.6 inches. Tight coupling lowers IL, regardless if line width is adjusted to meet differential impedance. In this example, there is only 0.1 dB delta between Tight1 and Tight2, which suggests most of the higher loss is due to tighter coupling.
Figure 5. Differential IL comparison of loose coupling (green); Tight1 coupling without line width adjustments (red) and Tight2 coupling with line width adjustment (blue).
This can be explained by reviewing SE to differential mixedmode conversion. Given a 4port Sparameter, with SE port order as shown in Figure 6, the differential IL is determined by;
Equation 2
Where:
SDD21 = the differential IL defined by the ratio of the differential signaling coming out of port 2 to the differential signal going into port 1
S21 = the SE IL defined by the ratio of the SE signaling coming out of port 2 to the SE signal going into port 1
S43 = the SE IL defined by the ratio of the SE signaling coming out of port 4 to the SE signal going into port 3
S23 = farend crosstalk coupling from port 3 to port 2
S43 = farend crosstalk coupling from port 4 to port 3
As you can see from Equation 2, when the traces get closer together, and the coupling terms get larger, differential IL increases.
Figure 6. SE 4port Sparameter port labeling.
Figure 7 plots differential TDR of all three examples. The steeper monotonic rise of the blue trace is due to higher resistive loss of 3.35 mil traces, as compared to the 4 mil traces in the other two examples.
Figure 7. Differential TDR comparison of loose coupling (green); Tight1 coupling without line width adjustments (red) and Tight2 coupling with line width adjustment (blue).
To summarize then, it doesn’t matter if a differential pair is tightly coupled or loosely coupled. Properly engineered, both can be designed to properly match the output driver impedance. But as we have seen, each will have advantages and disadvantages.
Tighter coupling gives you better routing density at the expense of higher loss. Loose coupling allows for easier routing around obstacles and less loss. But in either case, they must be designed and measured for differential impedance.
So why is this important?
PCB fabrication shops use impedance as a metric to determine if the board has been fabricated to specification. Because the oddmode impedance of a tightly spaced pair of traces depends on driving both traces differentially, you will not be able to determine the differential impedance by just measuring SE impedance of a tightly coupled pair like you could with two uncoupled traces.
References:

E. Bogatin, “Signal Integrity Simplified”, 3rd edition, Prentice Hall PTR, 2018

Keysight Advanced Design System (ADS) [computer software], (Version 2020)

Polar Instruments Si9000e [computer software] Version 2017
CannonballHuray Model Demystified
Recently on the SIList there was great debate on whether or not my Cannonball model can be used to determine surface ratio and radius of sphere parameters needed for Huray roughness model from data sheets alone.
The author of this paper, “Conductor surface roughness modeling: From “snowballs” to “cannonballs”, [1] argues it is impossible to accurately model transmission lines from data sheets alone and seems to imply that because I had measured data in advance that I had magically “adjusted” R_{z} parameter to get such good correlation to measurements in my EDICon 2016 paper, “Practical Model of Conductor Surface Roughness Using Cubic Closepacking of Equal Spheres” [5].
Unfortunately his paper has created more confusion than clarity. To be clear, there is only ONE “Cannonball” model, and it is based on the cubic close packing of equal spheres, also known as facecentered cubic (FCC) packing.
The author of [1] also advocates using a material model identification methodology, similar to what I like to call the Design Feedback Method, shown in Figure 1. The author believes it is the only “accurate” way of determining printed circuit board (PCB) material properties for modeling.
Figure 1 Design Feed Back Method flow chart
This involves designing, building and measuring a test coupon with the intended PCB trace geometry to be used in final design. After modeling and tuning various parameters to best fit measured data, material parameters are extracted and then used in channel modeling software to design the final product.
The problem with this approach for many small companies is: TIME, RESOURCES, and MONEY.

Time to define stackup and test structures.

Time to actually design a test coupon.

Time to procure raw material – can take weeks, depending on scarcity of core/prepreg material.

Time to fabricate the bare PCB.

Time to assemble and measure.

Time to crosssection and measure parameters.

Time to model and fit parameters to measurements.
Then there is the issue of resources, which include having the right test equipment and trained personnel to get trusted measurements.
In the end this process ultimately costs more money, and material properties are only accurate for the sample from which they were extracted for the software and roughness model used. There is no guarantee extracted parameters reflect the true material properties.
There will be variation from sample to sample built from the same fab shop and more so from different fab shops because they have a different etch line and oxide alternative process.
For example Figure 2 shows measurements from two boards of the same design. As you can see there are differences in both insertion loss and TDR plots. Which curve do we use to fit parameters for material extraction to use in simulations? How many do we have to build and test to get a statistical sample of reality? How much time will this take? And how much money will it cost, especially if several PCB stackup geometries are required?
Figure 2 Comparison of insertion loss and TDR measurements of two boards of the same design
But, as Eric Bogatin often likes to say, “Sometimes an OK answer NOW is better than a good answer late”. For many signal integrity engineers, and design consultants, like myself, have to come up with an answer sooner, rather than later for many reasons. And depending on the issue at hand, those answers may be good enough. This was the initial motivation for my research.
So where do we get these parameters? Often the only sources are from manufacturers’ data sheets alone. But in most cases, the numbers do not translate directly into parameters needed for the EDA tools.
This paper will revisit the Cannonball model as it applies to the CMP28 reference platform from Wildriver Technology [14], and as part of it I will show:

How to determine effective dielectric constant (D_{keff}) due to roughness from data sheets alone.

How to apply my simple Cannonball stack model to determine roughness parameters needed for Huray model from data sheets alone.

How to apply these parameters using Simbeor software [10].

How to pull it all together with a simple case study.
But before we get into it, it is important to give a bit of background on material properties and PCB fabrication process.
Electrodeposited Copper
Electrodeposited (ED) copper is widely used in the PCB industry due to its low cost. A finished sheet of ED foil has a matte side and drum side. The matte side is usually treated with tiny nodules and is the side bonded to the core laminate. The drum side is always smoother than the matte side. For high frequency boards, sometimes the drum side of the foil is treated instead and bonded to the core. In this case it is known as reversed treated foil (RTF).
IPCTM6502.2.17A defines the procedure for determining the roughness or profile of metallic foils used on PCBs. Profilometers are often used to quantify the roughness tooth profile of electrodeposited copper.
Nodule treated tooth profiles are typically reported in terms of 10point mean roughness (R_{z}). Some manufacturers may also report root mean square (RMS) roughness (R_{q}). For standard foil this is the matte side. For RTF it is the drum side. Most often the untreated, or prepreg side, reports average roughness (R_{a}) in manufacturers’ data sheets.
With the realization of roughness having a detrimental effect on insertion loss (IL), copper suppliers began providing very low profile (VLP) and ultralow profile (ULP) class of foils. VLP foils have treated roughness profiles less than 4 μm while ULP foils are less than 2 μm. Other names for ULP class are HVLP or eVLP, depending on the foil manufacturer.
It is important to obtain the actual vendor’s copper foil data sheet used by the respective laminate supplier for accurate modeling.
Oxide/Oxide Alternative Treatment
In order to promote good adhesion of copper to the prepreg material during the PCB lamination process, the copper surface is treated with chemicals to form a thin, nonconductive film of black or brown oxide. The controlled oxidation process increases the surface area, which provides a better bond between the prepreg and the copper surface. It also passivates the copper surface to protect it from contamination.
Although oxide treatment has been used for many years, eventually the industry learned that the lack of chemical resistance resulted in pink ring, which is indicative of poor adhesion between copper and prepreg. This weakness has led to oxide alternative (OA) treatments which rely on some sort of etching process, but no oxide layer is formed.
With the push for smoother copper to reduce conductor loss, newer chemical bond enhancement treatments, working at the molecular level, were developed to maintain copper smoothness, yet still provide good bonding to the prepreg.
Since OA treatment is applied to the drum side of the foil during the PCB Fabrication process, the OA roughness numbers should be used instead of R_{a} specified in foil manufacturer’s data sheets. RTF foil is modeled differently and discussed later in the case study.
Tale of Two Data Sheets
Everyone involved in the design and manufacture of PCBs knows the most important properties of the dielectric material are the dielectric constant (D_{k}) and dissipation factor (D_{f }).
Using D_{k} / D_{f }numbers for stackup design and channel modeling from “Marketing” data sheets, like the example shown in Figure 3, will give inaccurate results. These data sheets are easily obtained when searching laminate supplier’s web sites.
Figure 3 Example of a “Marketing” data sheet easily obtained from laminate supplier’s web site. Source Isola Group.
Instead, real or “Engineering” data sheets, which are used by PCB fabricators to design stackups, should be used for PCB interconnect modeling. These data sheets define the actual thickness, resin content and glass style for different cores and prepregs. They include D_{k }/ D_{f }over a wide frequency range; usually from 100 MHz10GHz.
Figure 4 Example of an “Engineering” data sheet showing D_{k}/D_{f} for different glass styles and resin content over frequency. Source Isola Group.
Effective D_{k} Due to Roughness
Many engineers assume D_{k }published is the intrinsic property of the material. But in actual fact, it is the effective dielectric constant (D_{keff}) generated by a specific test method. When simulations are compared against measurements, there is often a discrepancy in D_{keff}, due to increased phase delay caused by surface roughness.
D_{keff} is highly dependent on the test apparatus and conditions of how it is measured. One method commonly used by many laminate suppliers is the clamped stripline resonator test method, as described by IPCTM650, 2.5.5.5, Rev C, Test Methods Manual.
The measurements are done under stripline conditions using a carefully designed resonant element pattern card made with the same dielectric material to be tested. As shown in Figure 5, the card is sandwiched between two sheets of unclad dielectric material under test. Then the whole structure is clamped between two large plates; each lined with copper foil and are grounded. They act as reference planes for the stripline.
Figure 5 Illustration of clamped stripline resonator test method, as described by IPCTM650, 2.5.5.5, Rev C, Test Methods Manual
This method assures consistency of product when used in fabricated boards. It does not guarantee the values directly correspond to design applications.
This is a key point to keep in mind, and here is why.
Since the resonant element pattern card and material under test are not physically bonded together, there are small air gaps between the various layers that affect measured results. The small air gaps result in a lower D_{keff} than what is measured in real applications using foil with different roughness bonded to the same core laminate. This is the primary reason for phase delay discrepancy between simulation and measurements.
If D_{k} and R_{z} roughness parameters from the manufacturers’ data sheets are known, then the effective D_{k} due to roughness (D_{keff}_{_rough}) of the fabricated core laminate can be estimated by [2]:
Equation 1
where: H_{smooth} is the thickness of dielectric from data sheet; R_{z} is 10point mean roughness from data sheet; D_{k} is dielectric constant from data sheet
Most EDA tools include a wideband causal dielectric model. To use it, you must enter D_{k }and D_{f} at a particular frequency. I found it is usually best to use the values near the Nyquist frequency of the baud rate.
Modeling Copper Roughness
“All models are wrong but some are useful”– a famous quote by George E. P. Box, who was a British statistician in the mid20^{th} century. The same can be said when using various roughness models.
For example many roughness models require RMS roughness numbers, but often R_{z} is the only number available in data sheets, and vice versa. If R_{z} is defined as the sum of the average of the five highest peaks and the five lowest valleys of the roughness profile over a sample length, and R_{q} is the RMS value of that profile, then the roughness can be modeled as a triangular profile with a peak to valley height equal to R_{z}, as illustrated in Figure 6.
Figure 6 Triangular roughness profile model with peak to valley height equal to 10point mean roughness R_{z}.
If we define the RMS height of the triangular roughness profile is equal to ∆, then:
Equation 2
And likewise, if we assume ∆ ~ R_{q}, then:
Equation 3
Several modeling methods were developed over the years to determine a roughness correction factor (K_{SR}). When multiplicatively applied to the smooth conductor attenuation (α_{smooth}), the attenuation due to roughness (α_{rough}) can be determined by:
Equation 4
Huray Model
In recent years, the Huray model has found its way into popular EDA software due to the continually increasing need for better modeling accuracy. The model is based on a nonuniform distribution of spherical shapes resembling “snowballs” and stacked together forming a pyramidal geometry.
By applying electromagnetic wave analysis, the superposition of the sphere losses can be used to determine the total loss of the structure. Since the losses are proportional to the surface area of the roughness profile, an accurate estimation of a roughness correction factor (K_{SRH}) can be analytically solved by [4]:
Equation 5
Although it has been proven to be a pretty accurate model, it relied on analysis of scanning electron microscopy (SEM) pictures of the treated surface and tuning of parameters for best fit to measured data. This is not a practical solution if all you have is roughness parameters from manufacturers’ data sheets.
CannonballHuray Model
Building upon the work already done by Huray, and using the Cannonball stack principle, the sphere radius and flat base area parameters are easily estimated solely from roughness parameters published in manufacturers’ data sheets.
As illustrated in Figure 7 there are three rows of equal sized spheres stacked on a square tile base. Nine spheres are on the first row, four spheres in the middle row, and one sphere on top. This stacking arrangement is known as closepacking of equal spheres, but more commonly known as the “Cannonball” stack due to the method used by sailors to stack actual cannonballs aboard ships.
Figure 7 CannonballHuray physical model. The height of the stack is the RMS height of the peak to valley profile equal to R_{z} from data sheets.
If we could peer into the stack and imagine a pyramid lattice structure connecting to the center of all the spheres, then the total height is equal the height of two pyramids plus the diameter of one sphere.
Given the height of the Cannonball stack (∆) is equal to the RMS value of the peak to valley roughness profile; then from method described in my earlier papers, determining the sphere radius (r ), from R_{z} found in data sheets, can be further simplified and approximated as [13]:
and base area (A_{flat}) as:
Equation 7
Because the model assumes the ratio of A_{matte}/A_{flat} = 1, and there are only 14 spheres, the original CannonballHuray model can be further simplified to:
Equation 8
where: K_{CH} (f) = CannonballHuray roughness correction factor, as a function of frequency; δ (f) = skindepth, as a function of frequency in meters; r = the radius of spheres in meters (Equation 6)
CMP28 Case Study Revisited
To test the accuracy of the model, stackup details and measured data from a CMP28 test platform, design kit, courtesy of Wildriver Technology, shown in Figure 8, was used for model validation. The PCB stackup is shown in Figure 9
Two different sets of Sparameter (s2p) files from a 2 inch and 8 inch singleended (SE) stripline traces shown were used in this study. The original set of measurements, from my previous papers, and a second set provided as part of CMP28 design kit from another PCB were used for model correlation.
The 6 inch transmission line segment Sparameter data was deembedded using Ataitec ISD software [8] for both sets of data.
Figure 8 Photo of a portion of CMP28 test platform courtesy of Wildriver Technology used for model validation.
Figure 9 CMP28 PCB Stackup
The PCB was fabricated with Isola FR408HR 3313 core and prepreg, with 1 oz. RTF. D_{k} and D_{f} at 10GHz were obtained from the FR408HR data sheet found on their web site and shown in Figure 10 & Figure 11.
Figure 10 Isola FR408HR data sheet used for core dielectric properties.
Figure 11 Isola FR408HR data sheet used for prepreg dielectric properties.
The foil used on FR408HR core laminates is MLS, Grade 3, controlled elongation RTF from Oakmatsui. Roughness Rz parameters for drum and matte sides are 120μin (3.048 μm) and 225μin (5.715μm) respectively for 1 oz. copper foil.
Figure 12 MLS RTF foil data sheet used on FR408HR laminate.
An oxide or oxide alternative (OA) treatment is usually applied to the copper surfaces prior to final PCB lamination. When it is applied to the matte side of RTF, it tends to smoothen the macroroughness slightly. At the same time, it creates a surface full of microvoids which follows the underlying rough profile and allows the resin to fill in the cavities, providing a good anchor.
MultiBond MP from Macdermid Enthone is an example of an oxide alternative microetch treatment commonly used in the industry. Typically 50 μin (1.27μm) of copper is removed when the treatment is completed, depending on the board shop’s process control, as per Figure 13.
In a subsequent paper by J.A. Marshall, presented at IPC APEX 2015 titled, “Measuring Copper Surface Roughness for High Speed Applications” [11], there is data supporting the hypothesis that RTF roughness gets smoother after OA application.
Figure 13 Macdermid Enthone MultiBond MP data sheet reference from their web site.
Table 1 summarizes the PCB design parameters, dielectric material properties and copper roughness parameters obtained from respective manufactures’ data sheets.
Table 1 CMP28 Test Board and Data Sheet Parameters
Parameter  FR408HR/RTF 
Dk Core/Prepreg  3.65/3.59 @10GHz 
Df Core/Prepreg  0.0094/0.0095 @ 10GHz 
R_{z} Drum side  3.048 μm 
R_{z} Matte side before Microetch  5.715 μm 
R_{z }Matte side after Microetch  4.445 μm 
Trace Thickness, t  1.25 mil (31.7μm ) 
Trace Etch Factor  60 deg 
Trace Width, w  11 mils (279.20 μm) 
Core thickness, H1  12 mils (304.60 μm) 
Prepreg thickness, H2  10.6 mils (269.00 μm) 
GMS trace length  6 in (15.23 cm) 
From Table 1 and by applying Equation 1, D_{keff} of core and prepreg due to roughness were determined to be:
Next, the Cannonball model’s sphere radiuses, for matte and drum side of the foil, were determined to be:
Because most EDA tools only allow a single value for the radius parameter, the average radius (r_{avg}) was determined to be:
Equation 9
Simbeor electromagnetic software from Simberian Inc. [10] was used for modeling the transmission lines. It includes the latest and greatest dielectric and conductor roughness models, including the HurayBracken causal metal model.
Solution explorer pane and solution tree, as shown in Figure 14, allows you to edit and view solution data as a tree structure. All parameters from Table 1 were entered here.
Simbeor requires two parameters; roughness factor (RF1) and sphere radius (SR1). Because the Cannonball model always has N=14 spheres and base area (A_{flat}) is always 36r^{2}, r^{2} cancels out and RF1 can be simplified to:
Equation 10
Sphere radius (SR1) is r_{avg} = 0.225 as calculated from Equation 9.
Figure 14 Simbeor Solution Explorer Pane and Solution Tree
The wideband causal dielectric model option was used to model dielectric properties over frequency. Effective D_{k} due to roughness for core and prepreg, calculated above, were substituted instead of data sheet values. Standard copper resistivity of 1.724e8 ohmmeter was used.
After the transmission lines were modeled and simulated, the Sparameter results were saved in touchstone format. Keysight ADS [5] was used for further simulation analysis and comparison.
D_{keff} can be derived from phase delay. This is also known as time delay (TD) and is often used as a metric for simulation correlation accuracy for phase. TD, as a function of frequency, in seconds, is calculated from the unwrapped measured transmission phase angle, and is given by:
Equation 11
and:
D_{keff }, as a function of frequency, is then given by:
Equation 12
where:c = speed of light (m/s); Length = length of conductor (m)
Figure 15 compares the simulated results vs measurement of a 6inch, deembedded stripline trace. The red plots are measured from CMP28 design kit data. The data was bandwidth limited to 35 GHz. The blue plots are the original measured data used in my previous paper [5]. The green plots are modeled with data sheet values only with oxide alternative treatment applied. SE IL is shown on the left and D_{keff} is shown on the right. As can be seen, there is excellent correlation.
Figure 15 Measured vs simulated insertion loss (left) and D_{keff }(right) with OA etch treatment applied.
The author of [1] suggests is that because I had the measured data, R_{z} was “adjusted” to show excellent results. What he is implying is my “adjusting” the roughness, due to the oxide treatment, was the reason for such good results, in spite of the fact Macdermid’s OA data sheet reports typical 50 μin of copper removal after treatment and data from [11] showing RTF gets slightly smoother after OA treatment.
So ok, let’s see what happens if I didn’t adjust the roughness due to OA treatment. Instead of using R_{z }matte side after microetch (4.445 μm ) roughness, we will use 5.715 μm from data sheet.
This will affect D_{keff }of prepreg and average sphere radius r_{avg}_{ , }so we will recalculate them:
And average radius is:
Figure 16 compares the simulated results vs measurement. The red plots are measured from CMP28 design kit data. The blue plots are the original measured data used in my previous paper [5]. The green plots are modeled with data sheet values only without oxide alternative treatment applied. SE IL is shown on the left and D_{keff} is shown on the right.
As can be seen, there is still excellent correlation with insertion loss even though OA was not considered. As expected using the rougher number would increase effective Dk. But in the end the TDR plots in Figure 17shows impedance change is negligible.
Figure 16 Measured vs simulated insertion loss (left) and phase delay (right) without OA etch treatment applied.
Figure 17 Measured vs simulated TDR plots with OA etch treatment (left) and without (right).
Summary and Conclusions
By using CannonballHuray model, with copper foil roughness and dielectric material properties obtained solely from respective manufacturers’ data sheets, practical PCB interconnect modeling for highspeed design is now achievable using commercial fieldsolving software employing Huray model.
Measured results from two different boards confirmed there are variations due to manufacturing that would affect material model extraction method accuracy.
When oxide alternative treatment was not considered, even though the matte side roughness of RTF gets smoothened during the PCB fabrication process, the simulated results still show excellent correlation to the original measured data from previous paper [5].
References
[1] Y. Slepnev, “Conductor surface roughness modeling: From “snowballs” to “cannonballs”.
[2] B. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”. DesignCon 2017, Proceedings, Santa Clara, CA, 2017
[3] L. Simonovich, “Practical method for modeling conductor roughness using cubic closepacking of equal spheres,” 2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), Ottawa, ON, 2016, pp. 917920. doi: 10.1109/ISEMC.2016.7571773.
[4] Huray, P. G. (2009) “The Foundations of Signal Integrity”, John Wiley & Sons, Inc., Hoboken, NJ, USA., 2009
[5] L.Simonovich, “Practical Model of Conductor Surface Roughness Using Cubic Closepacking of Equal Spheres”, EDICon 2016, Boston, MA
[6] Keysight Advanced Design System (ADS) [computer software], (Version 2017). URL: http://www.keysight.com/en/pc1297113/advanceddesignsystemads?cc=US&lc=eng.
[7] Isola Group S.a.r.l., 3100 West Ray Road, Suite 301, Chandler, AZ 85226. URL: http://www.isolagroup.com/
[8] Ataitec, URL: http://ataitec.com/products/isd/
[9] V. DmitrievZdorov, B. Simonovich, I. Kochikov, “A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics”, DesignCon 2018 Proceedings, Santa Clara, CA, 2018
[10] Simberian Inc., 2629 Townsgate Rd., Suite 235, Westlake Village, CA 91361, USA, URL: http://www.simberian.com/
[11] John A. Marshall, “Measuring Copper Surface Roughness for High Speed Applications”, IPC APEX Expo 2015.
[12] Macdermid Enthone, Multibond MP, Inner Layer Oxide Alternative Bonding. URL: https://electronics.macdermidenthone.com/productsandapplications/printedcircuitboard/surfacetreatments/innerlayerbonding
[13] B. Simonovich, “PCB Interconnect Modeling Demystified”. DesignCon 2019, Proceedings, Santa Clara, CA, 2019.
[14] Wild River Technology LLC 8311 SW Charlotte Drive Beaverton, OR 97007. URL: https://wildrivertech.com/
Via Stubs Demystified
We worry about via stubs in highspeed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot (IL) of the channel. But are all via stubs bad? Well, as with most answers relating to signal integrity, “It depends.”
If one of these frequency nulls happen to line up at or near the Nyquist frequency of the bit rate (i.e. 1/2 of the bitrate), the received eye will be devastated, resulting in a high biterrorratio (BER), or even link failure.
Figure 1 shows simulation results of two backplane channels. On the left are measured SDD21 insertion loss and eye diagram of a 10 GB/s, nonreturntozero (NRZ) signal, with short through vias and long stubs ~ 270 mils. On the right, shows measured SDD21 IL and eye diagram of a channel with long through vias and shorter stubs ~ 65 mils
Because the ¼ wave resonant null occurs at a frequency ~ 4. 4 GHz, this is near the Nyquist frequency for 10 GB/s. As can be seen, the eye is totally closed for the long stub case. But when the shorter stub case is simulated, the eye is open with plenty of margin.
So how does a via stub cause ¼ wave resonance? This question can be explained with the aid of Figure 2. Starting on the left, we see a via with two sections. The through (thru) part is the top portion connecting a device pin to an inner layer trace of a printed circuit board (PCB). The stub portion is the lower portion and is an open circuit.
On the right a sinusoidal signal is injected into the pin at the top of the via and travels along the thru portion until it reaches the junction of the internal trace and stub. At that point, the signal splits. Some of it travels along the trace, and the rest continues down the stub. Once it reaches the bottom, it reflects back up. When it reaches the trace junction, it splits again with a portion traveling along the trace and the rest back to the source.
If f_{ }is the frequency of a sine wave, and the time delay (TD) through the stub portion equals a ¼ wavelength, then when it reflects at the bottom and reaches the junction again, it will be delayed by ½ a cycle and cancels most of the original signal.
Figure 2 Illustration of a ¼ wave resonance of a stub. If f = frequency where TD = ¼ wavelength, then when 2TD = ½ cycle minimum signal received.
Resonance nulls occurs at the fundamental frequency ( f_{o}) and at every odd harmonic. If you know the length of the stub (in inches) and the effective dielectric constant (Dk_{eff}), surrounding the via hole structure, the resonant frequency can be predicted by:
Equation 1
Where: f_{o} is the ¼ wave resonant frequency (GHz); c is the speed of light (~11.8 in/ns); Stub_length is inches.
You will find that Dk_{eff} is not the same as the bulk Dk published in laminate manufacturers’ data sheets. It is typically higher. A higher Dk_{eff} increases phase delay through the via resulting in a lower resonant frequency.
One reason is excess capacitance from the via pads as well as the via barrel’s proximity to the clearance hole openings (also known as antipads) in plane layers. The other is because of the anisotropic nature of the laminate material.
For the example in Figure 1, the ¼ wave resonant frequency of the long via stub is ~ 4.4 GHz. With a stub length of ~ 270 mils, this gives a Dk_{eff} of 6.16, which is considerably higher than the published bulk Dk of 3.65. When you model a via in an electromagnetic (EM) 3D field solver, it automatically accounts for the excess capacitance, but you will still need to compensate for the anisotropic nature of the dielectric.
A material is anisotropic when there are different values for parallel (xy) vs perpendicular (z) measured values for dielectric constant. Dielectric constant and loss tangent, as published in manufacturers’ data sheets, report perpendicular measured values. For FR4 fiberglass reinforced laminates, anisotropy can range from 15% 25% higher. The bad news is these numbers are not readily available from data sheets.
For differentially driven vias with plane layers evenly distributed throughout the entire stackup, Dk_{eff} can be roughly estimated by:
Equation 2
Where: Dk_{xy} is the dielectric constant adjusted for anisotropy (15%25% higher); Dk_{z} is the bulk dielectric constant from data sheets; s is viavia spacing; drillØ is drill diameter; H and W are antipad shape dimensions as shown in Figure 3 .
Figure 3 Antipad parameters for Equation 2.
The effects of via stubs can be mitigated by: using blind or buried vias; backdrilling; or by using thru vias only (i.e. from top layer to bottom layer). Practically, the shortest stub that can be achieved by backdrilling is on the order of 5 to 10 mils.
As a rule of thumb, we usually strive to have an interconnect bandwidth (BW) to be five times the Nyquist frequency of the bitrate. Since a ¼wave resonant null behaves somewhat like a notch filter, depending on the highfrequency rolloff due to Qfactor, frequencies near resonance will be attenuated. For that reason a good rule of thumb to follow is making sure the first null should occur at the 7^{th} harmonic, or higher, of the Nyquist frequency to maintain the integrity of the 5^{th} harmonic frequency component that makes up the risetime of a signal.
With this in mind, for a given baudrate (Baud) in GBd/s, the maximum stub length (l_{max}), in inches can be estimated by:
Equation 3
For NRZ signaling, the baudrate is equal to the bit rate. But for pulseamplitude modulation (PAM4) signaling, which has 2 symbols per bit time, the baudrate is ½ of that. Thus a 56 GB/s PAM4 signal has a baudrate of 28 GBd/s, and the Nyquist frequency is 14 GHz, which happens to be the same as 28 GB/s NRZ signalling.
Figure 4 presents a chart of maximum stub length vs baudrate based on Equation 3, using a Dk_{eff} = 6.16 (blue) vs 3.65 (red). It shows us the higher the baudrate, the more the stub length becomes an issue, especially past 10 GBd/s. We also get a feel for the sensitivity of stub length to Dk_{eff }. Even though there is ~ 70% difference in Dk_{eff}, there is only ~ 30% delta in stub lengths for the same baudrate. This means that even if we use the bulk Dk published in data sheets, we are probably not dead in the water.
If the respective stub length is greater than this, it does not mean there is a show stopper. Depending on how much longer means the eye opening at the receiver will be degraded and we lose margin. We see this by the example in Figure 1. Even though the stub lengths in the channel were almost double the value at 10 GBd/s from the chart, there is still plenty of eye opening.
Figure 4 Chart showing estimated maximum stub length vs baudrate with Dk_{eff} of 6.16 (red) vs 3.65 (blue) based on Equation 3
To further explore design space and test out the rule of thumb, a generic circuit model was built using Keysight ADS with the ability to vary the via stub lengths
Referring to the chart, at 28 GBd/s, the maximum stub length should be 12 mils, assuming a Dk_{eff} of 6.16. Figure 5 shows simulation results for NRZ signalling. As can be seen, there was a difference of only 17 mV in eye height (1.5%), and no extra jitter for 12 mil stubs compared to 5 mil stubs.
Figure 5 Eye diagrams comparison with BER at 10E12 for stub lengths of 5 mils vs 12 mils. Modeled and simulated with Keysight ADS.
But if we use the exact same channel model, and use the generic PAM4 IBIS AMI model from Keysight Technologies, we can see the results plotted in Figure 6. On the left are the eye openings with 5 mil stubs and the right with 12 mil stubs. In this case, there was an average reduction of ~7 mV (6%) in eye heights, and 0.24 ps (2%) in eye widths at BER 10E12 across all three eyes.
Figure 6 PAM4, 28 GBd/s (56 GB/s) eye height and width comparison at BER of 10E12 for 5 mil vs 12 mil stub lengths. Modeled and simulated with Keysight ADS.
Because PAM4 signalling has three smaller eyes, that are onethird the size of an NRZ eye for the same amplitude, it is more sensitive to channel impairments. From the above examples, we can see NRZ had only 1.5% reduction in eye height compared to 6% for PAM4. Similarly there was no increase in jitter for NRZ compared to 2% increase for PAM4 when stub lengths changed from 5 mils to 12 mils.
What this says is maintaining a BW to 5 times Nyquist rule of thumb, when estimating via stub lengths, is quite conservative for NRZ signalling. There is almost the same BW as the channel with 5 mil stub, which was the original objective. But because PAM4 is more sensitive to impairments, it shows there is less margin.
In summary then, rules of thumb and related equations are a good way to reinforce your intuitions or to give you an answer sooner rather than later. They help you know what to expect before you take any measurements or perform any simulations. But they should never be used to sign off on any highspeed design.
Because every system will have different impairments affecting BER, the only way to know how much margin you have is by modeling the via with a 3D EM field solver, based on the actual stackup and simulating the entire channel complete with crosstalk, if margins are tight. This is even more critical for data rates above 10 GBd/s.
So to answer the original question, “are all via stubs bad”? Well, the answer is it still depends. For NRZ signalling, there is more leeway than for PAM4. But you now have a practical way to quickly quantify the answer if you know the stub length, baudrate and delay through the via.
Obsessions with Conductor Surface Roughness – What’s the Dk Because of it?
You know you have an obsession when you are flying 6 miles over Colorado; look out your window at the beautiful scenery; and all you can think about is how the rocky mountain topology reminds you of conductor surface roughness! Well call me obsessed because that’s exactly what I thought on my way to DesignCon 2017 in Santa Clara, CA.
For those of you who know me, you know that I have been researching practical methods to model conductor surface roughness, and its effect on insertion loss (IL). I have presented several papers on the subject over the last couple of years. It’s one of my pet projects. This year, at DesignCon, I presented a paper titled, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness” .
Everyone involved in the design and manufacture of printed circuit boards (PCBs) knows one of the most important properties of the dielectric material is the relative permittivity (ε_{r}), commonly referred to as dielectric constant (D_{k}). But in reality, D_{k} is not constant at all. It varies over frequency as you will see later.
We often assume the value reported in manufacturers’ data sheets is the intrinsic property of the material. But in actual fact, it is the effective dielectric constant (D_{keff}) generated by a specific test method. When you compare simulation against measurements, you will often see a discrepancy in Dkeff and IL, due to increased phase delay caused by surface roughness. This has always bothered me. For a long time I was always looking for ways to come up with Dkeff from data sheet numbers alone. Thus the obsession and motivation for my recent research work.
Since phase delay, also known as time delay (TD), is proportional to Dkeff of the material, my theory was that the surface roughness profile decreases the effective separation between parallel plates, thereby increasing the electric field (efield) strength, resulting in additional capacitance, which accounts for an increase in effective D_{k} and TD.
The main focus of my paper was to prove the theory and to show a practical method to model Dkeff and TD due to surface roughness. By referencing Gauss’s Law for charged parallel plates, I confirmed mathematically, and through simulation, how the dielectric thickness and permittivity are interrelated to efield and capacitance. I also revealed how the 10point mean (R_{z}) roughness parameter can be applied to finally estimate effective Dkeff due to roughness. Finally I tested the method via case studies.
In his book, “Transmission Line Design Handbook”, Wadell defines D_{keff} as the ratio of the actual structure’s capacitance to the capacitance when the dielectric is replaced by air.
D_{keff} is highly dependent on the test apparatus and conditions of how it is measured. There are several methods used in the industry. One method that is commonly used by many laminate suppliers is called the clamped stripline resonator test method. It is described by IPCTM650, section 2.5.5.5, Rev C.
In short, this method rapidly tests dielectric material for permittivity and loss tangent, over an Xband frequency range of 812.4 GHz, in a production environment. It does not guarantee the values are accurate for design applications.
Here’s why:
The measurements are made under stripline conditions, using a carefully designed resonant element pattern card, made out of the same dielectric material to be tested. The card is sandwiched between two sheets of unclad dielectric material under test. The whole structure is then clamped between two large plates, lined with copper foils that are grounded.
Since the resonant element pattern card and material under test are not physically bonded together, there are small air gaps between the various layers affecting measured results. These air gaps are caused in part by:
 Removing the copper from the material under test, leaving the bare substrate, complete with the micro void imprint of the copper roughness.
 The air gap between resonant element pattern card and material under test, due to the copper thickness of the etch pattern.
 The roughness profile of the copper, on the resonant element pattern card and fixture’s grounded foil reference planes, are different than would be in practice, unless the same foil type is used.
If D_{keff} and R_{z} roughness parameters from the manufacturers’ data sheets are known, then the effective D_{k} due to roughness (D_{keff}_{_rough}) of the fabricated core laminate can now be easily estimated by:
Where: H_{smooth} is the thickness of dielectric from data sheet; R_{z} is 10point mean roughness from data sheet; and D_{keff} is the D_{k} from data sheet.
With reference to Figure 1, using D_{keff} with rough copper model, as shown on the left, is equivalent to using D_{keff}_{_rough}, with smooth copper model, as shown on the right. Therefore all you need to do is use D_{keff}_{_rough} for impedance calculations, and any other numerical simulations based on surface roughness, instead of D_{k} published in data sheets.
It is as simple as that.
Figure 1 Effective D_{k }due to roughness model. Using D_{keff} with rough copper model (left) is equivalent to using D_{keff}_{_rough }with smooth copper model (right).
For example, one case study I presented used measurements from a CMP28 modeling platform from Wild River Technology. The PCB was fabricated with FR408HR material and reverse treated foil (RTF). Keysight EEsof EDA ADS software was used for modeling and simulation. The results are shown in Figure 2.
The left graph shows results when data sheet values for core and prepreg were used. D_{keff} measured (red) was 3.761, compared to simulated D_{keff} (blue) of 3.626, at 10 GHz. This gave a delta of ~ 4%. But when the D_{keff_rough} was used for core and prepreg the delta was within 1%.
Figure 2 Measured vs simulated D_{keff} using FR408HR data sheet values for core and prepreg (left) and using D_{keff_rough} (right). Modeled and simulated with Keysight EEsof EDA ADS software.
The paper shows in more detail how Equation 1 was derived, based on Gauss’ Law. In addition, I show how IL and phase delay is also improved when D_{keff_rough} is used instead of data sheet values. You can download the paper titled, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”, and other papers on modeling conductor loss due to roughness from my web site.
Practical Conductor Roughness Modeling with Cannonballs
In the GB/s regime, accurate modeling of conductor losses is a precursor to successful highspeed serial link designs. Failure to model roughness effects can ruin you day. For example, Figure 1 shows the simulated total loss of a 40 inch printed circuit board (PCB) trace without roughness compared to measured data. Total loss is the sum of dielectric and conductor losses. With just 3dB delta in insertion loss between simulated and measured data at 12.5 GHz, there is half the eye height opening with rough copper at 25GB/s.
So what do cannon balls have to do with modeling copper roughness anyway? Well, other than sharing the principle of close packing of equal spheres, and having a cool name, not very much.
According to Wikipedia, closepacking of equal spheres is defined as “a dense arrangement of congruent spheres in an infinite, regular arrangement (or lattice)” [8]. The cubic closepacked and hexagonal closepacked are examples of two regular lattices. The cannonball stack is an example of a cubic closepacking of equal spheres, and is the basis of modeling the surface roughness of a conductor in this design note.
Figure 1 Comparisons of measured insertion loss of a 40 inch trace vs simulation. Eye diagrams show that with 3dB delta in insertion loss at 12.5GHz there is half the eye opening at 25GB/s. Modeled and simulated with Keysight EEsof EDA ADS software [14].
Background
In printed circuit (PCB) construction there is no such thing as a perfectly smooth conductor surface. There is always some degree of roughness that promotes adhesion to the dielectric material. Unfortunately this roughness also contributes to additional conductor loss.
Electrodeposited (ED) copper is widely used in the PCB industry. A finished sheet of ED copper foil has a matte side and drum side. The drum side is always smoother than the matte side.
The matte side is usually attached to the core laminate. For high frequency boards, sometimes the drum side of the foil is laminated to the core. In this case it is referred to as reversed treated (RT) foil.
Various foil manufacturers offer ED copper foils with varying degrees of roughness. Each supplier tends to market their product with their own brand name. Presently, there seems to be three distinct classes of copper foil roughness:
· Standard
· Verylow profile (VLP)
· Ultralow profile (ULP) or profile free (PF)
Some other common names referring to ULP class are HVLP or eVLP.
Profilometers are often used to quantify the roughness tooth profile of electrodeposited copper. Tooth profiles are typically reported in terms of 10point mean roughness (R_{z }) for both sides, but sometimes the drum side reports average roughness (R_{a }) in manufacturers’ data sheets. Some manufacturers also report RMS roughness (R_{q }).
Modeling Roughness
Several modeling methods were developed over the years to determine a roughness correction factor (K_{SR }). When multiplicatively applied to the smooth conductor attenuation (α_{smooth }), the attenuation due to roughness (α_{rough }) can be determined by:
Equation 1
The most popular method, for years, has been the Hammerstad and Jensen (H&J) model, based on work done in 1949 by S. P. Morgan. The H&J roughness correction factor (K_{HJ }), at a particular frequency, is solely based on a mathematical fit to S. P. Morgan’s power loss data and is determined by [2]:
Equation 2
Where:
K_{HJ} = H&J roughness correction factor;
∆ = RMS tooth height in meters;
δ = skin depth in meters.
Alternating current (AC) causes conductor loss to increase in proportion to the square root of frequency. This is due to the redistribution of current towards the outer edges caused by skineffect. The resulting skindepth (δ ) is the effective thickness where the current flows around the perimeter and is a function of frequency.
Skindepth at a particular frequency is determined by:
Equation 3
Where:
δ = skindepth in meters;
f = sinewave frequency in Hz;
μ_{0}= permeability of free space =1.256E6 Wb/Am;
σ = conductivity in S/m. For annealed copper σ = 5.80E7 S/m.
The model has correlated well for microstrip geometries up to about 15 GHz, for surface roughness of less than 2 RMS. However, it proved less accurate for frequencies above about 5GHz for very rough copper [3] .
In recent years, the Huray model [4] has gained popularity due to the continually increasing data rate’s need for better modeling accuracy. It takes a real world physics approach to explain losses due to surface roughness. The model is based on a nonuniform distribution of spherical shapes resembling “snowballs” and stacked together forming a pyramidal geometry, as shown by the scanning electron microscope (SEM) photo in Figure 2.
Figure 2 SEM photograph of electrodeposited copper nodules on a matte surface resembling “snowballs” on top of heat treated base foil. Photo credit OakMitsui.
By applying electromagnetic wave analysis, the superposition of the sphere losses can be used to calculate the total loss of the structure. Since the losses are proportional to the surface area of the roughness profile, an accurate estimation of a roughness correction factor (KSRH) can be analytically solved by [1]:
Equation 4
Where:
K_{SRH} (f ) = roughness correction factor, as a function of frequency, due to surface roughness based on the Huray model;
A_{flat}= relative area of the matte base compared to a flat surface;
a_{i} = radius of the copper sphere (snowball) of the i^{th} size, in meters;
Ni = number of copper spheres of the i^{th} size per unit flat area in sq. meters;
δ (f ) = skindepth, as a function of frequency, in meters.
Cannonball Model
Using the concept of cubic closepacking of equal spheres, the radius of the spheres (a_{i }) and tile area (A_{flat }) parameters for the Huray model can now be determined solely by the roughness parameters published in manufacturers’ data sheets.
Why is this important? Well, as my friend Eric Bogatin often says, “Sometimes an OK answer NOW! is more important than a good answer late”. For example, often during the architectural phase of a backplane design, you are going through some whatif scenarios to decide on a final physical configuration. Having a method to accurately predict loss from data sheets alone rather than go through a design feedback method, described in [7] can save an enormous amount of time and money.
Another reason is that it gives you a sense of intuition on what to expect with measurements to help determine root cause of differences; or sanitize simulation results from commercial modeling tools. If you are like me, I always like to have alternate ways to verify that I have used the tool properly.
Recalling that losses are proportional to the surface area of the roughness profile, the Cannonball model can be used to optimally represent the surface roughness. As illustrated in Figure 3, there are three rows of spheres stacked on a square tile base. Nine spheres are on the first row, four spheres in the middle row, and one sphere on top.
Figure 3 Cannonball model showing a stack of 14 uniform size spheres (left). Top and front views (right) shows the area (A_{flat}) of base, height (H_{RMS}) and radius of sphere (r).
Because the Cannonball model assumes the ratio of A_{matte}/A_{flat} = 1, and there are 14 spheres, Equation 4 can be simplified to:
Equation 5
Where:
K_{SR} (f ) = roughness correction factor, as a function of frequency, due to surface roughness based on the Cannonball model;
r = sphere radius in meters; δ (f ) = skindepth, as a function of frequency in meters;
A_{flat} = area of square tile base surrounding the 9 base spheres in sq. meters.
In my white paper [16] the radius of a single sphere is:
And the area of the square flat base is:
You can approximate the RMS heights of the drum and matte sides by Equation 6 and Equation 7 below:
Equation 6
Where: R_{z_drum} is the 10point mean roughness in meters. If the data sheet reports average roughness, then R_{a_drum} is used instead.
Equation 7
Where: R_{z_matte} is the 10point mean roughness in meters.
Practical Example
To test the accuracy of the model, board parameters from a PCBDesign007 February 2014 article, by Yuriy Shlepnev [5] was used. Measured data was obtained from Simbeor software design examples courtesy of Simberian Inc. [9]. The extracted deembedded generalized modal Sparameter (GMS) data was computed from 2 inch and 8 inch singleended stripline traces. They were originally measured from the CMP28 40 GHz HighSpeed Channel Modeling Platform from Wild River Technology [14].
The CMP28 Channel Modeling Platform, (Figure 4 left credit Wild River Technology) is a powerful tool for development of highspeed systems up to 40 GHz, and is an excellent platform for model development and analysis. It contains a total of 27 microstrip and stripline interconnect structures. All are equipped with 2.92mm connectors to facilitate accurate measurements with a vector network analyzer (VNA).
The PCB was fabricated with Isola FR408HR material and reverse treated (RT) 1oz. foil. The dielectric constant (Dk) and dissipation factor (Df), at 10GHz for FR408HR 3313 material, was obtained from Isola’s isoStack® webbased online design tool [10]. This tool is a free, but you need to register to use it. An example is shown in Figure 5.
Typical traces usually have a trapezoidal crosssection after etching due to etch factor. Since the tool does not handle trapezoidal crosssections in the impedance calculation, an equivalent rectangular trace width was determined based on a 2:1 etchfactor (60^{ }deg taper). The as designed nominal trace width of 11 mils, and a 1oz trace thickness of 1.25 mils per isoStack® was used in the analysis.
Figure 5 Example of Isola’s isoStack® online software used to determine dielectric thicknesses, Dk, Df and characteristic impedance for the CMP28 board.
The default foil used on FR408HR core laminates is MLS, Grade 3, controlled elongation RT foil. The roughness parameters were easily obtained from Oakmitsui [11]. Reviewing the data sheet, 1 oz. copper roughness parameters R_{z} for drum and matte sides are 120μin (3.175 μm) and 225μin (5.715μm) respectively. Because this is RT foil, the drum side is the treated side and bonded to the core laminate.
An oxide or microetch treatment is usually applied to the copper surfaces prior to final lamination. This provides enhanced adhesion to the prepreg material. COBRA BOND® [12] or MultiBond MP [13] are two examples of oxide alternative microetch treatments commonly used in the industry. Typically 50 μin (1.27μm) of copper is removed when the treatment is completed. But depending on the board shop’s process control, this can be 70100 μin (1.782.54μm) or higher.
The etch treatment creates a surface full of microvoids which follows the underlying rough profile and allows the resin to squish in and fill the voids providing a good anchor. Because some of the copper is removed during the microetch treatment, we need to reduce the published roughness parameter of the matte side by nominal 50 μin (1.27 μm) for a new thickness of 175μin (4.443μm).
Figure 6 shows SEM photos of typical surfaces for MLS RT foil courtesy of Oakmitsui. The left and center photos are the treated drum side and untreated matte side respectively. The right photo is a 5000x SEM photo of the matte side showing microvoids after etch treatment.
Figure 6 Example SEM photos of MLS RT foil courtesy of Oakmitsui. Left is the treated drum side and center is untreated matte side. SEM photo on the right is the matte side after etch treatment.
The data sheet and design parameters are summarized in Table 1. Respective Dk, Df, core, prepreg and trace thickness were obtained from the isoStack® software, shown in Figure 5. Roughness parameters were obtained from Oakmitsui data sheet. R_{z} of the matte side after microetch treatment (R_{z} = 4.443μm) was used to determine K_{SR_matte }.
Table 1 CMP28 test board parameters obtained from manufacturers’ data sheets and design objective.
Parameter 
FR408HR 
Dk Core/Prepreg 
3.65/3.59 @10GHz 
Df Core/Prepreg 
0.0094/0.0095 @ 10GHz 
R_{z} Drum side 
3.048 μm 
R_{z} Matte side before Microetch 
5.715 μm 
R_{z }Matte side after Microetch 
4.443 μm 
Trace Thickness, t 
31.730 μm 
Trace Etch Factor 
2:1 (60 deg taper) 
Trace Width, w 
11 mils (279.20 μm) 
Core thickness, H1 
12 mils (304.60 μm) 
Prepreg thickness, H2 
10.6 mils (269.00 μm) 
GMS trace length 
6 in (15.23 cm) 
Keysight EEsof EDA ADS software [14] was used for modeling and simulation analysis. A new controlled impedance line (CIL) designer enhancement, in version 2015.01, makes modeling the transmission line substrate easy. Unlike earlier substrate models, the CIL model allows you to model trapezoidal traces.
Figure 7 is the general schematic used for analysis. There are three transmission line substrates; one for dielectric loss; one for conductor loss and the other for total loss without roughness.
Figure 7 Keysight EEsof EDA ADS generic schematic of controlled impedance line designer used in the modeling and simulation analysis.
Dielectric loss was modeled using the Svensson/Djordjevic wideband Debye model to ensure causality. By setting the conductivity parameter to a value muchmuch greater than the normal conductivity of copper ensures the conductor is lossless for the simulation. Similarly the conductor loss model sets the Df to zero to ensure lossless dielectric.
Total insertion loss (IL) of the PCB trace, as a function of frequency, is the sum of dielectric and rough conductor insertion losses.
Equation 8
To accurately model the effect of roughness, the respective roughness correction factor (K_{SR} ) must be multiplicatively applied to the AC resistance of the drum and matte sides of the traces separately. Unfortunately ADS, and many other commercial simulators, do not allow access to these surfaces to apply the correction properly. The best you can do is to apply the average of (K_{SR_drum }) and (K_{SR_matte }) side to the smooth conductor loss (IL_{smooth }), as described above.
The following are the steps to determine K_{SR_avg} (f ) and total IL with roughness:
1. Determine H_{RMS_drum }and H_{RMS_matte }from Equation 6 and Equation 7.
2. Determine the radius of spheres for drum and matte sides:
3. Determine the area of the square flat base for drum and matte sides:
4. Determine K_{SR_drum} (f ) and K_{SR_matte} (f ) :
5. Determine the average K_{SR_drum} (f ) and K_{SR_matte} (f ):
6. Apply Equation 8 to determine total insertion loss of the PCB trace.
Summary and Results
The results are plotted in Figure 8. The left plot compares the simulated vs measured insertion loss for data sheet values and design parameters. Also plotted is the total smooth insertion loss (crosses) which is the sum of conductor loss (circles) and dielectric loss (squares). Remarkably there is excellent agreement up to about 30GHz by just using algebraic equations and published data sheet values for Dk, Df and roughness.
The plot shown on the right is the simulated (blue) vs measured (red) effective dielectric constant (Dkeff ), and is determined by the equations shown. As can be seen, the measured curve has a slightly higher Dkeff (3.76 vs 3.63 @ 10GHz) than published. According to [6], the small increase in the Dk is due to the anisotropy of the material.
When the measured Dkeff (3.76) was used in the model, for core and prepreg, the IL results shown in Figure 9 (left) are even more remarkable up to 50 GHz!
Figure 8 IL (left) for a 6 inch trace in FR408HR RTF using supplier data sheet values for Dk, Df and R_{z}. Effective Dk is shown right.
Figure 9 IL (left) for a 6 inch trace in FR408HR RTF and effective Dk (right).
Figure 10 compares the Cannonball model against the H&J model. The results show that the H&J is only accurate up to approximately 15 GHz compared to the Cannonball model’s accuracy to 50GHz.
Figure 10 Cannonball Model (left) vs HammerstadJensen model (right).
Conclusions
Using the concept of cubic closepacking of equal spheres to model copper roughness, a practical method to accurately calculate sphere size and tile area was devised for use in the Huray model. By using published roughness parameters and dielectric properties from manufacturers’ data sheets, it has been demonstrated that the need for further SEM analysis or experimental curve fitting, may no longer be required for preliminary design and analysis.
When measurements from CMP28 modeling platform, fabricated with FR408HR and RT foil, was compared to this method, there was excellent correlation up to 50GHz compared to the H&J model accuracy to 15GHz.
The Cannonball model looks promising for a practical alternative to building a test board and extracting fitting parameters from measured results to predict insertion loss due to surface roughness.
For More Information
If you liked this design note and want to learn more, or get more details on this innovative roughness modeling methodology, you can visit my web site, LAMSIM Enterprises.com , and download a copy of the white paper [16], or my award winning DesignCon 2015 paper, [1]. And while you are there, feel free to investigate my other white papers and publications.
If you would like more information on our signal integrity and backplane services, or how we can help you achieve your next highspeed design challenge, email us at: info@lamsimenterprises.com
References
[1] Simonovich, Bert, “Practical Method for Modeling Conductor Surface Roughness Using Close Packing of Equal Spheres”, DesignCon 2015 Proceedings, Santa Clara, CA, 2015, URL: http://lamsimenterprises.com/Copyright2.html
[2] Hammerstad, E.; Jensen, O., “Accurate Models for Microstrip ComputerAided Design,” Microwave symposium Digest, 1980 IEEE MTTS International , vol., no., pp.407,409, 2830 May 1980 doi: 10.1109/MWSYM.1980.1124303 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1124303&isnumber=24840
[3] S. Hall, H. Heck, “Advanced Signal Integrity for HighSpeed Digital Design”, John Wiley & Sons, Inc., Hoboken, NJ, USA., 2009
[4] Huray, P. G. (2009) “The Foundations of Signal Integrity”, John Wiley & Sons, Inc., Hoboken, NJ, USA., 2009
[5] Y. Shlepnev, “PCB and package design up to 50 GHz: Identifying dielectric and conductor roughness models”, The PCB Design Magazine, February 2014, p. 1228. URL: http://iconnect007.uberflip.com/i/258943pcbdfeb2014/12
[6] Y. Shlepnev, “Sink or swim at 28 Gbps”, The PCB Design Magazine, October 2014, p. 1223. URL: http://www.magazines007.com/pdf/PCBDOct2014.pdf
[7] E. Bogatin, D. DeGroot , P. G. Huray, Y. Shlepnev , “Which one is better? Comparing Options to Describe Frequency Dependent Losses”, DesignCon2013 Proceedings, Santa Clara, CA, 2013.
[8] Wikipedia, “Closepacking of equal spheres”. URL: http://en.wikipedia.org/wiki/Closepacking_of_equal_spheres
[9] Simberian Inc., 3030 S Torrey Pines Dr. Las Vegas, NV 89146, USA. URL: http://www.simberian.com/
[10] Isola Group S.a.r.l., 3100 West Ray Road, Suite 301, Chandler, AZ 85226. URL: http://www.isolagroup.com/
[11] Oakmitsui 80 First St, Hoosick Falls, NY, 12090. URL: http://www.oakmitsui.com/pages/company/company.asp
[12] Electrochemicals Inc. COBRA BOND®. URL: http://www.electrochemicals.com/ecframe.html
[13] Macdermid Inc., Multibond. URL: http://electronics.macdermid.com/cms/productsservices/printedcircuitboard/surfacetreatments/innerlayerbonding/index.shtml
[14] Keysight Technologies, EEsof EDA, Advanced Design System, 2015.01 software. URL: http://www.keysight.com/en/pc1297113/advanceddesignsystemads?cc=US&lc=eng
[15] Wild River Technology LLC 8311 SW Charlotte Drive Beaverton, OR 97007. URL: http://wildrivertech.com/home/
[16] Simonovich, Bert, “Practical Method for Modeling Conductor Surface Roughness Using The Cannonball Stack Principle”, White Paper, Issue 1.0, April 8, 2015,
URL: http://lamsimenterprises.com/Copyright.html
The Poor Man’s PCB Via Modeling Methodology
You are a backplane designer and have been assigned to engineer a new highspeed, multigigabit serial link architecture from several line cards to multiple fabric switch cards across a backplane. These links must operate at 6GB/s day one and be 10GB/s (IEEE 802.3KR) ready for product evolution. The schedule is tight, and you need to come up with a backplane architecture to allow the rest of the program to progress on schedule.
You come up with a concept you think will work, but the backplane is thick with over 30 layers. There are some long traces over 30 inches and some short traces of less than 2 inches between card slots. There is strong pressure to reuse the same connector you used in your last design, but your gut tells you its design may not be good enough for this higher speed application.
Finally, you are worried about the size and design of the differential via footprint used for the backplane connectors because you know they can be devastating to the quality of the received signal. You want to maximize the routing channel through the connector field, which requires you to shrink the antipad dimensions, so the tracks will be covered by the reference planes, but you can’t easily quantify the consequences on the via of doing so.
You have done all you can think of, based on experience, to make the vias as transparent as possible without simulating. Removal of nonfunctional pads on the inner layers, and planning to backdrill the connector via stubs will help, but is it enough? You know in the back of your mind the best way to answer these questions, and to help you sleep at night, is to put in the numbers.
So you decide to model and simulate the channel. But to do so, you need accurate models of the vias to plug into your favorite circuit simulator. But how do you get these? You have heard it all before; “for highspeed, the best way to model a via is with a 3D electromagnetic field solver”. Although this might be true, what if you don’t have access to such a tool, because the cost is more than your company wants to spend, or because you don’t have the expertise nor the time to learn how to build a model you can trust to make a timely decision?
On top of that, 3D field solvers typically produce Sparameter behavioral models. Since they represent only one sample of a given construction, it is impossible to perform whatif, worst case, min/max analysis with a single behavioral model. Because of this, many iterations of the model are required; causing further delay in getting your answer.
A circuit model on the other hand, is a schematic representation of the actual device. For any physical structure, there can be more than one circuit model to describe it. All can give the same performance, up to some bandwidth. When run in a circuit simulator, it predicts a measurable performance of the structure. These models can be parameterized so that worst case analysis can be explored quickly.
The problem with a circuit model is that you often need a behavioral model to calibrate it, or need to use analytical equations to estimate the parameters. But, as my friend Eric Bogatin often says, “an OK answer NOW! is better than a great answer late”.
In the past, it was next to impossible to develop a circuit model of a differential via structure without a behavioral model to calibrate it. These behavioral models were developed through empirical formulas, measured data, or through the use of 3D EM field solvers.
Now, there is another way. I have nicknamed it, “The Poor Man’s PCB Via Modeling Methodology”. Here’s how it works.
Anatomy of a Differential Via Structure:
An example of a differential via structure, shown in Figure 1, is representative of vias used to connect surface mounted components or backplane connectors to internal layer traces.
The via barrel is a plated through hole extending the entire length of a PCB stackup. The outside diameter equals the drill diameter. The inside diameter is the finished hole size (FHS) after plating. Pads are used on layers to ensure there is sufficient copper for track attachment after drilling operation. When used in this fashion, they are referred to as functional pads. Antipads are the clearance holes in the plane layers allowing the via barrel to pass through them without shorting.
The via portion is the length of the barrel connecting one signal layer to another. It is often referred to as the through via since it is part of the signal net. The stub portion is the rest of the barrel extending to the outer layer of the PCB. In highspeed designs, a good rule of thumb to remember is that a via stub should be less than 300mils/BR in length; where BR is the bit rate in Gb/s.
Building a Simple Scalable Circuit Model:
On close examination of Figure 2, a differential via structure can be represented by a twinrod transmission line geometry with excess capacitance (shown in red) distributed over its entire length. The smaller the antipad diameter, the greater the excess capacitance. This ultimately results in lower via impedance, causing higher reflections.
In all highspeed serial link designs, it is common practice to remove all nonfunctional pads and to maximize the antipad clearance as much as practically possible. Oval antipads are often used in this regard to further mitigate excess via capacitance.
Figure 3 illustrates the equivalent circuit for a differential via that could be used in a channel topology simulation. Here it is modeled with Keysight ADS software using a coupled line transmission line model for each section. This equivalent circuit model can be scaled for any combination of layer transitions and integrated in any channel simulation scenario.
Since the crosssection of the via is constant throughout its length, the differential impedance of all sections of the via are the same. We only need to know the physical length of each segment and the effective dielectric constant (Dkeff) to get the time delay of each segment.
When driven differentially, the oddmode parameters of each via are of major importance. Since the evenmode parameters have no impact on differential performance, both odd and evenmode parameters are set to the same values in the model.
The challenge then is to calculate the odd mode impedance (Zodd), representing the individual via impedance (Zvia), of a differential via structure and the effective dielectric constant (Dkeff) based on its geometry. Simple equations are used to determine these parameters.
Developing the Equations:
Antipads can vary in size and shape. They can be anything from round, to oval around each via, or even a large oval surrounding both vias as illustrated in Figure 4. Square, or rectangular variations (not shown) are similar.
Referring back to Figure 2, we see the structure of each via looks a lot like two coaxial transmission lines with the inner layer reference planes acting like a shield. Electrostatically this is a good approximation, but because the shield is not continuous, the magnetic fields are not contained like they are in a coaxial structure. Instead they behave more like magnetic fields around a twinrod structure.
So here lies the secret in modeling a differential via. We take the best of both geometries to calculate the oddmode impedance representing Zvia.
For inductance, we will use the oddmode inductance formula from the twinrod transmission line geometry to calculate Lvia :
Referring to Figure 4, we then calculate the oddmode capacitance for Cvia derived from an approximate formula for an elliptic coaxial structure developed by M.A.R. Gunston in his book, “Microwave Transmission Line Impedance Data” . In the original formula, both shield (W’+b) and inner conductor (w+t) are elliptical in shape and are dimensioned as shown. When the antipads are circular, then ln[(W’+b) /(w+t)] reduces to just ln[b/t)]; which is the denominator in the Coax equation. If we use Gunston’s approximation to calculate Cvia, then the equation becomes:
Since conventional FR4 type laminates are fabricated with a weave of glass fiber yarns and resin, they are anisotropic in nature. Because of this, the dielectric constant value depends on the direction of the electric fields. In a multilayer PCB, there are effectively two directions of electric fields.
The one we are most familiar with has the electric fields perpendicular to the surface of the PCB; as is the case of stripline shown here in Figure 5. The dielectric constant, designated as Dkz in this case, is normally the bulk value of the dielectric specified by the laminate manufacturer’s data sheet.
The other case has the electric fields running parallel to the surface of the PCB, as is the case when a signal propagates through a differential via structure. In this situation, the dielectric constant, designated as Dkxy, can be1520% higher than Dkz .
Therefore, assuming a nominal 18% anisotropic factor, Dkxy = 1.18(Dkz)
Now that we have defined Lvia, Cvia and Dkavg, Zvia can be estimated using the following equation:
But we are not finished yet. We still need to determine the effective dielectric constant (Dkeff) in order to accurately model the delay through the via and stub portion. Without the correct value, the quarterwave resonant nulls in the insertion loss plot, due to the stub length, cannot be accurately predicted. The value for Dkeff is determined based on how much the via’s oddmode impedance is decreased due to the distributed capacitive loading of the antipads.
To help us with this task, we start with the twinrod formula. The oddmode impedance (Zodd) is half the differential impedance (Ztwin), and is expressed as:
By substituting Equation 1 for Zodd into the equation above, and solving for Dkeff we eventually come up with the following equation:
Validating the Model:
A simple 26 layer test vehicle was fabricated to compare the accuracy of the differential via circuit model to real vias. It consisted of two differential via pairs separated by 6 inches of 100 Ohm stripline differential pairs. Three sample via structures representing long, medium and short via stubs, as summarized in Figure 6, were measured using an Agilent N5230A VNA.
The differential vias had the following common parameters:
Via drill diameter; D = 28 mils
Center to center pitch; s = 59 mils
Oval antipads= 53 mils x 73 mils
Dk of the laminate = 3.65
Anisotropy in Dkxy = 18%
Zvia = Zstub = 31.7 Ohms (per Equation 1)
Dkeff = 6.8 (per Equation 2)
Agilent ADS software was used to model and facilitate simulation correlation of the measured data as captured in Figure 7. This simple model accounts for the discontinuity of the long through section and the long stub section. The top half is the measured channel using an Sparameter file. The bottom half is a circuit model of the channel. Since the probes were not calibrated out, they are part of the device under test. The balun transformers are used to facilitate the display of the Sparameter and TDR results.
The comparison between the measured and simulated results of the insertion loss and TDR response for the three via stub cases using this simple approximation methodology is summarized in Figure 8. The insertion loss plots, in the frequency domain, are shown on the left, while the TDR plots are shown on the right.
The resonant nulls in the SDD21 plots are due to the stub lengths. As you can see, the longer the stub, the lower the resonant frequency null. If this null happens at the Nyquist frequency of the bit rate, the eye will be totally closed. This is why we backdrill them out after the board has been fabricated.
The simulation correlation is excellent up to about 12 GHz. The TDR plots show excellent impedance matching and delay for all three cases, while the simulated stub resonant frequencies match the measured frequencies very well. As you can see, these simple approximations for Dkeff and Zvia are perfectly adequate in providing a quick and accurate circuit model for differential through hole vias typically used in backplane applications.
Summary:
As illustrated, a simple twinrod model (Figure 2) is used as the basis for a practical differential via circuit modeling methodology. By using Equation 1 and Equation 2, you can quickly determine the oddmode impedance and effective dielectric constant needed for the circuit model.
Of course, you should use this methodology first as a rough starting point to quickly estimate the performance of your differential via design. If your worst case topology simulations show the performance is marginal, then it is worth while to invest the time and money to develop a 3D full wave model to perform a more accurate analysis.
On the other hand, if you find this approximation shows the vias have little impact on the channel performance, it may be of greater value for you to invest your time and money in resolving other critical issues with your design.
Try it the next time you are losing sleep over your design challenges.
For more Information:
If you liked this design note and want to learn more, or get more details on this innovative via modeling methodology, you can visit my web site, LAMSIM Enterprises.com , and download a copy of the white paper I wrote along with Eric Bogatin and Yazi Cao titled, “Method of Modeling Differential Vias” .
While you are there, feel free to investigate my other white papers and publications.
If you would like more information on our signal integrity and backplane services, or how we can help you achieve your next highspeed design challenge, email us at: info@lamsimenterprises.com.
UPDATE: In collaboration with Saturn PCB, I am pleased to announce my differential via equations above have been incorporated in a new impedance calculator available now in Saturn PCB Tool Kit software suite.
Twinrod and Rodoverplane Transmission Line Geometries
In my last Design Note on coaxial transmission geometry, I mentioned it was one of three unique crosssectional geometries that have exact equations for inductance and capacitance. The other two are twinrod and rodoverplane. All three relationships assume the dielectric material is homogeneous and completely fills the space when there are electric fields.
A common application for twinrod geometry is twinlead ribbon cable; once used for RF transmission between antenna and TV sets. With the popularity of cable and satellite TV over the years, twinlead has given way to coaxial cable due to its superior noise rejection and shielding effectiveness.
If we look at Figure1, we can see the electromagnetic field relationship of a twinrod geometry when it is driven differentially. As current propagates along one rod, an equal and opposite current flows in the opposite direction along the other.
The right half of Figure 1 shows the magneticfield loops and direction of rotation around each rod. Only one loop is shown for clarity, but the number of loops is a function of the amount of current and the length of the rods. The counterrotating loops of current forms a virtual return at exactly one half of the space between the two rods. We call this a virtual return because if we were to put a conducting plane in the same position, the electromagnetic fields would look exactly the same.
Figure 1 Twinrod geometry showing electromagnetic field relationship.
In his book, “Signal Integrity Simplified”, Eric Bogatin defines the loop inductance as, “the total number of field line loops around a conductor per amp of current”, and the loop selfinductance as, “the total number of field line loops around a conductor per amp of current in the same loop” . Applying these definitions to the figure, the loop inductance (L) is the inductance between the two rods, and the loop selfinductance (L/2) is the loop self inductance to the virtual return plane; equal to one half the loop inductance.
Likewise, the left half of Figure 1 shows the electric field with a capacitance (C) between the two rods, and twice the capacitance (2C) from each rod to the virtual return plane.
The relationships between capacitance, inductance and impedance of a twinrod geometry are described by the following equations:
Where:
Ctwin = Capacitance between twinrods – F
Ltwin = Loop Inductance between twinrods – H
Zdiff = Differential impedance of twinrods – Ω
Dk = Dielectric constant of material
Len = Length of the rods – inches
r = Radius of the rods – inches
s = Space between the rods – inches
Because the electromagnetic fields create a virtual return plane at exactly one half of the spacing between the rods, each rod behaves like a single rodoverplane geometry as illustrated in Figure 2.
Figure 2 Electromagnetic fields comparison of Twinrod (left) vs. Rodoverplane (right) geometries.
Whenever an AC current carrying conductor is in close proximity to a conducting plane, as is the case for rodoverplane, some of the magneticfield lines penetrate it. When the current changes direction, the associated magneticfield lines also change direction; causing small voltages to be induced in the plane. These voltages create eddy currents, which in turn produce their own magneticfields.
Eddy currentinduced magneticfield line patterns look exactly like magneticfield lines from an imaginary current below the plane; located the same distance as the real current above the plane. This imaginary current is called an image current, and has the same magnitude as the real current; except in the opposite direction [1]. The image current creates associated image magneticfield lines in the opposite direction of the real field lines. As a result, the real magneticfield lines are compressed between the rod and the plane. Since the rodoverplane geometry has only one rod, the loop inductance is the same as the loop selfinductance.
For a twinrod geometry, the odd mode capacitance is the capacitance of each rod to virtual return plane and is equal to twice the capacitance between rods.
Likewise, the odd mode inductance is the inductance of each rod to virtual return plane and equal to one half the inductance between rods.
The odd mode impedance of each rod is half of the differential impedance, and is equivalent to the rodoverplane impedance.
[1] “Signal Integrity Simplified”, Eric Bogatin
Coaxial Transmission Line Geometry
The coaxial (coax) transmission line geometry, described by Figure 1, consists of a center conductor; imbedded within a dielectric material; surrounded by a continuous outer conductor; also known as the shield. All share the same geometric center axis; hence the name coaxial. It is common practice to transmit the signal on the center conductor, while the outer conductor provides the return path for current back to the source. The shield is usually grounded at both ends.
Figure 1 Example of a coaxial transmission line geometry and the electromagnetic
field patterns with respect to the current through the structure.
As the signal propagates along the transmission line, an electromagnetic field is set up between the outer surface of the center conductor and the inner surface of the shield. As illustrated in red, the electric Efield pattern sets the capacitance per unit length, and the magnetic Hfield, in blue, sets the inductance. For the center conductor, the “X” represents current flowing into the page and the “.” (dots) within the shield ring is current flowing out of the page.
Figure 2 describes the magneticfield relationship for a coax geometry. As current propagates along the center conductor, concentric magneticfield lines (blue) are created in the direction as shown following the right hand rule.
Whenever an AC current carrying conductor is in close proximity to a conducting plane, some of the magneticfield lines penetrate it. If this plane totally surrounds the inner conductor, it becomes the outer conductor in a coax geometry, and some of the magneticfield lines penetrate the entire circumference. When the current changes direction, the associated magneticfield lines also change direction, causing small voltages to be induced in the outer conductor. These voltages create eddy currents, which in turn, produce their own magneticfields.
Eddy currentinduced magneticfield line patterns look exactly like magneticfield lines (grey) from imaginary currents surrounding the outer conductor. These imaginary currents are referred to as image currents, and have the same magnitude as the real current; except they are in the opposite direction [1]. For simplicity, there are only eight image currents shown. But in reality, there are many more; forming a continuous loop of imaginary currents on a radius equal to twice the radius of the outer conductor to the center of the circle. The image currents create associated image magneticfield lines in the opposite direction of the real field lines. As a result, the real magneticfield lines are compressed and are entirely contained within the outer conductor.
The outer conductor thus forms a shield preventing external magneticfields from coupling noise onto the main signal and likewise, prevents its own magnetic field from escaping and coupling to other cables or equipment. This is why it is a popular choice for RF applications.
The nice thing about a coaxial transmission line is you can use equations to calculate the exact inductance and capacitance per unit length. There are only two other geometries that can do the same. They are, twinrod and rodoverplane; which I will cover at a later time in separate design notes.
The relationships between capacitance, inductance and impedance can be expressed by the following equations:
Ccoax = Capacitance – F
Lcoax = Inductance – H
Zo = Characteristic Impedance – Ohms
Dk = Effective Dielectric constant
Len = Length of the rods
D1 = Diameter of conductor
D2 = Diameter of shield
The coaxial structure can be flexible or semirigid in construction. Flexible coax is used for cable applications; like distributing cable TV or connecting radio transmitters/receivers with their antennas. To achieve its flexibility, the shield is usually braided and is protected by an outer plastic sheathing. Being flexible, the same cable can be reconfigured for different equipment applications.
Semirigid coax, in comparison, employs a solid tubular outer shield, which yields 100% RF shielding, and enables the dielectric material and center conductor to maintain a constant spacing; even through bends. If you have ever worked on your automobile brakes, semirigid coax resembles the rigid brake lines routed through the chassis to the wheels. Semirigid coax is usually used for microwave applications where optimum impedance control is required. A bending tool is needed to form it to a consistent radius. After initial forming and installation, it is not intended to be flexed or reconfigured.
[1] “Signal Integrity Simplified”, Eric Bogatin
PCB Vias – An Overview
Vias make electrical connections between layers on a printed circuit board. They can carry signals or power between layers. For backplane designs, the most common form of vias use plated through hole (PTH) technology. They connect the pins of connectors to inner signal layers. A PTH via is formed by drilling a hole through the layers to be connected and then copper plating it.
High Density Interconnects (HDI) is another via technology used to form very small vias where drilling holes, using a conventional drill bit, is impractical. Also known as microvias, this technology creates the hole with a laser before plating.
Via Aspect Ratio
Via aspect ratio is defined as the ratio of the circuit board thickness to the smallest unplated drilled hole diameter. It is an important metric you need to be aware of when specifying the minimum via hole size for your design, and designing your stackup. For example, an unplated via with a drill diameter of 0.020 inches and a board thickness of 0.200, would have an aspect ratio of 10:1. The smaller the aspect ratio, the more consistent the plating is throughout the length of the via. It is desirable to have 2 mil plating thickness for the via walls. Large aspect ratio vias tend to have more plating at each end compared to the middle. This increases the chance of cracked via barrels due to zaxis expansion while soldering.
An aspect ratio of 6:1 pretty much ensures your board can be fabricated anywhere. Most highend board shops have the capability of fabricating boards with 10:1 aspect ratio; for drill diameters of less than 0.020 inches. Practically, the smallest drill diameter used for a through holed via is 0.013 inches. At 10:1, the maximum board thickness would be 0.130 inches.
For drill diameters larger than 0.020 inches, the max aspect ratio can be anywhere from 15:1 to over 20:1; depending on the board shop. Since backplane via hole size is driven by the compliant pins of the connector, it is best to work with your board shop to determine the maximum board thickness they can fabricate with the minimum finished hole size (FHS) specified in the design.
Via Configurations
The following lists the various via configurations you might expect to find on any multilayer PCB design:

Stub Via

Through Via
 Blind or Microvia

Buried Via

Backdrilled Via
Stub Via
The Stub Via is the most common via configuration found in PCBs today. As illustrated, there are two variations; Stub Via A and Stub Via B.
For the Stub Via A example, it shows the through portion starting from the top layer and ending at some inner layer. The stub portion is the remaining portion continuing from the inner layer junction to the bottom layer.
The Stub Via B example shows the through portion originating from one internal signal layer and terminating on another internal signal layer. In this scenario, there are two stubs. The first stub is from the first internal layer junction to the top layer; the second stub is from the second internal layer junction to the bottom layer.
Through Via
Through vias are the oldest and simplest via configurations originally used in 24 layer PCB designs. Since the signals originate and terminate from the outer layers of the PCB, there are no stubs. In multilayer PCB applications, they are an inexpensive way to eliminate the resonance effects caused by stubs where other mitigation techniques are not practical or are too expensive.
Blind/Buried Via
Blind and buried vias are just like any other via, except they do not go all the way through the PCB. A Blind Via connects one or more internal layers to only one external layer. Controlleddepth drilling is used to form the holes prior to plating.
A buried via, on the other hand, is a plated hole which is completely buried within the board. It connects one or more internal layers and does not connect to an external layer. Using buried via technology is costly because the inner layers being interconnected need to be fully fabricated and plated before final lamination of the entire PCB.
A microvia is a form of blind via. Because the holes are so small (0.006 inches or less), they are formed using lasers, and cannot penetrate more than one or two layers at a time. They are most commonly used in highdensity PCB designs like cell phones, or in FPGA and custom ASIC chip packaging.
Backdrilled Via
High speed pointpoint serial link based backplanes are often thick structures; due to the system architecture and cardcard interconnect requirements. Backdrilling the via stub is common practice on thick PCBs to minimize stub length for bitrates greater than 3Gb/s.
Backdrilling is a process to remove the stub portion of a PTH via. It is a postfabrication drilling process where the backdrilled hole is of larger diameter than the original PTH. This technology is often used instead of blindvia technology to remove the stubs of connector vias in very thick highspeed backplane designs. State of the art board fabrication shops are able to backdrill to within 8 mils of the signal layer to keep, so there will always be a small stub portion attached to the via.
Backdrilling is not without limitations. Smaller vias and tighter pitch driven by large pin count BGA packages makes backdrilling impractical in these applications; due to drill bit size and tolerance issues. Fortunately, smaller via diameters limit the maximum PCB thickness due to aspect ratio; thereby limiting the length of the stub to the board thickness. Careful planning the highspeed layers within the stackup is one way to control stub length.
We worry about stubs in highspeed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot of the channel. If one of these frequency nulls happen to line up at or near the Nyquist frequency of the bit rate, the received eye will be devastated resulting in a high biterrorrate; even link failure. A shorter stub length means these resonances will be pushed out further in frequency; ideally past the 5th harmonic of the Nyquist frequency as a rule of thumb.
Rules of thumb, in general, are no substitute for actual modeling and simulation. You should never depend on them to signoff the final design; but you can use them to gain some intuition before hand. With that in mind, you can estimate the maximum stub length in inches using the following equation:
Where:
L _{Stub_max }= maximum stub length in inches.
Dkeff = effective dielectric constant of the material surrounding the via hole structure.
BR = Bit rate in GB/s.
For example, the maximum stub length at 5GB/s should be less than 0.120 inches in FR4 material with a Dkeff of 4.0 to ensure the first resonant frequency null is greater than 5 times the Nyquist frequency of the bit rate. If the stub length is greater than this, it does not mean the design will not work at 5GB/s. Depending on just how much longer it is means there will be less than optimum eye opening at the receiver.
If you know the length of the stub, you can predict the fundamental resonant frequency, using the following equation:
Where:
Stub_len = stub length in inches.
f_{o} = fundamental resonant frequency in GHz
So, using the same Dkeff of 4.0, and stub length of 0.120 inches, we calculated in the above example, the first resonant frequency null would occur at approximately 12.3 GHz. If we assume this is the 5th harmonic, then the Nyquist frequency is approximately 2.5GHz and the bit rate is 5Gb/s; which is where we started.