Bert Simonovich's Design Notes

Innovative Signal Integrity & Backplane Solutions

Archive for the ‘Useful Equations’ Category

Via Stubs Demystified

leave a comment »

imageWe worry about via stubs in high-speed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot (IL) of the channel. But are all via stubs bad? Well, as with most answers relating to signal integrity, “It depends.”

If one of these frequency nulls happen to line up at or near the Nyquist frequency of the bit- rate (i.e. 1/2 of the bit-rate), the received eye will be devastated, resulting in a high bit-error-ratio (BER), or even link failure.

Figure 1 shows simulation results of two backplane channels. On the left are measured SDD21 insertion loss and eye diagram of a 10 GB/s, non-return-to-zero (NRZ) signal, with short through vias and long stubs ~ 270 mils. On the right, shows measured SDD21 IL and eye diagram of a channel with long through vias and shorter stubs ~ 65 mils

Because the ¼ -wave resonant null occurs at a frequency ~ 4. 4 GHz, this is near the Nyquist frequency for 10 GB/s. As can be seen, the eye is totally closed for the long stub case. But when the shorter stub case is simulated, the eye is open with plenty of margin.

So how does a via stub cause ¼ -wave resonance? This question can be explained with the aid of Figure 2. Starting on the left, we see a via with two sections. The through (thru) part is the top portion connecting a device pin to an inner layer trace of a printed circuit board (PCB). The stub portion is the lower portion and is an open circuit.

On the right a sinusoidal signal is injected into the pin at the top of the via and travels along the thru portion until it reaches the junction of the internal trace and stub. At that point, the signal splits. Some of it travels along the trace, and the rest continues down the stub. Once it reaches the bottom, it reflects back up. When it reaches the trace junction, it splits again with a portion traveling along the trace and the rest back to the source.

If f  is the frequency of a sine wave, and the time delay (TD) through the stub portion equals a ¼ -wavelength, then when it reflects at the bottom and reaches the junction again, it will be delayed by ½ a cycle and cancels most of the original signal.


Figure 2 Illustration of a ¼ -wave resonance of a stub. If f = frequency where TD = ¼ wavelength, then when 2TD = ½ cycle minimum signal received.

Resonance nulls occurs at the fundamental frequency ( fo) and at every odd harmonic. If you know the length of the stub (in inches) and the effective dielectric constant (Dkeff), surrounding the via hole structure, the resonant frequency can be predicted by:

Equation 1


Where: fo is the ¼ -wave resonant frequency (GHz); c is the speed of light (~11.8 in/ns); Stub_length is inches.

You will find that Dkeff is not the same as the bulk Dk published in laminate manufacturers’ data sheets. It is typically higher. A higher Dkeff increases phase delay through the via resulting in a lower resonant frequency.

One reason is excess capacitance from the via pads as well as the via barrel’s proximity to the clearance hole openings (also known as anti-pads) in plane layers. The other is because of the anisotropic nature of the laminate material.

For the example in Figure 1, the ¼ -wave resonant frequency of the long via stub is ~ 4.4 GHz. With a stub length of ~ 270 mils, this gives a Dkeff of 6.16, which is considerably higher than the published bulk Dk of 3.65. When you model a via in an electro-magnetic (EM) 3D field solver, it automatically accounts for the excess capacitance, but you will still need to compensate for the anisotropic nature of the dielectric.

A material is anisotropic when there are different values for parallel (x-y) vs perpendicular (z) measured values for dielectric constant. Dielectric constant and loss tangent, as published in manufacturers’ data sheets, report perpendicular measured values. For FR-4 fiberglass reinforced laminates, anisotropy can range from 15% -25% higher. The bad news is these numbers are not readily available from data sheets.

For differentially driven vias with plane layers evenly distributed throughout the entire stackup, Dkeff can be roughly estimated by:

Equation 2


Where: Dkxy is the dielectric constant adjusted for anisotropy (15%-25% higher); Dkz is the bulk dielectric constant from data sheets; s is via-via spacing; drillØ is drill diameter; H and W are anti-pad shape dimensions as shown in Figure 3 .


Figure 3 Anti-pad parameters for Equation 2.

The effects of via stubs can be mitigated by: using blind or buried vias; back-drilling; or by using thru vias only (i.e. from top layer to bottom layer). Practically, the shortest stub that can be achieved by back-drilling is on the order of 5 to 10 mils.

As a rule of thumb, we usually strive to have an interconnect bandwidth (BW) to be five times the Nyquist frequency of the bit-rate. Since a ¼-wave resonant null behaves somewhat like a notch filter, depending on the high-frequency roll-off due to Q-factor, frequencies near resonance will be attenuated. For that reason a good rule of thumb to follow is making sure the first null should occur at the 7th harmonic, or higher, of the Nyquist frequency to maintain the integrity of the 5th harmonic frequency component that makes up the risetime of a signal.

With this in mind, for a given baud-rate (Baud) in GBd/s, the maximum stub length (lmax), in inches can be estimated by:

Equation 3


For NRZ signaling, the baud-rate is equal to the bit rate. But for pulse-amplitude modulation (PAM-4) signaling, which has 2 symbols per bit time, the baud-rate is ½ of that. Thus a 56 GB/s PAM-4 signal has a baud-rate of 28 GBd/s, and the Nyquist frequency is 14 GHz, which happens to be the same as 28 GB/s NRZ signalling.

Figure 4 presents a chart of maximum stub length vs baud-rate based on Equation 3, using a Dkeff = 6.16 (blue) vs 3.65 (red). It shows us the higher the baud-rate, the more the stub length becomes an issue, especially past 10 GBd/s. We also get a feel for the sensitivity of stub length to Dkeff . Even though there is ~ 70% difference in Dkeff, there is only ~ 30% delta in stub lengths for the same baud-rate. This means that even if we use the bulk Dk published in data sheets, we are probably not dead in the water.

If the respective stub length is greater than this, it does not mean there is a show stopper. Depending on how much longer means the eye opening at the receiver will be degraded and we lose margin. We see this by the example in Figure 1. Even though the stub lengths in the channel were almost double the value at 10 GBd/s from the chart, there is still plenty of eye opening.


Figure 4 Chart showing estimated maximum stub length vs baud-rate with Dkeff of 6.16 (red) vs 3.65 (blue) based on Equation 3

To further explore design space and test out the rule of thumb, a generic circuit model was built using Keysight ADS with the ability to vary the via stub lengths

Referring to the chart, at 28 GBd/s, the maximum stub length should be 12 mils, assuming a Dkeff of 6.16. Figure 5 shows simulation results for NRZ signalling. As can be seen, there was a difference of only 17 mV in eye height (1.5%), and no extra jitter for 12 mil stubs compared to 5 mil stubs.


Figure 5 Eye diagrams comparison with BER at 10E-12 for stub lengths of 5 mils vs 12 mils. Modeled and simulated with Keysight ADS.

But if we use the exact same channel model, and use the generic PAM-4 IBIS AMI model from Keysight Technologies, we can see the results plotted in Figure 6. On the left are the eye openings with 5 mil stubs and the right with 12 mil stubs. In this case, there was an average reduction of ~7 mV (6%) in eye heights, and 0.24 ps (2%) in eye widths at BER 10E-12 across all three eyes.


Figure 6 PAM-4, 28 GBd/s (56 GB/s) eye height and width comparison at BER of 10E-12 for 5 mil vs 12 mil stub lengths. Modeled and simulated with Keysight ADS.

Because PAM-4 signalling has three smaller eyes, that are one-third the size of an NRZ eye for the same amplitude, it is more sensitive to channel impairments. From the above examples, we can see NRZ had only 1.5% reduction in eye height compared to 6% for PAM-4. Similarly there was no increase in jitter for NRZ compared to 2% increase for PAM-4 when stub lengths changed from 5 mils to 12 mils.

What this says is maintaining a BW to 5 times Nyquist rule of thumb, when estimating via stub lengths, is quite conservative for NRZ signalling. There is almost the same BW as the channel with 5 mil stub, which was the original objective. But because PAM-4 is more sensitive to impairments, it shows there is less margin.

In summary then, rules of thumb and related equations are a good way to reinforce your intuitions or to give you an answer sooner rather than later. They help you know what to expect before you take any measurements or perform any simulations. But they should never be used to sign off on any high-speed design.

Because every system will have different impairments affecting BER, the only way to know how much margin you have is by modeling the via with a 3-D EM field solver, based on the actual stackup and simulating the entire channel complete with crosstalk, if margins are tight. This is even more critical for data rates above 10 GBd/s.

So to answer the original question, “are all via stubs bad”? Well, the answer is it still depends. For NRZ signalling, there is more leeway than for PAM-4. But you now have a practical way to quickly quantify the answer if you know the stub length, baud-rate and delay through the via.

Written by Bert Simonovich

March 8, 2017 at 2:35 pm

Obsessions with Conductor Surface Roughness – What’s the Dk Because of it?

leave a comment »

clip_image002You know you have an obsession when you are flying 6 miles over Colorado; look out your window at the beautiful scenery; and all you can think about is how the rocky mountain topology reminds you of conductor surface roughness! Well call me obsessed because that’s exactly what I thought on my way to DesignCon 2017 in Santa Clara, CA.

For those of you who know me, you know that I have been researching practical methods to model conductor surface roughness, and its effect on insertion loss (IL). I have presented several papers on the subject over the last couple of years. It’s one of my pet projects. This year, at DesignCon, I presented a paper titled, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness” .

Everyone involved in the design and manufacture of printed circuit boards (PCBs) knows one of the most important properties of the dielectric material is the relative permittivity (εr), commonly referred to as dielectric constant (Dk). But in reality, Dk is not constant at all. It varies over frequency as you will see later.

We often assume the value reported in manufacturers’ data sheets is the intrinsic property of the material. But in actual fact, it is the effective dielectric constant (Dkeff) generated by a specific test method. When you compare simulation against measurements, you will often see a discrepancy in Dkeff and IL, due to increased phase delay caused by surface roughness. This has always bothered me. For a long time I was always looking for ways to come up with Dkeff from data sheet numbers alone. Thus the obsession and motivation for my recent research work.

Since phase delay, also known as time delay (TD), is proportional to Dkeff of the material, my theory was that the surface roughness profile decreases the effective separation between parallel plates, thereby increasing the electric field (e-field) strength, resulting in additional capacitance, which accounts for an increase in effective Dk and TD.

The main focus of my paper was to prove the theory and to show a practical method to model Dkeff and TD due to surface roughness. By referencing Gauss’s Law for charged parallel plates, I confirmed mathematically, and through simulation, how the dielectric thickness and permittivity are interrelated to e-field and capacitance. I also revealed how the 10-point mean (Rz) roughness parameter can be applied to finally estimate effective Dkeff due to roughness. Finally I tested the method via case studies.

In his book, “Transmission Line Design Handbook”, Wadell defines Dkeff as the ratio of the actual structure’s capacitance to the capacitance when the dielectric is replaced by air.

Dkeff is highly dependent on the test apparatus and conditions of how it is measured. There are several methods used in the industry. One method that is commonly used by many laminate suppliers is called the clamped stripline resonator test method. It is described by IPC-TM-650, section, Rev C.

In short, this method rapidly tests dielectric material for permittivity and loss tangent, over an X-band frequency range of 8-12.4 GHz, in a production environment. It does not guarantee the values are accurate for design applications.

Here’s why:

The measurements are made under stripline conditions, using a carefully designed resonant element pattern card, made out of the same dielectric material to be tested. The card is sandwiched between two sheets of unclad dielectric material under test. The whole structure is then clamped between two large plates, lined with copper foils that are grounded.

Since the resonant element pattern card and material under test are not physically bonded together, there are small air gaps between the various layers affecting measured results. These air gaps are caused in part by:

  • Removing the copper from the material under test, leaving the bare substrate, complete with the micro void imprint of the copper roughness.
  • The air gap between resonant element pattern card and material under test, due to the copper thickness of the etch pattern.
  • The roughness profile of the copper, on the resonant element pattern card and fixture’s grounded foil reference planes, are different than would be in practice, unless the same foil type is used.

If Dkeff and Rz roughness parameters from the manufacturers’ data sheets are known, then the effective Dk due to roughness (Dkeff_rough) of the fabricated core laminate can now be easily estimated by:

Equation 1


Where: Hsmooth is the thickness of dielectric from data sheet; Rz is 10-point mean roughness from data sheet; and Dkeff is the Dk from data sheet.

With reference to Figure 1, using Dkeff with rough copper model, as shown on the left, is equivalent to using Dkeff_rough, with smooth copper model, as shown on the right. Therefore all you need to do is use Dkeff_rough for impedance calculations, and any other numerical simulations based on surface roughness, instead of Dk published in data sheets.

It is as simple as that.


Figure 1 Effective Dk due to roughness model. Using Dkeff with rough copper model (left) is equivalent to using Dkeff_rough with smooth copper model (right).

For example, one case study I presented used measurements from a CMP28 modeling platform from Wild River Technology. The PCB was fabricated with FR408HR material and reverse treated foil (RTF). Keysight EEsof EDA ADS software was used for modeling and simulation. The results are shown in Figure 2.

The left graph shows results when data sheet values for core and prepreg were used. Dkeff measured (red) was 3.761, compared to simulated Dkeff (blue) of 3.626, at 10 GHz. This gave a delta of ~ 4%. But when the Dkeff_rough was used for core and prepreg the delta was within 1%.


Figure 2 Measured vs simulated Dkeff using FR408HR data sheet values for core and prepreg (left) and using Dkeff_rough (right). Modeled and simulated with Keysight EEsof EDA ADS software.

The paper shows in more detail how Equation 1 was derived, based on Gauss’ Law. In addition, I show how IL and phase delay is also improved when Dkeff_rough is used instead of data sheet values. You can download the paper titled, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”, and other papers on modeling conductor loss due to roughness from my web site.

Written by Bert Simonovich

February 21, 2017 at 10:48 am

Practical Conductor Roughness Modeling with Cannonballs

leave a comment »


In the GB/s regime, accurate modeling of conductor losses is a precursor to successful high-speed serial link designs. Failure to model roughness effects can ruin you day. For example, Figure 1 shows the simulated total loss of a 40 inch printed circuit board (PCB) trace without roughness compared to measured data. Total loss is the sum of dielectric and conductor losses. With  just -3dB delta in insertion loss between simulated and measured data at 12.5 GHz, there is half the eye height opening with rough copper at 25GB/s.

So what do cannon balls have to do with modeling copper roughness anyway? Well, other than sharing the principle of close packing of equal spheres, and having a cool name, not very much.

According to Wikipedia, close-packing of equal spheres is defined as “a dense arrangement of congruent spheres in an infinite, regular arrangement (or lattice)[8].  The cubic close-packed and hexagonal close-packed are examples of two regular lattices.  The cannonball stack is an example of a cubic close-packing of equal spheres, and is the basis of modeling the surface roughness of a conductor in this design note.


Figure 1 Comparisons of measured insertion loss of a 40 inch trace vs simulation. Eye diagrams show that with -3dB delta in insertion loss at 12.5GHz there is half the eye opening at 25GB/s. Modeled and simulated with Keysight EEsof EDA ADS software [14].


In printed circuit (PCB) construction there is no such thing as a perfectly smooth conductor surface. There is always some degree of roughness that promotes adhesion to the dielectric material. Unfortunately this roughness also contributes to additional conductor loss.

Electro-deposited (ED) copper is widely used in the PCB industry. A finished sheet of ED copper foil has a matte side and drum side. The drum side is always smoother than the matte side.

The matte side is usually attached to the core laminate. For high frequency boards, sometimes the drum side of the foil is laminated to the core. In this case it is referred to as reversed treated (RT) foil.

Various foil manufacturers offer ED copper foils with varying degrees of roughness. Each supplier tends to market their product with their own brand name. Presently, there seems to be three distinct classes of copper foil roughness:

·         Standard

·         Very-low profile (VLP)

·         Ultra-low profile (ULP) or profile free (PF)

Some other common names referring to ULP class are HVLP or eVLP.

Profilometers are often used to quantify the roughness tooth profile of electro-deposited copper. Tooth profiles are typically reported in terms of 10-point mean roughness (Rz ) for both sides, but sometimes the drum side reports average roughness (Ra ) in manufacturers’ data sheets. Some manufacturers also report RMS roughness (Rq ).

Modeling Roughness

Several modeling methods were developed over the years to determine a roughness correction factor (KSR ). When multiplicatively applied to the smooth conductor attenuation (αsmooth ), the attenuation due to roughness (αrough ) can be determined by:

Equation 1


The most popular method, for years, has been the Hammerstad and Jensen (H&J) model, based on work done in 1949 by S. P. Morgan. The H&J roughness correction factor (KHJ ), at a particular frequency, is solely based on a mathematical fit to S. P. Morgan’s power loss data and is determined by [2]:

Equation 2



KHJ = H&J roughness correction factor;

= RMS tooth height in meters;

δ = skin depth in meters.

Alternating current (AC) causes conductor loss to increase in proportion to the square root of frequency. This is due to the redistribution of current towards the outer edges caused by skin-effect. The resulting skin-depth (δ ) is the effective thickness where the current flows around the perimeter and is a function of frequency.

Skin-depth at a particular frequency is determined by:

Equation 3



δ = skin-depth in meters;

f = sine-wave frequency in Hz;

μ0= permeability of free space =1.256E-6 Wb/A-m;

σ = conductivity in S/m. For annealed copper σ = 5.80E7 S/m.

The model has correlated well for microstrip geometries up to about 15 GHz, for surface roughness of less than 2  RMS. However, it proved less accurate for frequencies above about 5GHz for very rough copper [3] .

In recent years, the Huray model [4] has gained popularity due to the continually increasing data rate’s need for better modeling accuracy. It takes a real world physics approach to explain losses due to surface roughness. The model is based on a non-uniform distribution of spherical shapes resembling “snowballs” and stacked together forming a pyramidal geometry, as shown by the scanning electron microscope (SEM) photo in Figure 2.


Figure 2 SEM photograph of electrodeposited copper nodules on a matte surface resembling “snowballs” on top of heat treated base foil. Photo credit Oak-Mitsui.

By applying electromagnetic wave analysis, the superposition of the sphere losses can be used to calculate the total loss of the structure. Since the losses are proportional to the surface area of the roughness profile, an accurate estimation of a roughness correction factor (KSRH) can be analytically solved by [1]:


Equation 4



KSRH (f ) = roughness correction factor, as a function of frequency, due to surface roughness based on the Huray model;

Aflat= relative area of the matte base compared to a flat surface;

 ai = radius of the copper sphere (snowball) of the ith size, in meters;

 Ni = number of copper spheres of the ith size per unit flat area in sq. meters;

 δ (f ) = skin-depth, as a function of frequency, in meters.

Cannonball Model

Using the concept of cubic close-packing of equal spheres, the radius of the spheres (ai ) and tile area (Aflat ) parameters for the Huray model can now be determined solely by the roughness parameters published in manufacturers’ data sheets.  

Why is this important? Well, as my friend Eric Bogatin often says, “Sometimes an OK answer NOW! is more important than a good answer late”. For example, often during the architectural phase of a backplane design, you are going through some what-if scenarios to decide on a final physical configuration. Having a method to accurately predict loss from data sheets alone rather than go through a design feedback method, described in [7] can save an enormous amount of time and money.

Another reason is that it gives you a sense of intuition on what to expect with measurements to help determine root cause of differences; or sanitize simulation results from commercial modeling tools. If you are like me, I always like to have alternate ways to verify that I have used the tool properly.

Recalling that losses are proportional to the surface area of the roughness profile, the Cannonball model can be used to optimally represent the surface roughness. As illustrated in Figure 3, there are three rows of spheres stacked on a square tile base. Nine spheres are on the first row, four spheres in the middle row, and one sphere on top.


Figure 3 Cannonball model showing a stack of 14 uniform size spheres (left). Top and front views (right) shows the area (Aflat) of base, height (HRMS) and radius of sphere (r).

Because the Cannonball model assumes the ratio of Amatte/Aflat = 1, and there are 14 spheres, Equation 4 can be simplified to:

Equation 5



KSR (f ) = roughness correction factor, as a function of frequency, due to surface roughness based on the Cannonball model;

r = sphere radius in meters; δ (f ) = skin-depth, as a function of frequency in meters;

Aflat = area of square tile base surrounding the 9 base spheres in sq. meters.

In my white paper [16] the radius of a single sphere is:


And the area of the square flat base is:


You can approximate the RMS heights of the drum and matte sides by Equation 6 and Equation 7 below:

Equation 6


Where: Rz_drum is the 10-point mean roughness in meters. If the data sheet reports average roughness, then Ra_drum is used instead.

Equation 7


Where: Rz_matte is the 10-point mean roughness in meters.

Practical Example

To test the accuracy of the model, board parameters from a PCBDesign007 February 2014 article, by Yuriy Shlepnev [5] was used. Measured data was obtained from Simbeor software design examples courtesy of Simberian Inc. [9]. The extracted de-embedded generalized modal S-parameter (GMS) data was computed from 2 inch and 8 inch single-ended stripline traces. They were originally measured from the CMP-28 40 GHz High-Speed Channel Modeling Platform from Wild River Technology [14].

imageThe CMP-28 Channel Modeling Platform, (Figure 4 left -credit Wild River Technology) is a powerful tool for development of high-speed systems up to 40 GHz, and is an excellent platform for model development and analysis. It contains a total of 27 microstrip and stripline interconnect structures. All are equipped with 2.92mm connectors to facilitate accurate measurements with a vector network analyzer (VNA).

The PCB was fabricated with Isola FR408HR material and reverse treated (RT) 1oz. foil. The dielectric constant (Dk) and dissipation factor (Df), at 10GHz for FR408HR 3313 material, was obtained from Isola’s isoStack® web-based online design tool [10]. This tool is a free, but you need to register to use it. An example is shown in Figure 5.

Typical traces usually have a trapezoidal cross-section after etching due to etch factor. Since the tool does not handle trapezoidal cross-sections in the impedance calculation, an equivalent rectangular trace width was determined based on a 2:1 etch-factor (60 deg taper).  The as designed nominal trace width of 11 mils, and a 1oz trace thickness of 1.25 mils per isoStack® was used in the analysis.


Figure 5 Example of Isola’s isoStack® online software used to determine dielectric thicknesses, Dk, Df and characteristic impedance for the CMP-28 board.

The default foil used on FR408HR core laminates is MLS, Grade 3, controlled elongation RT foil. The roughness parameters were easily obtained from Oak-mitsui [11]. Reviewing the data sheet, 1 oz. copper roughness parameters Rz for drum and matte sides are 120μin (3.175 μm) and 225μin (5.715μm) respectively. Because this is RT foil, the drum side is the treated side and bonded to the core laminate.

An oxide or micro-etch treatment is usually applied to the copper surfaces prior to final lamination. This provides enhanced adhesion to the prepreg material. CO-BRA BOND® [12] or MultiBond MP [13] are two examples of oxide alternative micro-etch treatments commonly used in the industry. Typically 50 μin (1.27μm) of copper is removed when the treatment is completed. But depending on the board shop’s process control, this can be 70-100 μin (1.78-2.54μm) or higher.

The etch treatment creates a surface full of micro-voids which follows the underlying rough profile and allows the resin to squish in and fill the voids providing a good anchor. Because some of the copper is removed during the micro-etch treatment, we need to reduce the published roughness parameter of the matte side by nominal 50 μin (1.27 μm) for a new thickness of 175μin (4.443μm).

Figure 6 shows SEM photos of typical surfaces for MLS RT foil courtesy of Oak-mitsui. The left and center photos are the treated drum side and untreated matte side respectively. The right photo is a 5000x SEM photo of the matte side showing micro-voids after etch treatment.


Figure 6 Example SEM photos of MLS RT foil courtesy of Oak-mitsui. Left is the treated drum side and center is untreated matte side. SEM photo on the right is the matte side after etch treatment.

The data sheet and design parameters are summarized in Table 1. Respective Dk, Df, core, prepreg and trace thickness were obtained from the isoStack® software, shown in Figure 5. Roughness parameters were obtained from Oak-mitsui data sheet. Rz of the matte side after micro-etch treatment (Rz = 4.443μm) was used to determine KSR_matte .

Table 1 CMP-28 test board parameters obtained from manufacturers’ data sheets and design objective.



Dk Core/Prepreg

3.65/3.59 @10GHz

Df Core/Prepreg

0.0094/0.0095 @ 10GHz

Rz Drum side

3.048 μm

Rz Matte side before Micro-etch

5.715 μm

Rz Matte side  after Micro-etch

4.443 μm

Trace Thickness, t

31.730 μm

Trace Etch Factor

2:1 (60 deg taper)

Trace Width, w

11 mils (279.20 μm)

Core thickness, H1

12 mils (304.60 μm)

Prepreg thickness, H2

10.6 mils (269.00 μm)

GMS trace length

6 in (15.23 cm)


Keysight EEsof EDA ADS software [14] was used for modeling and simulation analysis. A new controlled impedance line (CIL) designer enhancement, in version 2015.01, makes modeling the transmission line substrate easy. Unlike earlier substrate models, the CIL model allows you to model trapezoidal traces.

Figure 7 is the general schematic used for analysis. There are three transmission line substrates; one for dielectric loss; one for conductor loss and the other for total loss without roughness.


Figure 7 Keysight EEsof EDA ADS generic schematic of controlled impedance line designer used in the modeling and simulation analysis.

Dielectric loss was modeled using the Svensson/Djordjevic wideband Debye model to ensure causality. By setting the conductivity parameter to a value much-much greater than the normal conductivity of copper ensures the conductor is lossless for the simulation. Similarly the conductor loss model sets the Df to zero to ensure lossless dielectric.

Total insertion loss (IL) of the PCB trace, as a function of frequency, is the sum of dielectric and rough conductor insertion losses.

Equation 8


To accurately model the effect of roughness, the respective roughness correction factor (KSR ) must be multiplicatively applied to the AC resistance of the drum and matte sides of the traces separately. Unfortunately ADS, and many other commercial simulators, do not allow access to these surfaces to apply the correction properly. The best you can do is to apply the average of (KSR_drum ) and (KSR_matte ) side to the smooth conductor loss (ILsmooth ), as described above.

The following are the steps to determine KSR_avg (f ) and total IL with roughness:

1. Determine HRMS_drum and HRMS_matte from Equation 6 and Equation 7. 


2. Determine the radius of spheres for drum and matte sides:

3. Determine the area of the square flat base for drum and matte sides:

4. Determine KSR_drum (f ) and KSR_matte (f ) :

5. Determine the average KSR_drum (f ) and KSR_matte (f ):

6. Apply Equation 8 to determine total insertion loss of the PCB trace.


Summary and Results

The results are plotted in Figure 8. The left plot compares the simulated vs measured insertion loss for data sheet values and design parameters.  Also plotted is the total smooth insertion loss (crosses) which is the sum of conductor loss (circles) and dielectric loss (squares). Remarkably there is excellent agreement up to about 30GHz by just using algebraic equations and published data sheet values for Dk, Df and roughness.

The plot shown on the right is the simulated (blue) vs measured (red) effective dielectric constant (Dkeff ), and is determined by the equations shown. As can be seen, the measured curve has a slightly higher Dkeff (3.76 vs 3.63 @ 10GHz) than published. According to [6], the small increase in the Dk is due to the anisotropy of the material.

When the measured Dkeff (3.76) was used in the model, for core and prepreg, the IL results shown in Figure 9 (left) are even more remarkable up to 50 GHz!


Figure 8 IL (left) for a 6 inch trace in FR408HR RTF using supplier data sheet values for Dk, Df and Rz. Effective Dk is shown right.


Figure 9 IL (left) for a 6 inch trace in FR408HR RTF and effective Dk (right).

Figure 10 compares the Cannonball model against the H&J model. The results show that the H&J is only accurate up to approximately 15 GHz compared to the Cannonball model’s accuracy to 50GHz.


Figure 10 Cannonball Model (left) vs Hammerstad-Jensen model (right).


Using the concept of cubic close-packing of equal spheres to model copper roughness, a practical method to accurately calculate sphere size and tile area was devised for use in the Huray model. By using published roughness parameters and dielectric properties from manufacturers’ data sheets,  it has been demonstrated that the need for further SEM analysis or experimental curve fitting, may no longer be required for preliminary design and analysis.

When measurements from CMP-28 modeling platform, fabricated with FR408HR and RT foil, was compared to this method, there was excellent correlation up to 50GHz compared to the H&J model accuracy to 15GHz.

The Cannonball model looks promising for a practical alternative to building a test board and extracting fitting parameters from measured results to predict insertion loss due to surface roughness.

For More Information

If you liked this design note and want to learn more, or get more details on this innovative roughness modeling methodology, you can visit my web site, LAMSIM , and download a copy of the white paper [16], or my award winning DesignCon 2015 paper, [1]. And while you are there, feel free to investigate my other white papers and publications.

If you would like more information on our signal integrity and backplane services, or how we can help you achieve your next high-speed design challenge, email us at:


[1]   Simonovich, Bert, “Practical Method for Modeling Conductor Surface Roughness Using Close Packing of Equal Spheres”, DesignCon 2015 Proceedings, Santa Clara, CA, 2015, URL:

[2]   Hammerstad, E.; Jensen, O., “Accurate Models for Microstrip Computer-Aided Design,” Microwave symposium Digest, 1980 IEEE MTT-S International , vol., no., pp.407,409, 28-30 May 1980 doi: 10.1109/MWSYM.1980.1124303 URL:

[3]   S. Hall, H. Heck, “Advanced Signal Integrity for High-Speed Digital Design”, John Wiley & Sons, Inc., Hoboken, NJ, USA., 2009

[4]   Huray, P. G. (2009) “The Foundations of Signal Integrity”, John Wiley & Sons, Inc., Hoboken, NJ, USA., 2009

[5]   Y. Shlepnev, “PCB and package design up to 50 GHz: Identifying dielectric and conductor roughness models”, The PCB Design Magazine, February 2014, p. 12-28. URL:

[6]   Y. Shlepnev, “Sink or swim at 28 Gbps”, The PCB Design Magazine, October 2014, p. 12-23. URL:

[7]    E. Bogatin, D. DeGroot , P. G. Huray, Y. Shlepnev , “Which one is better? Comparing Options to Describe Frequency Dependent Losses”, DesignCon2013 Proceedings, Santa Clara, CA, 2013.

[8]   Wikipedia, “Close-packing of equal spheres”. URL:

[9]   Simberian Inc., 3030 S Torrey Pines Dr. Las Vegas, NV 89146, USA. URL:

[10]    Isola Group S.a.r.l., 3100 West Ray Road, Suite 301, Chandler, AZ 85226. URL:

[11]    Oak-mitsui 80 First St, Hoosick Falls, NY, 12090. URL:

[12]    Electrochemicals Inc. CO-BRA BOND®. URL:

[13]    Macdermid Inc., Multibond. URL:

[14]    Keysight Technologies, EEsof EDA, Advanced Design System, 2015.01 software. URL:

[15]    Wild River Technology LLC 8311 SW Charlotte Drive Beaverton, OR 97007. URL:

[16]    Simonovich, Bert, “Practical Method for Modeling Conductor Surface Roughness Using The Cannonball Stack Principle”, White Paper, Issue 1.0, April 8, 2015,

The Poor Man’s PCB Via Modeling Methodology

with 13 comments

You are a backplane designer and have been assigned to engineer a  new high-speed, multi-gigabit serial link architecture from several line cards to multiple fabric switch cards across a backplane. These links must operate at 6GB/s day one and be 10GB/s (IEEE 802.3KR) ready for product evolution. The schedule is tight, and you need to come up with a backplane architecture to allow the rest of the program to progress on schedule.

imageYou come up with a concept you think will work, but the backplane is thick with over 30 layers. There are some long traces over 30 inches and some short traces of less than 2 inches between card slots. There is strong pressure to reuse the same connector you used in your last design, but your gut tells you its design may not be good enough for this higher speed application.

Finally, you are worried about the size and design of the differential via footprint used for the backplane connectors because you know they can be devastating to the quality of the received signal.  You want to maximize the routing channel through the connector field, which requires you to shrink the anti-pad dimensions, so the tracks will be covered by the reference planes, but you can’t easily quantify the consequences on the via of doing so.

You have done all you can think of, based on experience, to make the vias as transparent as possible without simulating. Removal of non-functional pads on the inner layers, and planning to back-drill the connector via stubs will help,  but is it enough? You know in the back of your mind the best way to answer these questions, and to help you sleep at night,  is to put in the numbers.

So you decide to model and simulate the channel. But to do so, you need accurate models of the vias to plug into your favorite circuit simulator. But how do you get these? You have heard it all before; “for high-speed, the best way to model a via is with a 3D electro-magnetic field solver”.  Although this might be true, what if you don’t have access to such a tool, because the cost is more than your company wants to spend, or because you don’t have the expertise nor the time to learn how to build a model you can trust to make a timely decision?

On top of that, 3D field solvers typically produce S-parameter behavioral models. Since they represent only one sample of a given construction, it is impossible to perform what-if, worst case, min/max analysis with a single behavioral model. Because of this,  many iterations of the model are required; causing further delay in getting your answer.

A circuit model on the other hand, is a schematic representation of the actual device. For any physical structure, there can be more than one circuit model to describe it. All can give the same performance, up to some bandwidth. When run in a circuit simulator, it predicts a measurable performance of the structure. These models can be parameterized so that worst case analysis can be explored quickly.

The problem with a circuit model is that you often need a behavioral model to calibrate it, or need to use analytical equations to estimate the parameters. But, as my friend Eric Bogatin often says, “an OK answer NOW! is better than a great answer late”.

In the past, it was next to impossible to develop a circuit model of a differential via structure without a behavioral model to calibrate it. These behavioral models were developed through empirical formulas, measured data, or through the use of 3D EM field solvers.

Now, there is another way. I have nicknamed it, “The Poor Man’s PCB Via Modeling Methodology”. Here’s how it works.

Anatomy of a Differential Via Structure:

imageAn example of a differential via structure, shown in Figure 1, is representative of vias used to connect surface mounted components or backplane connectors to internal layer traces.

The via barrel is a plated through hole extending the entire length of a PCB stack-up. The outside diameter equals the drill diameter. The inside diameter is the finished hole size (FHS) after plating. Pads are used on layers to ensure there is sufficient copper for track attachment after drilling operation. When used in this fashion, they are referred to as functional pads. Anti-pads are the clearance holes in the plane layers allowing the via barrel to pass through them without shorting.

The via portion is the length of the barrel connecting one signal layer to another. It is often referred to as the through via since it is part of the signal net. The stub portion is the rest of the barrel extending to the outer layer of the PCB. In high-speed designs, a good rule of thumb to remember is that a via stub should be less than 300mils/BR in length; where BR is the bit rate in Gb/s.

Building a Simple Scalable Circuit Model:

imageOn close examination of Figure 2, a differential via structure can be represented by a twin-rod transmission line geometry with excess capacitance (shown in red) distributed over its entire length. The smaller the anti-pad diameter, the greater the excess capacitance. This ultimately results in lower via impedance, causing higher reflections.

In all high-speed serial link designs, it is common practice to remove all non-functional pads and to maximize the anti-pad clearance as much as practically possible. Oval anti-pads are often used in this regard to further mitigate excess via capacitance.

Figure 3 illustrates the equivalent circuit for a differential via that could be used in a channel topology simulation. Here it is modeled with Agilent ADS software using a coupled line transmission line model for each section. This equivalent circuit model can be scaled for any combination of layer transitions and integrated in any channel simulation scenario.


imageSince the cross-section of the via is constant throughout its length, the differential impedance of all sections of the via are the same. We only need to know the physical length of each segment and the effective dielectric constant (Dkeff) to get the time delay of each segment.

When driven differentially, the odd-mode parameters of each via are of major importance. Since the even-mode parameters have no impact on differential performance, both odd and even-mode parameters are set to the same values in the model.

The challenge then is to calculate the odd mode impedance (Zodd), representing the individual via impedance (Zvia), of a differential via structure and the effective dielectric constant (Dkeff) based on its geometry. Simple equations are used to determine these parameters.

Developing the Equations:

Anti-pads can vary in size and shape. They can be anything from round, to oval around each via, or even a large oval surrounding both vias as illustrated in Figure 4. Square, or rectangular variations (not shown) are similar. image

Referring back to Figure 2, we see the structure of each via looks a lot like two coaxial transmission lines with the inner layer reference planes acting like a shield. Electrostatically this is a good approximation, but because the shield is not continuous, the magnetic fields are not contained like they are in a coaxial structure. Instead they behave more like magnetic fields around a twin-rod structure.

So here lies the secret in modeling a differential via. We take the best of both geometries to calculate the odd-mode impedance representing Zvia.

For inductance, we will use the odd-mode inductance formula from the twin-rod transmission line geometry to calculate Lvia :


Referring to Figure 4, we then calculate the odd-mode capacitance for Cvia derived from an approximate formula for an elliptic coaxial structure developed by M.A.R. Gunston in his book, “Microwave Transmission Line Impedance Data” . In the original formula, both shield (W’+b) and inner conductor (w+t) are elliptical in shape and are dimensioned as shown. When the anti-pads are circular, then ln[(W’+b) /(w+t)] reduces to just ln[b/t)]; which is the denominator in the Coax equation. If we use Gunston’s approximation to calculate Cvia, then the equation becomes:










imageSince conventional FR4 type laminates are fabricated with a weave of glass fiber yarns and resin, they are anisotropic in nature. Because of this, the dielectric constant value depends on the direction of the electric fields. In a multi-layer PCB, there are effectively two directions of electric fields.

The one we are most familiar with has the electric fields perpendicular to the surface of the PCB; as is the case of stripline shown here in Figure 5. The dielectric constant, designated as Dkz in this case, is normally the bulk value of the dielectric specified by the laminate manufacturer’s data sheet.

The other case has the electric fields running parallel to the surface of the PCB, as is the case when a signal propagates through a differential via structure. In this situation, the dielectric constant, designated as Dkxy, can be15-20% higher than Dkz .

Therefore, assuming a nominal 18% anisotropic factor, Dkxy = 1.18(Dkz)

Now that we have defined Lvia, Cvia and Dkavg, Zvia can be estimated using the following equation:


But we are not finished yet. We still need to determine the effective dielectric constant (Dkeff) in order to accurately model the delay through the via and stub portion. Without the correct value, the quarter-wave resonant nulls in the insertion loss plot, due to the stub length, cannot be accurately predicted. The value for Dkeff is determined based on how much the via’s odd-mode impedance is decreased due to the distributed capacitive loading of the anti-pads.

To help us with this task, we start with the twin-rod formula. The odd-mode impedance (Zodd) is half the differential impedance (Ztwin), and is expressed as:


By substituting Equation 1 for Zodd into the equation above, and solving for Dkeff we eventually come up with the following equation:


Validating the Model:image

A simple 26 layer test vehicle was fabricated to compare the accuracy of the differential via circuit model to real vias. It consisted of two differential via pairs separated by 6 inches of 100 Ohm stripline differential pairs. Three sample via structures representing long, medium and short via stubs, as summarized in Figure 6, were measured using an Agilent N5230A VNA.

The differential vias had the following common parameters:

imageVia drill diameter; D = 28 mils
Center to center pitch; s = 59 mils
Oval anti-pads= 53 mils x 73 mils
Dk of the laminate = 3.65
Anisotropy in Dkxy = 18%
Zvia = Zstub = 31.7 Ohms (per Equation 1)
Dkeff = 6.8 (per Equation 2)

Agilent ADS software was used to model and facilitate simulation correlation of the measured data as captured in Figure 7. This simple model accounts for the discontinuity of the long through section and the long stub section. The top half is the measured channel using an S-parameter file. The bottom half is a circuit model of the channel. Since the probes were not calibrated out, they are part of the device under test. The balun transformers are used to facilitate the display of the S-parameter and TDR results.image

The comparison between the measured and simulated results of the insertion loss and TDR response for the three via stub cases using this simple approximation methodology is summarized in Figure 8.  The insertion loss plots, in the frequency domain, are shown on the left, while the TDR plots are shown on the right.

The resonant nulls in the SDD21 plots are due to the stub lengths. As you can see, the longer the stub, the lower the resonant frequency null. If this null happens at the Nyquist frequency of the bit rate, the eye will be totally closed. This is why we back-drill them out after the board has been fabricated.

The simulation correlation is excellent up to about 12 GHz. The TDR plots show excellent impedance matching and delay for all three cases, while the simulated stub resonant frequencies match the measured frequencies very well. As you can see, these simple approximations for Dkeff and Zvia are perfectly adequate in providing a quick and accurate circuit model for differential through hole vias typically used in backplane applications.image


As illustrated, a simple twin-rod model (Figure 2) is used as the basis for a practical differential via circuit modeling methodology. By using Equation 1 and Equation 2, you can quickly determine the odd-mode impedance and effective dielectric constant needed for the circuit model.

Of course, you should use this methodology first as a rough starting point to quickly estimate the performance of your differential via design. If your worst case topology simulations show the performance is marginal, then it is worth while to invest the time and money to develop a 3D full wave model to perform a more accurate analysis.

On the other hand, if you find this approximation shows the vias have little impact on the channel performance, it may be of greater value for you to invest your time and money in resolving other critical issues with your design.

Try it the next time you are losing sleep over your design challenges.

For more Information:


If you liked this design note and want to learn more, or get more details on this innovative via modeling methodology, you can visit my web site, LAMSIM , and download a copy of the white paper I wrote along with Eric Bogatin and Yazi Cao titled, “Method of Modeling Differential Vias” .

While you are there, feel free to investigate my other white papers and publications.

If you would like more information on our signal integrity and backplane services, or how we can help you achieve your next high-speed design challenge, email us at:

Written by Bert Simonovich

March 14, 2011 at 11:23 am

Twin-rod and Rod-over-plane Transmission Line Geometries

with one comment

In my last Design Note on coaxial transmission geometry,  I mentioned it was one of three unique cross-sectional geometries that have exact equations for inductance and capacitance. The other two are twin-rod and rod-over-plane.  All three relationships assume the dielectric material is homogeneous and completely fills the space when there are electric fields.

A common application for twin-rod geometry is twin-lead ribbon cable; once used for RF transmission between antenna and TV sets. With the popularity of cable and satellite TV over the years, twin-lead has given way to coaxial cable due to its superior noise rejection and shielding effectiveness.

If we look at Figure1, we can see the electromagnetic field relationship of a twin-rod geometry when it is driven differentially. As current propagates along one rod, an equal and opposite current flows in the opposite direction along the other.

The right half of Figure 1 shows the magnetic-field loops and direction of rotation around each rod. Only one loop is shown for clarity, but the number of loops is a function of the amount of current and the length of the rods. The counter-rotating  loops of current forms a virtual return at exactly one half of the space between the two rods. We call this a virtual return because if we were to put a conducting plane in the same position, the electromagnetic fields would look exactly the same.


Figure 1 Twin-rod geometry showing electromagnetic field relationship.

In his book, “Signal Integrity Simplified”,  Eric Bogatin defines the loop inductance as, “the total number of field line loops around a conductor per amp of current”, and the loop self-inductance as, “the total number of field line loops around a conductor per amp of current in the same loop” . Applying these definitions to the figure, the loop inductance (L) is the inductance between the two rods, and the loop self-inductance (L/2) is the loop self inductance to the virtual return plane; equal to one half the loop inductance.

Likewise, the left half of Figure 1 shows the electric field with a capacitance (C) between the two rods, and twice the capacitance (2C) from each rod to the virtual return plane.

The relationships between capacitance, inductance and impedance of a twin-rod geometry are described by the following equations:



Ctwin = Capacitance between twin-rods – F

Ltwin = Loop Inductance between twin-rods – H

Zdiff = Differential impedance of twin-rods – Ω

Dk = Dielectric constant of material

Len = Length of the rods – inches

r = Radius of the rods – inches

s = Space between the rods – inches

Because the electro-magnetic fields create a virtual return plane at exactly one half of the spacing between the rods, each rod behaves like a single rod-over-plane geometry as illustrated in Figure 2.


Figure 2 Electromagnetic fields comparison of Twin-rod (left) vs. Rod-over-plane (right) geometries.

Whenever an AC current carrying conductor is in close proximity to a conducting plane, as is the case for rod-over-plane, some of the magnetic-field lines penetrate it.  When the current changes direction, the associated magnetic-field lines also change direction; causing small voltages to be induced in the plane. These voltages create eddy currents, which in turn produce their own magnetic-fields.

Eddy current-induced magnetic-field line patterns look exactly like magnetic-field lines from an imaginary current  below the plane; located the same distance as the real current  above the plane. This imaginary current is called an image current, and has the same magnitude as the real current; except in the opposite direction [1]. The image current creates associated image magnetic-field lines in the opposite direction of the real field lines. As a result, the real magnetic-field lines are compressed between the rod and the plane. Since the rod-over-plane geometry has only one rod, the loop inductance is the same as the loop self-inductance.

For a twin-rod geometry, the odd mode capacitance is the capacitance of each rod to virtual return plane and is equal to twice the capacitance between rods.






Likewise, the odd mode inductance is the inductance of each rod to virtual return plane and equal to one half the inductance between rods.





The odd mode impedance of each rod is half of the differential impedance, and is equivalent to the rod-over-plane impedance.





[1] “Signal Integrity Simplified”, Eric Bogatin

Written by Bert Simonovich

March 1, 2011 at 9:41 am

Coaxial Transmission Line Geometry

with 2 comments

The coaxial (coax) transmission line geometry, described by Figure 1, consists of a center conductor; imbedded within a dielectric material; surrounded by a continuous outer conductor; also known as the shield. All share the same geometric center axis; hence the name coaxial. It is common practice to transmit the signal on the center conductor, while the outer conductor provides the  return path  for current back to the source. The shield  is usually grounded at both ends.

Figure 1 Example of a coaxial transmission line geometry and the electromagnetic
field patterns with respect to the current through the structure.

As the signal propagates along the transmission line, an electromagnetic field is set up between the outer surface of the center conductor and the inner surface of the shield. As illustrated in red, the electric E-field  pattern sets the capacitance per unit length, and the magnetic H-field, in blue, sets the inductance. For the center conductor, the “X” represents current flowing into the page and the “.” (dots) within the shield ring is current flowing out of the page.

Figure 2 describes the magnetic-field relationship for a coax geometry. As current propagates along the center conductor, concentric magnetic-field lines (blue) are created in the direction as shown following the right hand rule.

imageWhenever an AC current carrying conductor is in close proximity to a conducting plane, some of the magnetic-field lines penetrate it. If this plane totally surrounds the inner conductor, it becomes the outer conductor in a coax geometry, and some of the magnetic-field lines penetrate the entire circumference.  When the current changes direction, the associated magnetic-field lines also change direction, causing small voltages to be induced in the outer conductor. These voltages create eddy currents, which in turn, produce their own magnetic-fields.

Eddy current-induced magnetic-field line patterns look exactly like magnetic-field lines  (grey) from imaginary currents  surrounding the outer conductor. These imaginary currents are referred to as image currents, and have the same magnitude as the real current; except they are in the opposite direction [1]. For simplicity, there are only eight image currents shown. But in reality, there are many more; forming a continuous loop of imaginary currents on  a radius equal to twice the radius of the outer conductor to the center of the circle. The image currents create associated image magnetic-field lines in the opposite direction of the real field lines. As a result, the real magnetic-field lines are compressed and are entirely contained within the outer conductor.

The outer conductor thus forms a shield preventing external magnetic-fields from coupling noise onto the main signal and likewise, prevents its own magnetic field from escaping and coupling to other cables or equipment. This is why it is a popular choice for RF applications.

The nice thing about a coaxial transmission line is you can use equations to calculate the exact inductance and capacitance per unit length. There are only two other geometries that can do the same. They are, twin-rod and rod-over-plane; which I will cover at a later time in separate design notes.

The relationships between capacitance, inductance and impedance can be expressed by the following equations:


Ccoax = Capacitance – F

Lcoax = Inductance – H

Zo = Characteristic Impedance – Ohms

Dk = Effective Dielectric constant

Len = Length of the rods

D1 = Diameter of conductor

D2 = Diameter of shield

The coaxial structure can be flexible or semi-rigid in construction. Flexible coax is used for cable applications; like distributing cable TV or connecting radio transmitters/receivers with their antennas. To achieve its flexibility, the shield is usually braided and is protected by an outer plastic sheathing. Being flexible, the same cable can be reconfigured for different equipment applications.

Semi-rigid coax, in comparison, employs a solid tubular outer shield, which yields 100% RF shielding, and enables the dielectric material and center conductor to maintain a constant spacing; even through bends. If you have ever worked on your automobile brakes, semi-rigid coax resembles the rigid brake lines routed through the chassis to the wheels. Semi-rigid coax is usually used for microwave applications where optimum impedance control is required.  A bending tool is needed to form it to a consistent radius. After initial forming and installation, it is not intended to be flexed or reconfigured.

[1] “Signal Integrity Simplified”, Eric Bogatin

Written by Bert Simonovich

February 22, 2011 at 8:57 pm

PCB Vias – An Overview

with 5 comments

imageVias make electrical connections between layers on a printed circuit board. They can carry signals or power between layers. For backplane designs, the most common form of vias use plated through hole (PTH) technology. They connect the pins of connectors to inner signal layers. A PTH via is formed by drilling a hole through the layers to be connected and then copper plating it.

High Density Interconnects (HDI) is another via technology used to form very small vias where drilling holes, using a conventional drill bit, is impractical. Also known as micro-vias, this technology creates the hole with a laser before plating.

Via Aspect Ratio

Via aspect ratio is defined as the ratio of the circuit board thickness to the smallest unplated drilled hole diameter. It is an important metric you need to be aware of when specifying the minimum via hole size for your design, and designing your stack-up. For example, an unplated via with a drill diameter of 0.020 inches and a board thickness of 0.200, would have an aspect ratio of 10:1. The smaller the aspect ratio, the more consistent the plating is throughout the length of the via. It is desirable to have 2 mil plating thickness for the via walls. Large aspect ratio vias tend to have more plating at each end compared to the middle. This increases the chance of cracked via barrels due to z-axis expansion while soldering.

An aspect ratio of 6:1 pretty much ensures your board can be fabricated anywhere. Most high-end board shops have the capability of fabricating boards with 10:1 aspect ratio; for drill diameters of less than 0.020 inches. Practically, the smallest drill diameter used for a through holed via is 0.013 inches. At 10:1, the maximum board thickness would be 0.130 inches.

For drill diameters larger than 0.020 inches, the max aspect ratio can be anywhere from 15:1 to over 20:1; depending on the board shop. Since backplane via hole size is driven by the compliant pins of the connector, it is best to work with your board shop to determine the maximum board thickness they can fabricate with the minimum finished hole size (FHS) specified in the design.

Via Configurations

The following lists the various via configurations you might expect to find on any multi-layer PCB design:

  • Stub Via
  • Through Via
  • Blind or Micro-via
  • Buried Via
  • Back-drilled Via

Stub Via

imageThe Stub Via is the most common via configuration found in PCBs today. As illustrated, there are two variations; Stub Via A and Stub Via B.

For the Stub Via A example, it shows the through portion starting from the top layer and ending at some inner layer. The stub portion is the remaining portion continuing from the inner layer junction to the bottom layer.

The Stub Via B example shows the through portion  originating from one internal signal layer and terminating on another internal signal layer. In this scenario, there are two stubs. The first stub is from the first internal layer junction to the top layer; the second stub is from the second internal layer junction to the bottom layer.

Through Via

imageThrough vias are the oldest and simplest via configurations originally used in 2-4 layer PCB designs. Since the signals originate and terminate from the outer layers of the PCB, there are no stubs. In multi-layer PCB applications, they are an inexpensive way to eliminate the resonance effects caused by stubs where other mitigation techniques are not practical or are too expensive.


Blind/Buried Via

imageBlind and buried vias are just like any other via, except  they do not go all the way through the PCB. A Blind Via connects one or more internal layers to only one external layer. Controlled-depth drilling is used to form the holes prior to plating.

A buried via, on the other hand, is a plated hole which is completely buried within the board. It connects one or more internal layers and does not connect to an external layer. Using buried via technology is costly because the inner layers being interconnected need to be fully fabricated and plated before final lamination of the entire PCB.

A micro-via is a form of blind via. Because the holes are so small (0.006 inches or less), they are formed using lasers, and cannot penetrate more than one or two layers at a time. They are most commonly used in high-density PCB designs like cell phones, or in FPGA and custom ASIC chip packaging.

Back-drilled Via

imageHigh speed point-point serial link based backplanes are often thick structures; due to the system architecture and card-card interconnect requirements. Back-drilling the via stub is common practice on thick PCBs to minimize stub length for bit-rates greater than 3Gb/s.

Back-drilling is a process to remove the stub portion of a PTH via. It is a post-fabrication drilling process where the back-drilled hole is of larger diameter than the original PTH. This technology is often used instead of blind-via technology to remove the stubs of connector vias in very thick high-speed backplane designs. State of the art board fabrication shops are able to back-drill to within 8 mils of the signal layer to keep, so there will always be a small stub portion attached to the via.

Back-drilling is not without limitations. Smaller vias and tighter pitch driven by large pin count BGA packages makes back-drilling impractical in these applications; due to drill bit size and tolerance issues. Fortunately, smaller via diameters limit the maximum PCB thickness due to aspect ratio; thereby limiting the length of the stub to the board thickness. Careful planning the high-speed layers within the stack-up is one way to control stub length.

imageWe worry about stubs in high-speed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot of the channel. If one of these frequency nulls happen to line up at or near the Nyquist frequency of the bit rate, the received eye will be devastated resulting in a high bit-error-rate; even link failure.  A shorter stub length means these resonances will be pushed out further in frequency; ideally past the 5th harmonic of the Nyquist frequency as a rule of thumb.

Rules of thumb, in general, are no substitute for actual modeling and simulation. You should never depend on them to sign-off the final design; but you can use them to gain some intuition before hand. With that in mind, you can estimate the maximum stub length in inches using the following equation:



L Stub_max = maximum stub length in inches.

Dkeff = effective dielectric constant of the material surrounding the via hole structure.

BR = Bit rate in GB/s.

For example, the maximum stub length at 5GB/s should be less than 0.120 inches in FR4 material with a Dkeff of 4.0 to ensure the first resonant frequency null is greater than 5 times the Nyquist frequency of the bit rate. If the stub length is greater than this, it does not mean the design will not work at 5GB/s. Depending on just how much longer it is means there will be less than optimum eye opening at the receiver.

If you know the length of the stub, you can predict the fundamental resonant frequency, using the following equation:



Stub_len = stub length in inches.

fo = fundamental resonant frequency in GHz

So, using the same  Dkeff of 4.0, and stub length of 0.120 inches, we calculated in the above example, the first resonant frequency null would occur at approximately 12.3 GHz. If we assume this is the 5th harmonic, then the Nyquist frequency is approximately 2.5GHz and the bit rate is 5Gb/s; which is where we started.

Written by Bert Simonovich

February 15, 2011 at 1:29 pm

%d bloggers like this: