Bert Simonovich's Design Notes

Recently on the SI-List there was great debate on whether or not my Cannonball model can be used to determine surface ratio and radius of sphere parameters needed for Huray roughness model from data sheets alone.

The author of this paper, “Conductor surface roughness modeling: From “snowballs” to “cannonballs”, [1] argues it is impossible to accurately model transmission lines from data sheets alone and seems to imply that because I had measured data in advance that I had magically “adjusted” R_z parameter to get such good correlation to measurements in my EDICon 2016 paper, “Practical Model of Conductor Surface Roughness Using Cubic Close-packing of Equal Spheres” [5].

Unfortunately his paper has created more confusion than clarity. To be clear, there is only ONE “Cannonball” model, and it is based on the cubic close packing of equal spheres, also known as face-centered cubic (FCC) packing.

The author of [1] also advocates using a material model identification methodology, similar to what I like to call the Design Feedback Method, shown in Figure 1. The author believes it is the only “accurate” way of determining printed circuit board (PCB) material properties for modeling.

Figure 1 Design Feed Back Method flow chart

This involves designing, building and measuring a test coupon with the intended PCB trace geometry to be used in final design. After modeling and tuning various parameters to best fit measured data, material parameters are extracted and then used in channel modeling software to design the final product.

The problem with this approach for many small companies is: TIME, RESOURCES, and MONEY.

• Time to define stackup and test structures.
• Time to actually design a test coupon.
• Time to procure raw material – can take weeks, depending on scarcity of core/prepreg material.
• Time to fabricate the bare PCB.
• Time to assemble and measure.
• Time to cross-section and measure parameters.
• Time to model and fit parameters to measurements.

Then there is the issue of resources, which include having the right test equipment and trained personnel to get trusted measurements.

In the end this process ultimately costs more money, and material properties are only accurate for the sample from which they were extracted for the software and roughness model used. There is no guarantee extracted parameters reflect the true material properties.

There will be variation from sample to sample built from the same fab shop and more so from different fab shops because they have a different etch line and oxide alternative process.

For example Figure 2 shows measurements from two boards of the same design. As you can see there are differences in both insertion loss and TDR plots. Which curve do we use to fit parameters for material extraction to use in simulations? How many do we have to build and test to get a statistical sample of reality? How much time will this take? And how much money will it cost, especially if several PCB stackup geometries are required?

Figure 2 Comparison of insertion loss and TDR measurements of two boards of the same design

But, as Eric Bogatin often likes to say, “Sometimes an OK answer NOW is better than a good answer late”. For many signal integrity engineers, and design consultants, like myself, have to come up with an answer sooner, rather than later for many reasons. And depending on the issue at hand, those answers may be good enough. This was the initial motivation for my research.

So where do we get these parameters? Often the only sources are from manufacturers’ data sheets alone. But in most cases, the numbers do not translate directly into parameters needed for the EDA tools.

This paper will revisit the Cannonball model as it applies to the CMP-28 reference platform from Wildriver Technology [14], and as part of it I will show:

• How to determine effective dielectric constant (D_keff) due to roughness from data sheets alone.
• How to apply my simple Cannonball stack model to determine roughness parameters needed for Huray model from data sheets alone.
• How to apply these parameters using Simbeor software [10].
• How to pull it all together with a simple case study.

But before we get into it, it is important to give a bit of background on material properties and PCB fabrication process.

Electro-deposited Copper

Electro-deposited (ED) copper is widely used in the PCB industry due to its low cost. A finished sheet of ED foil has a matte side and drum side. The matte side is usually treated with tiny nodules and is the side bonded to the core laminate. The drum side is always smoother than the matte side. For high frequency boards, sometimes the drum side of the foil is treated instead and bonded to the core. In this case it is known as reversed treated foil (RTF).

IPC-TM-650-2.2.17A defines the procedure for determining the roughness or profile of metallic foils used on PCBs. Profilometers are often used to quantify the roughness tooth profile of electro-deposited copper.

Nodule treated tooth profiles are typically reported in terms of 10-point mean roughness (R_z). Some manufacturers may also report root mean square (RMS) roughness (R_q). For standard foil this is the matte side. For RTF it is the drum side. Most often the untreated, or prepreg side, reports average roughness (R_a) in manufacturers’ data sheets.

With the realization of roughness having a detrimental effect on insertion loss (IL), copper suppliers began providing very low profile (VLP) and ultra-low profile (ULP) class of foils. VLP foils have treated roughness profiles less than 4 μm while ULP foils are less than 2 μm. Other names for ULP class are HVLP or eVLP, depending on the foil manufacturer.

It is important to obtain the actual vendor’s copper foil data sheet used by the respective laminate supplier for accurate modeling.

Oxide/Oxide Alternative Treatment

In order to promote good adhesion of copper to the prepreg material during the PCB lamination process, the copper surface is treated with chemicals to form a thin, nonconductive film of black or brown oxide. The controlled oxidation process increases the surface area, which provides a better bond between the prepreg and the copper surface. It also passivates the copper surface to protect it from contamination.

Although oxide treatment has been used for many years, eventually the industry learned that the lack of chemical resistance resulted in pink ring, which is indicative of poor adhesion between copper and prepreg. This weakness has led to oxide alternative (OA) treatments which rely on some sort of etching process, but no oxide layer is formed.

With the push for smoother copper to reduce conductor loss, newer chemical bond enhancement treatments, working at the molecular level, were developed to maintain copper smoothness, yet still provide good bonding to the prepreg.

Since OA treatment is applied to the drum side of the foil during the PCB Fabrication process, the OA roughness numbers should be used instead of R_a specified in foil manufacturer’s data sheets. RTF foil is modeled differently and discussed later in the case study.

Tale of Two Data Sheets

Everyone involved in the design and manufacture of PCBs knows the most important properties of the dielectric material are the dielectric constant (D_k) and dissipation factor (D_f ).

Using D_k / D_f numbers for stackup design and channel modeling from “Marketing” data sheets, like the example shown in Figure 3, will give inaccurate results. These data sheets are easily obtained when searching laminate supplier’s web sites.

Figure 3 Example of a “Marketing” data sheet easily obtained from laminate supplier’s web site. Source Isola Group.

Instead, real or “Engineering” data sheets, which are used by PCB fabricators to design stackups, should be used for PCB interconnect modeling. These data sheets define the actual thickness, resin content and glass style for different cores and prepregs. They include D_k / D_f over a wide frequency range; usually from 100 MHz-10GHz.

Figure 4 Example of an “Engineering” data sheet showing D_k/D_f for different glass styles and resin content over frequency. Source Isola Group.

Effective D_k Due to Roughness

Many engineers assume D_k published is the intrinsic property of the material. But in actual fact, it is the effective dielectric constant (D_keff) generated by a specific test method. When simulations are compared against measurements, there is often a discrepancy in D_keff, due to increased phase delay caused by surface roughness.

D_keff is highly dependent on the test apparatus and conditions of how it is measured. One method commonly used by many laminate suppliers is the clamped stripline resonator test method, as described by IPC-TM-650, 2.5.5.5, Rev C, Test Methods Manual.

The measurements are done under stripline conditions using a carefully designed resonant element pattern card made with the same dielectric material to be tested. As shown in Figure 5, the card is sandwiched between two sheets of unclad dielectric material under test. Then the whole structure is clamped between two large plates; each lined with copper foil and are grounded. They act as reference planes for the stripline.

Figure 5 Illustration of clamped stripline resonator test method, as described by IPC-TM-650, 2.5.5.5, Rev C, Test Methods Manual

This method assures consistency of product when used in fabricated boards. It does not guarantee the values directly correspond to design applications.

This is a key point to keep in mind, and here is why.

Since the resonant element pattern card and material under test are not physically bonded together, there are small air gaps between the various layers that affect measured results. The small air gaps result in a lower D_keff than what is measured in real applications using foil with different roughness bonded to the same core laminate. This is the primary reason for phase delay discrepancy between simulation and measurements.

If D_k and R_z roughness parameters from the manufacturers’ data sheets are known, then the effective D_k due to roughness (D_{keff_rough}) of the fabricated core laminate can be estimated by [2]:

Equation 1

where: H_smooth is the thickness of dielectric from data sheet; R_z is 10-point mean roughness from data sheet; D_k is dielectric constant from data sheet

Most EDA tools include a wideband causal dielectric model. To use it, you must enter D_k and D_f at a particular frequency. I found it is usually best to use the values near the Nyquist frequency of the baud rate.

Modeling Copper Roughness

“All models are wrong but some are useful”– a famous quote by George E. P. Box, who was a British statistician in the mid-20^th century. The same can be said when using various roughness models.

For example many roughness models require RMS roughness numbers, but often R_z is the only number available in data sheets, and vice versa. If R_z is defined as the sum of the average of the five highest peaks and the five lowest valleys of the roughness profile over a sample length, and R_q is the RMS value of that profile, then the roughness can be modeled as a triangular profile with a peak to valley height equal to R_z, as illustrated in Figure 6.

Figure 6 Triangular roughness profile model with peak to valley height equal to 10-point mean roughness R_z.

If we define the RMS height of the triangular roughness profile is equal to ∆, then:

Equation 2

And likewise, if we assume ∆ ~ R_q, then:

Equation 3

Several modeling methods were developed over the years to determine a roughness correction factor (K_SR). When multiplicatively applied to the smooth conductor attenuation (α_smooth), the attenuation due to roughness (α_rough) can be determined by:

Equation 4

Huray Model

In recent years, the Huray model has found its way into popular EDA software due to the continually increasing need for better modeling accuracy. The model is based on a non-uniform distribution of spherical shapes resembling “snowballs” and stacked together forming a pyramidal geometry.

By applying electromagnetic wave analysis, the superposition of the sphere losses can be used to determine the total loss of the structure. Since the losses are proportional to the surface area of the roughness profile, an accurate estimation of a roughness correction factor (K_SRH) can be analytically solved by [4]:

Equation 5

Although it has been proven to be a pretty accurate model, it relied on analysis of scanning electron microscopy (SEM) pictures of the treated surface and tuning of parameters for best fit to measured data. This is not a practical solution if all you have is roughness parameters from manufacturers’ data sheets.

Cannonball-Huray Model

Building upon the work already done by Huray, and using the Cannonball stack principle, the sphere radius and flat base area parameters are easily estimated solely from roughness parameters published in manufacturers’ data sheets.

As illustrated in Figure 7 there are three rows of equal sized spheres stacked on a square tile base. Nine spheres are on the first row, four spheres in the middle row, and one sphere on top. This stacking arrangement is known as close-packing of equal spheres, but more commonly known as the “Cannonball” stack due to the method used by sailors to stack actual cannonballs aboard ships.

Figure 7 Cannonball-Huray physical model. The height of the stack is the RMS height of the peak to valley profile equal to R_z from data sheets.

If we could peer into the stack and imagine a pyramid lattice structure connecting to the center of all the spheres, then the total height is equal the height of two pyramids plus the diameter of one sphere.

Given the height of the Cannonball stack (∆) is equal to the RMS value of the peak to valley roughness profile; then from method described in my earlier papers, determining the sphere radius (r ), from R_z found in data sheets, can be further simplified and approximated as [13]:

Equation 6

and base area (A_flat) as:

Equation 7

Because the model assumes the ratio of A_matte/A_flat = 1, and there are only 14 spheres, the original Cannonball-Huray model can be further simplified to:

Equation 8

where: K_CH (f) = Cannonball-Huray roughness correction factor, as a function of frequency; δ (f) = skin-depth, as a function of frequency in meters; r = the radius of spheres in meters (Equation 6)

CMP28 Case Study Revisited

To test the accuracy of the model, stackup details and measured data from a CMP28 test platform, design kit, courtesy of Wildriver Technology, shown in Figure 8, was used for model validation. The PCB stackup is shown in Figure 9

Two different sets of S-parameter (s2p) files from a 2 inch and 8 inch single-ended (SE) stripline traces shown were used in this study. The original set of measurements, from my previous papers, and a second set provided as part of CMP-28 design kit from another PCB were used for model correlation.

The 6 inch transmission line segment S-parameter data was de-embedded using Ataitec ISD software [8] for both sets of data.

Figure 8 Photo of a portion of CMP-28 test platform courtesy of Wildriver Technology used for model validation.

Figure 9 CMP-28 PCB Stackup

The PCB was fabricated with Isola FR408HR 3313 core and prepreg, with 1 oz. RTF. D_k and D_f at 10GHz were obtained from the FR408HR data sheet found on their web site and shown in Figure 10 & Figure 11.

Figure 10 Isola FR408HR data sheet used for core dielectric properties.

Figure 11 Isola FR408HR data sheet used for prepreg dielectric properties.

The foil used on FR408HR core laminates is MLS, Grade 3, controlled elongation RTF from Oak-matsui. Roughness Rz parameters for drum and matte sides are 120μin (3.048 μm) and 225μin (5.715μm) respectively for 1 oz. copper foil.

Figure 12 MLS RTF foil data sheet used on FR408HR laminate.

An oxide or oxide alternative (OA) treatment is usually applied to the copper surfaces prior to final PCB lamination. When it is applied to the matte side of RTF, it tends to smoothen the macro-roughness slightly. At the same time, it creates a surface full of microvoids which follows the underlying rough profile and allows the resin to fill in the cavities, providing a good anchor.

MultiBond MP from Macdermid Enthone is an example of an oxide alternative micro-etch treatment commonly used in the industry. Typically 50 μin (1.27μm) of copper is removed when the treatment is completed, depending on the board shop’s process control, as per Figure 13.

In a subsequent paper by J.A. Marshall, presented at IPC APEX 2015 titled, “Measuring Copper Surface Roughness for High Speed Applications” [11], there is data supporting the hypothesis that RTF roughness gets smoother after OA application.

Figure 13 Macdermid Enthone MultiBond MP data sheet reference from their web site.

Table 1 summarizes the PCB design parameters, dielectric material properties and copper roughness parameters obtained from respective manufactures’ data sheets.

Table 1 CMP-28 Test Board and Data Sheet Parameters

From Table 1 and by applying Equation 1, D_keff of core and prepreg due to roughness were determined to be:

Next, the Cannonball model’s sphere radiuses, for matte and drum side of the foil, were determined to be:

Because most EDA tools only allow a single value for the radius parameter, the average radius (r_avg) was determined to be:

Equation 9

Simbeor electromagnetic software from Simberian Inc. [10] was used for modeling the transmission lines. It includes the latest and greatest dielectric and conductor roughness models, including the Huray-Bracken causal metal model.

Solution explorer pane and solution tree, as shown in Figure 14, allows you to edit and view solution data as a tree structure. All parameters from Table 1 were entered here.

Simbeor requires two parameters; roughness factor (RF1) and sphere radius (SR1). Because the Cannonball model always has N=14 spheres and base area (A_flat) is always 36r², r² cancels out and RF1 can be simplified to:

Equation 10

Sphere radius (SR1) is r_avg = 0.225 as calculated from Equation 9.

Figure 14 Simbeor Solution Explorer Pane and Solution Tree

The wideband causal dielectric model option was used to model dielectric properties over frequency. Effective D_k due to roughness for core and prepreg, calculated above, were substituted instead of data sheet values. Standard copper resistivity of 1.724e-8 ohm-meter was used.

After the transmission lines were modeled and simulated, the S-parameter results were saved in touchstone format. Keysight ADS [5] was used for further simulation analysis and comparison.

D_keff can be derived from phase delay. This is also known as time delay (TD) and is often used as a metric for simulation correlation accuracy for phase. TD, as a function of frequency, in seconds, is calculated from the unwrapped measured transmission phase angle, and is given by:

Equation 11

and:

D_keff , as a function of frequency, is then given by:

Equation 12

where:c = speed of light (m/s); Length = length of conductor (m)

Figure 15 compares the simulated results vs measurement of a 6inch, de-embedded stripline trace. The red plots are measured from CMP-28 design kit data. The data was bandwidth limited to 35 GHz. The blue plots are the original measured data used in my previous paper [5]. The green plots are modeled with data sheet values only with oxide alternative treatment applied. SE IL is shown on the left and D_keff is shown on the right. As can be seen, there is excellent correlation.

Figure 15 Measured vs simulated insertion loss (left) and D_keff (right) with OA etch treatment applied.

The author of [1] suggests is that because I had the measured data, R_z was “adjusted” to show excellent results. What he is implying is my “adjusting” the roughness, due to the oxide treatment, was the reason for such good results, in spite of the fact Macdermid’s OA data sheet reports typical 50 μin of copper removal after treatment and data from [11] showing RTF gets slightly smoother after OA treatment.

So ok, let’s see what happens if I didn’t adjust the roughness due to OA treatment. Instead of using R_z matte side after micro-etch (4.445 μm ) roughness, we will use 5.715 μm from data sheet.

This will affect D_keff of prepreg and average sphere radius r_{avg ,} so we will recalculate them:

And average radius is:

Figure 16 compares the simulated results vs measurement. The red plots are measured from CMP-28 design kit data. The blue plots are the original measured data used in my previous paper [5]. The green plots are modeled with data sheet values only without oxide alternative treatment applied. SE IL is shown on the left and D_keff is shown on the right.

As can be seen, there is still excellent correlation with insertion loss even though OA was not considered. As expected using the rougher number would increase effective Dk. But in the end the TDR plots in Figure 17shows impedance change is negligible.

Figure 16 Measured vs simulated insertion loss (left) and phase delay (right) without OA etch treatment applied.

Figure 17 Measured vs simulated TDR plots with OA etch treatment (left) and without (right).

Summary and Conclusions

By using Cannonball-Huray model, with copper foil roughness and dielectric material properties obtained solely from respective manufacturers’ data sheets, practical PCB interconnect modeling for high-speed design is now achievable using commercial field-solving software employing Huray model.

Measured results from two different boards confirmed there are variations due to manufacturing that would affect material model extraction method accuracy.

When oxide alternative treatment was not considered, even though the matte side roughness of RTF gets smoothened during the PCB fabrication process, the simulated results still show excellent correlation to the original measured data from previous paper [5].

References

[1] Y. Slepnev, “Conductor surface roughness modeling: From “snowballs” to “cannonballs”.

[2] B. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”. DesignCon 2017, Proceedings, Santa Clara, CA, 2017

[3] L. Simonovich, “Practical method for modeling conductor roughness using cubic close-packing of equal spheres,” 2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), Ottawa, ON, 2016, pp. 917-920. doi: 10.1109/ISEMC.2016.7571773.

[4] Huray, P. G. (2009) “The Foundations of Signal Integrity”, John Wiley & Sons, Inc., Hoboken, NJ, USA., 2009

[5] L.Simonovich, “Practical Model of Conductor Surface Roughness Using Cubic Close-packing of Equal Spheres”, EDICon 2016, Boston, MA

[6] Keysight Advanced Design System (ADS) [computer software], (Version 2017). URL: http://www.keysight.com/en/pc-1297113/advanced-design-system-ads?cc=US&lc=eng.

[7] Isola Group S.a.r.l., 3100 West Ray Road, Suite 301, Chandler, AZ 85226. URL: http://www.isola-group.com/

[8] Ataitec, URL: http://ataitec.com/products/isd/

[9] V. Dmitriev-Zdorov, B. Simonovich, I. Kochikov, “A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics”, DesignCon 2018 Proceedings, Santa Clara, CA, 2018

[10] Simberian Inc., 2629 Townsgate Rd., Suite 235, Westlake Village, CA 91361, USA, URL: http://www.simberian.com/

[11] John A. Marshall, “Measuring Copper Surface Roughness for High Speed Applications”, IPC APEX Expo 2015.

[12] Macdermid Enthone, Multibond MP, Inner Layer Oxide Alternative Bonding. URL: https://electronics.macdermidenthone.com/products-and-applications/printed-circuit-board/surface-treatments/innerlayer-bonding

[13] B. Simonovich, “PCB Interconnect Modeling Demystified”. DesignCon 2019, Proceedings, Santa Clara, CA, 2019.

[14] Wild River Technology LLC 8311 SW Charlotte Drive Beaverton, OR 97007. URL: https://wildrivertech.com/

We worry about via stubs in high-speed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot (IL) of the channel. But are all via stubs bad? Well, as with most answers relating to signal integrity, “It depends.”

If one of these frequency nulls happen to line up at or near the Nyquist frequency of the bit- rate (i.e. 1/2 of the bit-rate), the received eye will be devastated, resulting in a high bit-error-ratio (BER), or even link failure.

Figure 1 shows simulation results of two backplane channels. On the left are measured SDD21 insertion loss and eye diagram of a 10 GB/s, non-return-to-zero (NRZ) signal, with short through vias and long stubs ~ 270 mils. On the right, shows measured SDD21 IL and eye diagram of a channel with long through vias and shorter stubs ~ 65 mils

Because the ¼ -wave resonant null occurs at a frequency ~ 4. 4 GHz, this is near the Nyquist frequency for 10 GB/s. As can be seen, the eye is totally closed for the long stub case. But when the shorter stub case is simulated, the eye is open with plenty of margin.

So how does a via stub cause ¼ -wave resonance? This question can be explained with the aid of Figure 2. Starting on the left, we see a via with two sections. The through (thru) part is the top portion connecting a device pin to an inner layer trace of a printed circuit board (PCB). The stub portion is the lower portion and is an open circuit.

On the right a sinusoidal signal is injected into the pin at the top of the via and travels along the thru portion until it reaches the junction of the internal trace and stub. At that point, the signal splits. Some of it travels along the trace, and the rest continues down the stub. Once it reaches the bottom, it reflects back up. When it reaches the trace junction, it splits again with a portion traveling along the trace and the rest back to the source.

If f  is the frequency of a sine wave, and the time delay (TD) through the stub portion equals a ¼ -wavelength, then when it reflects at the bottom and reaches the junction again, it will be delayed by ½ a cycle and cancels most of the original signal.

Figure 2 Illustration of a ¼ -wave resonance of a stub. If f = frequency where TD = ¼ wavelength, then when 2TD = ½ cycle minimum signal received.

Resonance nulls occurs at the fundamental frequency ( f_o) and at every odd harmonic. If you know the length of the stub (in inches) and the effective dielectric constant (Dk_eff), surrounding the via hole structure, the resonant frequency can be predicted by:

Equation 1

Where: f_o is the ¼ -wave resonant frequency (GHz); c is the speed of light (~11.8 in/ns); Stub_length is inches.

You will find that Dk_eff is not the same as the bulk Dk published in laminate manufacturers’ data sheets. It is typically higher. A higher Dk_eff increases phase delay through the via resulting in a lower resonant frequency.

One reason is excess capacitance from the via pads as well as the via barrel’s proximity to the clearance hole openings (also known as anti-pads) in plane layers. The other is because of the anisotropic nature of the laminate material.

For the example in Figure 1, the ¼ -wave resonant frequency of the long via stub is ~ 4.4 GHz. With a stub length of ~ 270 mils, this gives a Dk_eff of 6.16, which is considerably higher than the published bulk Dk of 3.65. When you model a via in an electro-magnetic (EM) 3D field solver, it automatically accounts for the excess capacitance, but you will still need to compensate for the anisotropic nature of the dielectric.

A material is anisotropic when there are different values for parallel (x-y) vs perpendicular (z) measured values for dielectric constant. Dielectric constant and loss tangent, as published in manufacturers’ data sheets, report perpendicular measured values. For FR-4 fiberglass reinforced laminates, anisotropy can range from 15% -25% higher. The bad news is these numbers are not readily available from data sheets.

For differentially driven vias with plane layers evenly distributed throughout the entire stackup, Dk_eff can be roughly estimated by:

Equation 2

Where: Dk_xy is the dielectric constant adjusted for anisotropy (15%-25% higher); Dk_z is the bulk dielectric constant from data sheets; s is via-via spacing; drillØ is drill diameter; H and W are anti-pad shape dimensions as shown in Figure 3 .

Figure 3 Anti-pad parameters for Equation 2.

The effects of via stubs can be mitigated by: using blind or buried vias; back-drilling; or by using thru vias only (i.e. from top layer to bottom layer). Practically, the shortest stub that can be achieved by back-drilling is on the order of 5 to 10 mils.

As a rule of thumb, we usually strive to have an interconnect bandwidth (BW) to be five times the Nyquist frequency of the bit-rate. Since a ¼-wave resonant null behaves somewhat like a notch filter, depending on the high-frequency roll-off due to Q-factor, frequencies near resonance will be attenuated. For that reason a good rule of thumb to follow is making sure the first null should occur at the 7^th harmonic, or higher, of the Nyquist frequency to maintain the integrity of the 5^th harmonic frequency component that makes up the risetime of a signal.

With this in mind, for a given baud-rate (Baud) in GBd, the maximum stub length (l_max), in inches can be estimated by:

Equation 3

For NRZ signaling, the baud-rate is equal to the bit rate. But for pulse-amplitude modulation (PAM-4) signaling, which has 2 symbols per bit time, the baud-rate is ½ of that. Thus a 56 GB/s PAM-4 signal has a baud-rate of 28 GBd, and the Nyquist frequency is 14 GHz, which happens to be the same as 28 GB/s NRZ signalling.

Figure 4 presents a chart of maximum stub length vs baud-rate based on Equation 3, using a Dk_eff = 6.16 (blue) vs 3.65 (red). It shows us the higher the baud-rate, the more the stub length becomes an issue, especially past 10 GBd. We also get a feel for the sensitivity of stub length to Dk_eff . Even though there is ~ 70% difference in Dk_eff, there is only ~ 30% delta in stub lengths for the same baud-rate. This means that even if we use the bulk Dk published in data sheets, we are probably not dead in the water.

If the respective stub length is greater than this, it does not mean there is a show stopper. Depending on how much longer means the eye opening at the receiver will be degraded and we lose margin. We see this by the example in Figure 1. Even though the stub lengths in the channel were almost double the value at 10 GBd from the chart, there is still plenty of eye opening.

Figure 4 Chart showing estimated maximum stub length vs baud-rate with Dk_eff of 6.16 (red) vs 3.65 (blue) based on Equation 3

To further explore design space and test out the rule of thumb, a generic circuit model was built using Keysight ADS with the ability to vary the via stub lengths

Referring to the chart, at 28 GBd, the maximum stub length should be 12 mils, assuming a Dk_eff of 6.16. Figure 5 shows simulation results for NRZ signalling. As can be seen, there was a difference of only 17 mV in eye height (1.5%), and no extra jitter for 12 mil stubs compared to 5 mil stubs.

Figure 5 Eye diagrams comparison with BER at 10E-12 for stub lengths of 5 mils vs 12 mils. Modeled and simulated with Keysight ADS.

But if we use the exact same channel model, and use the generic PAM-4 IBIS AMI model from Keysight Technologies, we can see the results plotted in Figure 6. On the left are the eye openings with 5 mil stubs and the right with 12 mil stubs. In this case, there was an average reduction of ~7 mV (6%) in eye heights, and 0.24 ps (2%) in eye widths at BER 10E-12 across all three eyes.

Figure 6 PAM-4, 28 GBd (56 GB/s) eye height and width comparison at BER of 10E-12 for 5 mil vs 12 mil stub lengths. Modeled and simulated with Keysight ADS.

Because PAM-4 signalling has three smaller eyes, that are one-third the size of an NRZ eye for the same amplitude, it is more sensitive to channel impairments. From the above examples, we can see NRZ had only 1.5% reduction in eye height compared to 6% for PAM-4. Similarly there was no increase in jitter for NRZ compared to 2% increase for PAM-4 when stub lengths changed from 5 mils to 12 mils.

What this says is maintaining a BW to 5 times Nyquist rule of thumb, when estimating via stub lengths, is quite conservative for NRZ signalling. There is almost the same BW as the channel with 5 mil stub, which was the original objective. But because PAM-4 is more sensitive to impairments, it shows there is less margin.

In summary then, rules of thumb and related equations are a good way to reinforce your intuitions or to give you an answer sooner rather than later. They help you know what to expect before you take any measurements or perform any simulations. But they should never be used to sign off on any high-speed design.

Because every system will have different impairments affecting BER, the only way to know how much margin you have is by modeling the via with a 3-D EM field solver, based on the actual stackup and simulating the entire channel complete with crosstalk, if margins are tight. This is even more critical for data rates above 10 GBd.

So to answer the original question, “are all via stubs bad”? Well, the answer is it still depends. For NRZ signalling, there is more leeway than for PAM-4. But you now have a practical way to quickly quantify the answer if you know the stub length, baud-rate and delay through the via.

You know you have an obsession when you are flying 6 miles over Colorado; look out your window at the beautiful scenery; and all you can think about is how the rocky mountain topology reminds you of conductor surface roughness! Well call me obsessed because that’s exactly what I thought on my way to DesignCon 2017 in Santa Clara, CA.

For those of you who know me, you know that I have been researching practical methods to model conductor surface roughness, and its effect on insertion loss (IL). I have presented several papers on the subject over the last couple of years. It’s one of my pet projects. This year, at DesignCon, I presented a paper titled, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness” .

Everyone involved in the design and manufacture of printed circuit boards (PCBs) knows one of the most important properties of the dielectric material is the relative permittivity (ε_r), commonly referred to as dielectric constant (D_k). But in reality, D_k is not constant at all. It varies over frequency as you will see later.

We often assume the value reported in manufacturers’ data sheets is the intrinsic property of the material. But in actual fact, it is the effective dielectric constant (D_keff) generated by a specific test method. When you compare simulation against measurements, you will often see a discrepancy in Dkeff and IL, due to increased phase delay caused by surface roughness. This has always bothered me. For a long time I was always looking for ways to come up with Dkeff from data sheet numbers alone. Thus the obsession and motivation for my recent research work.

Since phase delay, also known as time delay (TD), is proportional to Dkeff of the material, my theory was that the surface roughness profile decreases the effective separation between parallel plates, thereby increasing the electric field (e-field) strength, resulting in additional capacitance, which accounts for an increase in effective D_k and TD.

The main focus of my paper was to prove the theory and to show a practical method to model Dkeff and TD due to surface roughness. By referencing Gauss’s Law for charged parallel plates, I confirmed mathematically, and through simulation, how the dielectric thickness and permittivity are interrelated to e-field and capacitance. I also revealed how the 10-point mean (R_z) roughness parameter can be applied to finally estimate effective Dkeff due to roughness. Finally I tested the method via case studies.

In his book, “Transmission Line Design Handbook”, Wadell defines D_keff as the ratio of the actual structure’s capacitance to the capacitance when the dielectric is replaced by air.

D_keff is highly dependent on the test apparatus and conditions of how it is measured. There are several methods used in the industry. One method that is commonly used by many laminate suppliers is called the clamped stripline resonator test method. It is described by IPC-TM-650, section 2.5.5.5, Rev C.

In short, this method rapidly tests dielectric material for permittivity and loss tangent, over an X-band frequency range of 8-12.4 GHz, in a production environment. It does not guarantee the values are accurate for design applications.

Here’s why:

The measurements are made under stripline conditions, using a carefully designed resonant element pattern card, made out of the same dielectric material to be tested. The card is sandwiched between two sheets of unclad dielectric material under test. The whole structure is then clamped between two large plates, lined with copper foils that are grounded.

Since the resonant element pattern card and material under test are not physically bonded together, there are small air gaps between the various layers affecting measured results. These air gaps are caused in part by:

• Removing the copper from the material under test, leaving the bare substrate, complete with the micro void imprint of the copper roughness.
• The air gap between resonant element pattern card and material under test, due to the copper thickness of the etch pattern.
• The roughness profile of the copper, on the resonant element pattern card and fixture’s grounded foil reference planes, are different than would be in practice, unless the same foil type is used.

If D_keff and R_z roughness parameters from the manufacturers’ data sheets are known, then the effective D_k due to roughness (D_{keff_rough}) of the fabricated core laminate can now be easily estimated by:

Equation 1

Where: H_smooth is the thickness of dielectric from data sheet; R_z is 10-point mean roughness from data sheet; and D_keff is the D_k from data sheet.

With reference to Figure 1, using D_keff with rough copper model, as shown on the left, is equivalent to using D_{keff_rough}, with smooth copper model, as shown on the right. Therefore all you need to do is use D_{keff_rough} for impedance calculations, and any other numerical simulations based on surface roughness, instead of D_k published in data sheets.

It is as simple as that.

Figure 1 Effective D_k due to roughness model. Using D_keff with rough copper model (left) is equivalent to using D_{keff_rough} with smooth copper model (right).

For example, one case study I presented used measurements from a CMP28 modeling platform from Wild River Technology. The PCB was fabricated with FR408HR material and reverse treated foil (RTF). Keysight EEsof EDA ADS software was used for modeling and simulation. The results are shown in Figure 2.

The left graph shows results when data sheet values for core and prepreg were used. D_keff measured (red) was 3.761, compared to simulated D_keff (blue) of 3.626, at 10 GHz. This gave a delta of ~ 4%. But when the D_{keff_rough} was used for core and prepreg the delta was within 1%.

Figure 2 Measured vs simulated D_keff using FR408HR data sheet values for core and prepreg (left) and using D_{keff_rough} (right). Modeled and simulated with Keysight EEsof EDA ADS software.

The paper shows in more detail how Equation 1 was derived, based on Gauss’ Law. In addition, I show how IL and phase delay is also improved when D_{keff_rough} is used instead of data sheet values. You can download the paper titled, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”, and other papers on modeling conductor loss due to roughness from my web site.