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The Effects on Transmission Line Losses Due to Mixed Reference Plane Roughness Case Study

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This article is an edited version of White Paper, “Heuristic Modeling of Transmission Lines due to Mixed Reference Plane Foil Roughness in Printed Circuit Board Stackups” [1].

Designing the right printed circuit board (PCB) stackup can make or break your product performance. If your product has circuitry that is transmission loss sensitive, then paying attention to conductor surface roughness is paramount.

Conductor surface roughness traditionally has been applied to copper foil to promote adhesion to the dielectric material. Early PCBs were only constructed with single or double-sided copper core laminates. The only important metric for copper was its purity and the roughness to improve peel strength. There was no such thing as a PCB stackup and nobody worried about impedance or transmission line losses.

But over the years PCBs have evolved into multi-layer constructions with evermore attention being paid to impedance control and transmission line losses. Thus a PCB stackup definition became vital for consistent performance.

Like any construction project, you need a blueprint before you start building. Similarly for PCBs, you need a stackup drawing and detailed fabrication notes. Part of the stackup design process includes signal integrity (SI) modeling for characteristic impedance and transmission loss. If your design is running at 56Gig pulse amplitude modulation level 4 (PAM-4), for example, you are probably looking at low loss dielectrics and low roughness copper for the signal traces.

But what is sometimes overlooked in the stackup, is the roughness of the reference planes. Often thin core laminate power and ground (GND) planes will specify reverse-treated foils (RTF), which are rougher on the side that bonds to the prepreg. Sometimes one of these planes, usually GND, acts as a reference plane to an adjacent signal layer as shown in Figure 1. If that adjacent high-speed signal layer is using smoother copper than one or both reference planes, a higher insertion loss than expected for that layer will occur and possibly ruin your day.

A similar scenario could occur for high density interconnect (HDI) technology. This is a popular method to increase component density on modern PCBs. By the nature of their stackup construction, a rougher copper reference plane could sometimes also end up adjacent to a signal layer as well. Thus, if insertion loss is a concern, copper foil roughness of reference planes needs to be considered.


Figure 1 An example cross-section stripline geometry from a stackup showing thin core laminate (top) with RTF bonded to prepreg and adjacent to a high-speed differential pair with smooth foil.

So how do you know this before you design your stackup and build your first prototype? Since we do not have any empirical data to go by, we can rely on a heuristic, high-level design (HLD) modeling method starting with published parameters found solely in manufacturer’s data sheets.

Heuristic HLD modeling is a practical technique that is not guaranteed to be perfect, but is still adequate in finding a satisfactory solution sooner, rather than later.

For dielectric parameters, we choose dielectric constant (Dk) / dissipation factor (Df) at or near the Nyquist frequency of the baud rate, then apply effective Dk (Dkeff) correction factor due to roughness, Equation 1 [5].

Equation 1



H = thickness of core/prepreg; Rz is surface roughness of copper; Dk is as published in laminate supplier’s Dk/Df tables. Equation 1 assumes Rz of the foil on each side of the dielectric (core or prepreg) is the same.

For conductor loss, we use Rz roughness numbers from copper suppliers’ data sheets and oxide/oxide alternative Rz roughness numbers from your favorite fab shop, then apply the Cannonball-Huray roughness model [1]-[3].

Cannonball-Huray Model

The original Huray model is defined as:

Equation 2


The Cannonball-Huray model allows you to extract the right parameters using Rz roughness for core and prepreg sides of the foil [1]. Because the Cannonball-Huray model assumes the ratio of Amatte/Aflat = 1, and Ni = 14 spheres, the radius of a sphere (r) can be determined by:

Equation 3


and area of flat tile base (Aflat) by:

Equation 4


Wildriver Isola I-Tera® MT40 Custom Modeling Platform Case Study

To study the effect of reference plane roughness on transmission insertion loss, Wildriver Technology’s [7] custom modeling platform (CMP), shown in Figure 2, was used as a case study. This CMP was custom developed for Isola [6] to characterize their new I-Tera® MT40 very low-loss laminate material.

It combines 27 structures based on a consistent development of primitive structures; useful for performing a host of calibrations including automatic fixture removal, unknown THRU, WinCal XE™ calibration, and VNA gating and time transform analysis.


Figure 2 Wildriver Isola I-Tera® MT40 Custom Modeling Platform. Source: Wildriver Technology [7]

Stackup Validation

The PCB stackup is shown in Figure 3. Often PCB fab shop field application engineers (FAE) modify existing stackups and unintentionally make errors in transferring new parameters from data sheets into their software tools. Also, they may not necessarily know the design intent of the stackup. So the first step for any model correlation exercise is to sanitize the stackup, to ensure it meets the product design intent for signal integrity (SI) performance. In fact that is how the issue of different plane roughness was uncovered.

Since it is always a good practice to ensure the same roughness is specified for reference planes as the adjacent signal layers, I naively assumed it would be the case for any high-speed stackup. But that wasn’t the case here. Layers E1,E2 and E7, E8 specify 1oz RTF, while layers E3, E4 and E5, E6 specify 1oz VLP2 foil. Because the Isola I-Tera® MT40 CMP is intended to aid in modeling test structures, this is not a fatal flaw. On the contrary, it is a perfect platform to assess the effect of rougher reference planes.


Figure 3 Isola I-Tera® MT40 Custom Modeling Platform stackup. Source: Wildriver Technology [7]

Upon further review, it was discovered that the core laminates between E3,E4 and E5, E6 specified 1067/2×3313 glass styles, but this combination was not listed for 12 mil thickness. Instead, only 3×3313 core is offered. Because of that, the Dk shown is also wrong and will affect the impedance of the traces. The right Dk for 3×3313 is 3.53 instead if 3.33.

Foil Roughness

As mentioned earlier, the roughness of the foil affects the effective Dk, so we need to use the right number for our model validation. The standard VLP2 foil, used on I-Tera® MT40 core laminates is BF-TZA foil. Optional RTF foil, used for layers E1, E2 and E7, E8, is TWLS-B. Both are from Circuit Foil [8].

Relevant roughness parameters are shown in Figure 4. For the core side of the foil we are interested in the Rz parameters for the treated side listed in the table. But there are two Rz parameters, JIS B 601 and ISO 4287 specified. So which one do we use for modeling?

From IPC-TM-650 Section 1.2 [11] states, “The foil profile of foils shall be evaluated using the parameter Rz (DIN) or RTM, which is defined as the average maximum peak to valley height of five consecutive sampling lengths within the measurement length. This value is approximately equivalent to the values of profile determined from microsectioning techniques.


Section 1.3 states, “RZ (ISO) is a different parameter from Rz (DIN) and is not applicable to this method.

Rz JIS represents the 10-point mean value, which is the sum of the average of the 5 highest peaks and the 5 lowest valleys over the sample length. Rz DIN is similar; except it is defined as the average maximum peak to valley height of five consecutive sampling lengths within the measurement length. Thus we will use Rz JIS for modeling analysis.


Figure 4 Roughness parameters from Circuit Foil [8] data sheets. Top is VLP2 standard foil used on I-Tera® MT40, while bottom is RTF option used for relevant layers in the stackup

Determine Effective Dk Due to Roughness

The first step in HLD impedance modeling is to gather all the dielectric and foil data sheet parameters to determine the effective Dk.

Figure 5 summarizes thickness of core, prepreg and signal trace from the stackup geometry in Figure 3. Note that photos are for illustrative purposes only and are not actual cross-sections from CMP PCB. Dk for core and prepreg were obtained from Isola I-Tera® MT40 Dk/Df tables [6].


Figure 5 Data sheet parameters for RTF/VLP2 foil roughness and dielectric properties for I-Tera® MT40 stackup geometry. Note: Photos are for illustrative purposes only and are not actual cross-sections from CMP PCB. Surface roughness pictures source: Circuit Foil [8]

The top reference plane is TWLS-B RTF foil with matte side 1 ≤ 7.5 JIS, obtained from Circuit Foil data sheet (Figure 4). The roughness surface profile is shown in the upper left. After OA smoothing, 1 ≤ 6.23 [1].

BF-TZA foil is used for both sides of the core laminate. The top surface of the stripline trace, shown in the upper right picture, is the drum side of the foil, before OA treatment. After OA treatment, Rz2 ~ 1.9 μm [1].

The bottom surface profile of the stripline trace and the top surface of the bottom reference plane are the treated matte sides of the foil, shown in the bottom right and bottom left pictures respectively. They both share the same roughness (Rz3, Rz4 =2.5μm JIS) from the BF-TZA data sheet (Figure 4).

The next step is to convert the imperial thickness units to metric, then use Equation 1 to determine Dkeff due to roughness for the prepreg and core.


Determine Cannonball-Huray Roughness Parameters

Several popular electronic design automation (EDA) tools include the Cannonball-Huray model directly as an option, so the respective Rz parameter is all that is needed.

Any of these tools can be used for HLD modeling, but my favorite is Polar SI9000 [9] because of its simplicity and sufficient accuracy for prefabrication modeling and analysis. Many fab shops use this tool for impedance prediction, so it is easy to stay in sync with them during the HLD stage of your project. Plus, it has the added benefit of modeling transmission loss and exporting S-parameters in touchstone format for further channel modeling in other tools.

Because Polar Si9000 assumes all the reference planes have the same roughness, it only allows Rz roughness parameters to be inputted for the matte and drum side of the signal trace. The best we can do, is take the average roughness of Rz1,Rz2 and Rz3,Rz4:


Simulation Correlation

When Dkeff due to roughness values were used instead of published Dk values, the new impedance prediction is 48.24 ohms, as shown in Figure 6.


Figure 6 Polar Si9000 impedance prediction with Dkeff due to roughness

Dkeff/Df for H1, H2 was then inputted into the causal dielectric model at 10GHz, as shown in Figure 7 (left), while Rzmatte, Rzdrum was inputted into the Cannonball-Huray model (right).


Figure 7 Causal Dkeff/Df dielectric and Cannonball-Huray roughness model input panels in Polar Si9000

After a 6-inch transmission line was simulated, the S-parameters were exported in touchstone format. Keysight Pathwave ADS [10] was used for further processing and analysis.

Figure 6 compares simulated insertion loss vs de-embedded reflectionless generalized modal (GM) S-parameter measurements, provided by Wildriver Technology [7]. As you can see there is excellent correlation without fitting to measured data!


Figure 8 HLD Insertion Loss simulation correlation for as designed stackup from data sheet and stackup parameters

Figure 9 plots simulated Dkeff vs measurements. At 10 GHz, simulated Dkeff is 0.105 (-2.8%) lower than measured value. Without actual cross-section microscopic measurements, it is difficult to conclude if the published Dk is wrong, or if there is process variation with roughness parameters used in the model.

But it is also interesting to note that measured Dkeff is not a constant value over frequency, as shown in the I-Tera® MT-40 Dk/Df tables. Instead Figure 9 reveals it varies over frequency, so the Dk/Df data sheet numbers are suspect.

Regardless, for the HLD modeling process, the simulation results are within acceptable tolerance.


Figure 9 HLD Dkeff simulation correlation for as designed stackup

Exploring the Effects of Alternate Foil Roughness

Now that we have good correlation to measurements, we can repeat the HLD modeling process to explore different foil roughness options. Figure 10 summarizes the thickness of core, prepreg and signal trace for VLP2/VLP2 foil (top) and VLP1/VLP1 foil (bottom). Note that photos are for illustrative purposes only and are not actual cross-sections from CMP PCB.

Respective Dkeff, and Cannonball-Huray roughness parameters were recalculated with same steps as VLP2/RTF case above.


Figure 10 Alternate foil options simulated for what-if loss comparison. Top is VLP2/VLP2 foil parameters for all copper layers and bottom is VLP1/VLP1 foil parameters for all copper layers. Note: Photos are for illustrative purposes only and are not actual cross-section from CMP PCB. Surface roughness pictures source: Circuit Foil [8]

Figure 11 presents the simulation results of all three scenarios. As expected. when the reference plane foil roughness went from RTF/VLP2 to VLP2/VLP2 there was improvement. At 14 GHz it was 0.5 dB and at 28GHz it was 1 dB improvement.

When VLP1/VLP1 foil was used, it was further improved by 0.8 dB and 1.7 dB at 14 GHz and 28 GHz respectively. So if your design is loss sensitive, you might want to consider VLP1 foil option.

When we compare Dkeff plots, we see effective Dk approaches actual Dk/Df data sheet values in the tables when smoother copper is used, as expected [5].

Since Dkeff was derived by phase delay, propagation delay will be affected by rougher copper.


Figure 11 What-if simulation comparison of VLP2/RTF, VLP2/VLP2, VLP1/VLP1 foil options and their effect on insertion loss and Dkeff


1. Roughness of reference planes make a significant difference in loss and phase delay, especially if one of the reference planes is RTF. If loss is important then all high-speed reference planes should have the same foil roughness specified

2. Heuristic HLD modeling method is a useful and accurate way to determine prefabrication impedance and loss predictions using data sheet parameters.

3. Published Dk from I-Tera® MT40 Dk/Df data sheet tables is not a flat constant over frequency.

4. Confirmed Rz JIS is the right parameter to use from Circuit Foil data sheet, instead of Rz ISO.


· Al Neves, CTO Wildriver Technology, for providing the custom modeling platform design details and measured data for the case study.

· Michael Gay, Director Business Development – Strategic Accounts at Isola Group, for providing foil supplier’s data sheets used on I-Tera® MT40 laminates.


[1] B. Simonovich, Heuristic Modeling of Transmission Lines due to Mixed Reference Plane Foil Roughness in Printed Circuit Board Stackups”, White Paper, Lamsim Enterprises Inc.

[2] B. Simonovich, “Practical Method for Modeling Conductor Surface Roughness Using The Cannonball Stack Principle”, White Paper, Lamsim Enterprises Inc.

[3] L. Simonovich, “Practical method for modeling conductor roughness using cubic close-packing of equal spheres,” 2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), 2016, pp. 917-920, doi: 10.1109/ISEMC.2016.7571773.

[4] L. Simonovich,  “PCB Interconnect Modeling Demystified”, DesignCon 2019, Proceedings, Santa Clara, CA, 2019

[5] B. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”. DesignCon 2017, Proceedings, Santa Clara, CA, 2017

[6] Isola Group S.a.r.l., 3100 West Ray Road, Suite 301, Chandler, AZ 85226, URL:

[7] Wild River Technology LLC 8311SW Charlotte Drive Beaverton, OR 97007, URL:

[8] Circuit Foil 6 Salzbaach, 9559 Wiltz, Grand Duchy of Luxembourg URL:

[9] Polar Instruments Si9000e [computer software] Version 2018, URL:

[10] Keysight Pathwave Advanced Design System (ADS) [computer software], (Version 2021 update2). URL:

[11] IPC-TM-650 Test Methods Manual 2.2.17A, Surface Roughness and Profile of Metallic Foils (Contacting Stylus Technique), 2/2001 Rev. A

[12] IPC-TM-650,, Rev C, Test Methods Manual

Written by Bert Simonovich

September 5, 2021 at 4:34 pm

Characteristic Impedance – Where SI/PI Worlds Collide

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Originally published Signal Integrity Journal, February 23, 2021

Signal and power integrity (SI/PI) simulations, measurements, and analysis usually live in two different worlds, but occasionally these worlds collide. One such collision occurs when we refer to characteristic impedance, Z0. Traditionally the PI world lives in the frequency domain while the SI world lives in the time domain.

When designing a power distribution network (PDN) in the PI world, we are mostly interested in engineering a flat impedance below a target impedance from DC to the highest frequency components of the transient current. Practically this is achieved with a network of capacitors with different values connected to the respective power planes as shown in Figure 1.


Figure 1 A simplified model of a typical PDN courtesy [1].

In the real world, there is no such thing as an ideal capacitor. There are always parasitic elements known as equivalent series inductance (ESL) and equivalent series resistance (ESR). Physical characteristics of the PCB, like component mounting inductance, plane spreading inductance, via and BGA ball inductance, along with voltage regulator module (VRM) characteristics also contribute to the impedance profile. When connected together, the interaction of capacitors and parasitic inductance and resistance create a transfer impedance profile with resonant peaks and anti-resonant nulls as shown in Figure 2.

The transfer impedance between the VRM and the load is calculated and plotted in the frequency domain with a log-log scale. The resulted impedance curve is then compared to the target impedance (Ztarget), which is estimated based on the allowed noise ripple and maximum transient current. The flat target impedance is frequency independent in the analysis.


Figure 2 Impedance profile of the PDN as viewed from the pads on the die power rail courtesy [1].

Resonant peaks are due to ESL of one capacitor connected in parallel with another capacitor. Anti-resonant nulls are due to the series combination of ESR, ESL, and C for each capacitor. Different capacitor values will have anti-resonant nulls at different frequencies.

But in the PI world, there is a rarely talked about characteristic impedance, Z0. In this case, it refers to the geometric average of the reactive impedance of a capacitor (XC) and reactive impedance of an inductor (XL).

Equation 1


At resonance, XL and XC intersect at the characteristic impedance and are equal as shown in Figure 3.


Figure 3 Inductive and capacitive reactance plot of ideal inductor and capacitor versus frequency. At resonance, XL and XC are equal and intersect at the characteristic impedance, Z0. Simulated with Pathwave ADS [6].

This is a very important observation, and it is where the SI/PI worlds collide.

In the SI world, characteristic impedance, Z0 refers to the instantaneous ratio of the voltage to current of a wave front traveling along a uniform transmission line without reflections. For an infinitely long uniform transmission line, Z0 equals the input impedance.

The characteristic impedance of a lossy transmission line is defined as:

Equation 2


Where R is resistance per unit length; G is conductance per unit length; L is inductance per unit length; and C is capacitance per unit length. For a lossless uniform transmission line, R and G are assumed to be zero and thus the characteristic impedance is reduced to:

Equation 3


Time Domain Reflectometer

In the SI world, we usually use a time domain reflectometer (TDR) to measure characteristic impedance, but more often than not, the measured impedance we get is not what we predicted with a 2D field solver. Many 2D field solvers used by most PCB FAB shops only calculate the lossless characteristic impedance of the cross-sectional geometry at a single frequency, defined by the dielectric constant (Dk). It has no input for conductor resistivity, dielectric loss, or how long the conductor(s) is.

So the issue is: we design the stackup, then do our SI modeling analysis based on stackup parameters and matching characteristic impedance. But the PCB FAB shop will often adjust the line width(s), over and above normal process variation, so that when measured, the impedance will fall within the specified tolerance, usually +/-10 percent.  

Part of the problem lies with the method used to take the measurements. Most PCB FAB shops follow IPC-TM-650 Test Methods Manual [2]. But it has limitations because Z0 measured is derived and cannot be directly measured. The reason is the measurements include resistive and dielectric losses, up to the point where the measurement takes place along the TDR plot.

Resistive loss often results in a slow monotonic rise in the impedance profile, shown in the example TDR plot of Figure 4. IPC-TM-650 specifies a measurement zone between 30-70 percent to avoid probing induced ringing affecting the measurements. Most PCB FAB shops will measure an average impedance over this range, usually in the center region.

Depending on the linewidth, thickness and dielectric dissipation factor (Df), the slope of the monotonic rise will vary.


Figure 4 Example TDR plot showing slow monotonic rise in impedance due to resistive losses and IPC-TM-650 measurement zone.

The problem is that the IPC-TM-650 test method was last updated back in 2004, when higher dielectric loss, along with wider line widths and thicker copper weights, were used more often. A higher Df tends to compensate for resistive loss by flattening the slope as shown in Figure 5.

On the bottom left is a simulated TDR plot using a high loss dielectric with Df = 0.024. The right side has the exact same geometry properties except Df = 0.004. The average impedance, when measured at the 50 percent point, is 49.8 Ohms on the left side vs. 51.4 Ohms on the right side. We also confirm flatter slope for high loss material.

The actual characteristic impedance predicted by a Polar SI9000 2D field solver [5] in Figure 5 is 49 Ohms. For higher loss material, measuring within the measurement zone would pass without any issues. But for lower loss material, the resistive loss dominates and measuring within the measurement zone will give ~5 percent higher impedance reading compared to the higher loss material. The correct measurement point for Z0 is, in fact, the initial dip, equivalent to the field solver prediction. Depending on the tolerance specified, this may affect yield and cost.


Figure 5 Characteristic impedance prediction by Polar SI9000 2D field solver [5] (top). Simulated 2 inch TDR plots using a high loss dielectric (bottom left) vs. low loss dielectric with exactly the same geometry (bottm right). A higher Df compensates for higher resistive loss thereby flattening the curve. Simulated with Pathwave ADS [6].

Today, with the push to low loss dielectric and finer line widths with thinner copper weights, measuring the true transmission line characteristic impedance using a TDR becomes more challenging. This is even more so when measuring differential impedance, because a change in line width space geometry can have a more profound effect on measured differential impedance.

Using the first article build of a new design, as an example, let’s assume the correct characteristic impedance, when measured at the beginning of the slow monotonic rise of a TDR plot, is on the high end of nominal +10 percent tolerance. Let’s say it’s 54 Ohms.  But because of the low loss dielectric and high resistive loss, the TDR measurement at the midpoint is now reading 5% higher at 57 Ohms. This would imply the impedance is now out of spec over nominal and the board would be scrapped.

The PCB fab shop will then go back and adjust the linewidth accordingly for the next build to bring the measurement within range to their measurement set up. Doing this effectively lowers the true nominal characteristic impedance!

If subsequent manufacturing variations pushes the measured impedance within the measurement zone on the low end of the -10 percent tolerance, say 44 Ohms, then the true characteristic impedance, if measured at the initial dip, will be 5 percent lower at 42 Ohms and be out of spec. But the board will pass because it was measured following IPC-TM-650 test method.   

2-port Shunt Measurement

But what if there were another way? What if we could borrow impedance measuring techniques from the PI world to determine the true transmission line characteristic impedance in the SI world?  Well there is. Enter the 2-port shunt measurement technique.

For example, in the PI world, to measure ESL and ESR of a chip capacitor, of a device under test (DUT), a 2-port shunt measurement is often used. It is much like the 4-point Kelvin measurement technique used to measure very low DC resistance.

The 2-port shunt measurement is usually done with a 2-port vector network analyzer (VNA). Port 1 of the VNA sends out a calibrated signal, and port 2 measures the voltage signal across the DUT. Often an isolation transformer is also used to break the inherent ground loop when measuring ultra-low impedances [3].

Once the measurements have been completed and S-parameters saved in touchstone format, further analysis can be done in your favorite SPICE simulator. Figure 6 is a generic schematic using popular Pathwave ADS [5] that can be used for 2-port shunt analysis.

When port 1 and port 2 are connected to port 1 of the DUT and port 2 of the DUT is grounded, the impedance of the DUT can be determined by [3];

Equation 4



Figure 6 Generic Pathwave ADS [6] schematic used for 2-port shunt analysis on a S2P file for DUT.

If we replace the DUT in Figure 6 with a capacitor and inductor, we get an impedance plot shown in Figure 7.  As we saw earlier, when we take the geometric average of the inductive and capacitive reactance using Equation 1, we get the characteristic impedance. If we apply Equation 4 to the results of a 2-port shunt measurements of a capacitor and inductor, we get exactly the same results as shown in the top of Figure 7.

When we replace the capacitor and inductor with a S-parameter file of a transmission line model from Figure 5, we get the plot shown at the bottom of Figure 7. Except for the resonant nulls and peaks, up to a certain frequency, the impedance of a transmission line looks like the impedance of a capacitor when the far-end is open, and looks like the impedance of an inductor when the far-end is shorted. And because of that, this is where the two worlds collide!

If we take the geometric average of the impedance when the far-end is open (Zopen) or shorted (Zshort), we get the characteristic impedance at that frequency. We note where the red and blue impedance lines first intersect, is exactly the geometric average characteristic impedance at that frequency.

Also worth noting, the lines intersect at half of the frequency between the peaks and valleys at higher frequencies as well.


Figure 7 Impedance of inductive and capacitive reactance vs. frequency (top) and impedance of a transmission line vs. frequency (bottom) when the far-end is open (solid red) compared to when the far-end is shorted (solid blue). The intersection of the red and blue lines is exactly the characteristic impedance. Simulated with Pathwave ADS [5].

We can see this more clearly if we replot Figure 7 bottom using a linear scale for the x-axis, as shown in Figure 8. This is a very powerful observation. What this means is that when we measure the impedance half way between a peak and adjacent valley, of either the red or blue plot, it is the characteristic impedance of the transmission line at that frequency.

Thus, only an open or shorted end measurement is all that is needed to determine the characteristic impedance. For example, if we look at the red curve alone, then measure the first resonant null (m14) and adjacent peak (m15), the characteristic impedance (mag(Zopen) is measured exactly at one half the frequency between the two (m16). 


Figure 8 Impedance of a transmission line vs. frequency on a linear scale when the far-end is open (solid red) compared to when the far-end is shorted (solid blue). The intersection of the red and blue lines half way between respective peaks and valleys is the characteristic impedance. Simulated with Pathwave ADS [6].

The first resonant red null and blue peak represent the quarter-wave resonant frequency due to open and shorted end. Each respective red null and blue peak following are the odd harmonics of the first quarter-wave resonant frequency.

Knowing this, we can now determine the phase or time delay (TD) of the transmission line as being one quarter of the period of the resonant frequency (f0).

Equation 5


Because resonant nulls and peaks occur at the resonant frequency, we can also determine the effective dielectric constant (Dkeff). Given the speed of light (c) = 11.8 in. per nanosecond, the length of the transmission line (len) in in. and quarter-wave resonant frequency (f0), Dkeff can be determined by:

Equation 6


CMP28 Case Study


Figure 9 Photo of a portion of CMP-28 test platform courtesy of Wildriver Technology [8] used for measurement validation.

To test the accuracy of this method, measured data from a CMP28 test platform, shown in Figure 9, was used for measurement validation. S-parameter (s2p) files from 2 inch and 8 inch single-ended stripline traces were provided as part of CMP-28 design kit courtesy of Wildriver Technologies [8]. The 6-inch transmission line segment S-parameter data was de-embedded courtesy of AtaiTec Corporation [9].

The characteristic impedance, based on trace geometry and stackup parameters, was modeled in Polar SI9000 [5]. Using Dk from data sheet tables @ 10GHz, and correcting for conductor roughness [10], the characteristic impedance predicted was 49.66 Ohms, as shown in Figure 10.


Figure 10 Polar SI9000 field-solver [5] characteristic impedance prediction of CMP28 trace geometry.

Touchstone S-parameter DUT files were connected with far-end open, shorted, and terminated as shown in Figure 11. The TDR plot, with far-end terminated, shows an impedance of 50.57 Ohms, when measured at the initial peak. Then it takes an immediate dip to approximately 50 Ohms before continuing with a slow monotonic rise with some ripples. If the DUT was a uniform trace, with connector discontinuity de-embedded, we would not see the initial peak followed by the dip.  This signature strongly suggests that the DUT is not uniform and thus it is very difficult to determine the actual characteristic impedance using IPC-TM-650 test method alone. 

But only after taking 2-port shunt measurements can we confirm the true characteristic impedance. As shown, Zoavg is 50.68 Ohms where the red and blue curves cross at 122.5 MHz, and confirms the true measurement point in the TDR plot is the initial peak. Both are about 1 Ohm higher compared with 2-D field solver results in Figure 10.

If the length of the transmission line simulated above is 6 in. and f0 =248.2 MHz, then TD = 1 ns and Dkeff = 3.92, using Equation 5 and Equation 6 respectively.


Figure 11 Measured results from a CMP28 test platform design kit, courtesy of Wildriver Technology [8].

But wait a minute. Why is Dkeff is higher than what was used in the 2-D field solver in Figure 10?

One reason is due to process variation of the material and fabrication. The actual Dkeff is determined by the final thickness of dielectric and the roughness of the copper, which also increases inductance affecting TD [10] [11]. But the main reason is Dk is frequency dependent and the value used in the field solver was at 10 GHz, based on laminate supplier’s Dk/Df tables.

Since TD, ultimately determines Dkeff, it does not represent the intrinsic property of the dielectric material. Because Dkeff varies with frequency, it was calculated at the first resonant null of 248.2 MHz, which is at a much lower frequency for Dk than the frequency originally used to select Dk in the field solver.

As can be seen in Figure 12, a simulated vs. measured 2-port shunt frequency plot, with far-end open and shorted, we get exactly the same information, compared to the traditional method used to validate characteristic impedance and Dkeff.

If we measure the 39th odd harmonic frequency (H) at 9.884GHz for the resonant null closest to 10GHz, equating to the value of Dk used in Polar Si9000 2D field solver, Dkeff can be calculated with Equation 7:

Equation 7


The bottom right plot of Figure 12, shows Dkeff simulated (blue) vs. measured (red). As we can see, the measured Dkeff at 248.7 MHz is 3.94; pretty much agreeing with our earlier calculation of 3.92 using Equation 6. Furthermore, when we compare Dkeff = 3.76 at 9.884 GHz, it agrees with our calculation for the 39th harmonic frequency from Equation 7. The reason there is still a slight difference in Dkeff is because the added delay due to inductance due to roughness [11] was not factored into the simulated model.

The bottom left is a TDR plot that shows measured impedance (red) vs. simulated (blue) over time. The marker at the beginning of the initial dip (m6) represents the characteristic impedance with highest frequency harmonics included in the incident step edge of TDR waveform. The marker at the end (m16) represents the impedance at twice the TD with high frequency harmonics attenuated due to dispersion of the lossy dielectric and resistance of trace length.

When we measure Zoavg_meas impedance of DUT at 9.884GHz, at the top plot of Figure 12, it agrees pretty well with the simulated and measured TDR plot at the initial step.


Figure 12 Comparison of PI world 2-port shunt measurement results for transmission line characteristic impedance and Dkeff compared to traditional SI world measurement results. Top plot is the 2-port shunt simulated vs. DUT impedance measurements at the fundamental and 39th harmonic frequencies. Bottom left is beginning and end impedance measurements on TDR plot. Bottom right measuring equivalent Dkeff at fundamental and 39th harmonic frequencies.  

Summary and Conclusion

Sometimes, when SI and PI worlds collide, we get the best of both worlds. By borrowing a simple 2-port shunt impedance measuring technique from the PI world, we have another tool at our disposal to measure true characteristic impedance, TD, and effective Dk from a uniformly designed transmission line in the SI world. The advantage is, unlike a TDR measurement, measuring true characteristic impedance using 2-port shunt method is not influenced by resistive or dielectric losses.


  1. L. Smith, S. Sandler, E. Bogatin, “Target Impedance Is Not Enough,” Signal Integrity Journal, Vol. 1, Issue 1, January 2019; URL:
  2. IPC-TM-650 Test methods Manual, Number, “Characteristic Impedance of Lines on Printed Boards by TDR”, Rev. A, March, 2004
  3. I. Novak, J. Millar, “Frequency-Domain Characterization of Power Distribution Networks,” Artech House, 685 Canton St., Norwood, MA, 02062, 2007.
  4. Pathwave Advanced Design System (ADS) [computer software], Version 2021, URL:
  5. Polar Instruments Si9000e [computer software], Version 2018, URL:
  6. Keysight Pathwave Advanced Design System (ADS) [computer software], Version 2021, URL:
  7. E. Bogatin, “Bogatin’s Practical Guide to Transmission Line Design and Characterization for Signal Integrity”, Artech House, 685 Canton St., Norwood, MA, 02062, 2020
  8. Wild River Technology LLC 8311 SW Charlotte Drive Beaverton, OR 97007. URL:
  9. AtaiTec Corporation, URL:
  10. V. Dmitriev-Zdorov, B. Simonovich, I. Kochikov, “A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics”, DesignCon 2018 proceedings, Santa Clara, CA.
  11. I. Novak et al, “Determining PCB Trace Impedance by TDR: Challenges and Possible Solutions”, DesignCon 2013 proceedings, Santa Clara, CA.
  12. S. Sandler, “Easy trick to measure plane impedance with VNA”, EDN Asia, 2014, URL:

Written by Bert Simonovich

May 2, 2021 at 4:24 pm

Single-ended to Mixed-Mode Conversions

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Originally published in Signal Integrity Journal Magazine, July 2020

Signal Integrity (SI) engineers almost always have to work with S-parameters. If you haven’t had to work with them yet, then chances are you will sometime in your SI career. As speed moves up in the double-digit GB/s regime, many industry standards are moving to serial link-based architectures and are using frequency domain compliance limits based on S-parameter measurements.

A vector network analyzer (VNA) is the test instrument of choice to measure S-parameters from a device under test (DUT). By definition, each S-parameter (Sij) is the ratio of the sine wave voltage coming out of a port to the sine wave voltage that was going in to a port (Equation 1). Each S-parameter is complex with a magnitude and a phase.

Equation 1


Sufficed to say, for mathematical reasons, the indexes refer to the port in which the voltages are coming or going. This is counter intuitive to our normal train of thought and is important to be cognisant of this relationship when working with S-parameters.

Single-ended S-parameters

Figure 1 shows an example of a 1-Port, 2-Port and 4-Port DUTs and their respective S-parameter matrices representing uniform transmission lines with respective port index labelling. Each S-parameter in the matrix are single-ended measurements from one port to another.

A 1-Port DUT has one S-parameter (S11) shown in red. It is the ratio of the voltage coming out of Port 1 to the voltage going into Port 1. As a measure of reflected energy out of Port 1, it is also known as return loss (RL)

A 2-Port DUT has 4 S-parameters shown in blue. S-parameters with the same index subscript numbers, i.e. S11, S22 are RL. S-parameters with alternate index subscript numbers, are a measure of transmitted energy and is the ratio of the voltage coming out of a Port to the voltage going into the opposite Port. It is also known as insertion loss (IL). For example, S12 is the ratio of the voltage coming out of Port 1 to the voltage going into Port 2, whereas S21 is the ratio of the voltage coming out of Port 2 to the voltage going into Port 1.


Figure 1 From left to right examples of 1-Port (Red), 2-Port (Blue), 4-Port (Black) DUTs and their respective S-parameter matrices.

A 4-Port DUT has 16 S-parameters, divided into 4 quadrants, shown in black. As you can see the number of S-parameter combinations is the square of the number of ports. In this example, the top left quadrant 1 and bottom right quadrant 4 are the same as individual 2-Port DUTs with different port indices. They are described as:

Quadrant 1:

  • S11 is the ratio of the voltage coming out of Port 1 to the voltage going into Port 1. It is the RL out of Port 1.
  • S12 is the IL and is the ratio of the voltage coming out of Port 1 to the voltage going into Port 2. It is the IL from Port 2 to Port 1.
  • S21 is the ratio of the voltage coming out of Port 2 to the voltage going into Port 1. It is the IL from Port 1 to Port 2. For a uniform transmission line, S21 = S12.
  • S22 is the ratio of the voltage coming out of Port 2 to the voltage going into Port 2. It is the RL out of Port 2. For a uniform transmission line, S22 = S11.

Quadrant 4:

  • S33 is the ratio of the voltage coming out of Port 3 to the voltage going into Port 3. It is the RL out of Port 3
  • S34 is the ratio of the voltage coming out of Port 3 to the voltage going into Port 4. It is the IL from Port 4 to Port 3
  • S43 is the ratio of the voltage coming out of Port 4 to the voltage going into Port 3. It is the IL from Port 3 to Port 4. For a uniform transmission line, S43 = S34.
  • S44 is the ratio of the voltage coming out of Port 4 to the voltage going into Port 4. It is the RL out of Port 4. For a uniform transmission line, S44 = S33

S-parameters in the top right quadrant 2 and bottom left quadrant 3 describe the near-end and far-end coupling of the respective ports. When unwanted coupling happens at the near-end, it is referred to as near-end cross talk, or NEXT. When it happens at the far-end, it is known as far-end crosstalk, or FEXT.

Quadrant 2:

  • S13 is the ratio of the voltage coming out of Port 1 to the voltage going into Port 3. It is the coupling or NEXT from Port 3 to Port 1.
  • S14 is the ratio of the voltage coming out of Port 1 to the voltage going into Port 4. It is coupling or FEXT from Port 4 to Port 1.
  • S23 is the ratio of the voltage coming out of Port 2 to the voltage going into Port 3. It is coupling or FEXT from Port 3 to Port 2.
  • S24 is the ratio of the voltage coming out of Port 2 to the voltage going into Port 4. It is coupling or NEXT from Port 4 to Port 2.

Quadrant 3:

  • S31 is the ratio of the voltage coming out of Port 3 to the voltage going into Port 1. It is the coupling or NEXT from Port 1 to Port 3.
  • S32 is the ratio of the voltage coming out of Port 3 to the voltage going into Port 2. It is coupling or FEXT from Port 2 to Port 3.
  • S41 is the ratio of the voltage coming out of Port 4 to the voltage going into Port 1. It is coupling or FEXT from Port 1 to Port 4.
  • S42 is the ratio of the voltage coming out of Port 4 to the voltage going into Port 2. It is coupling or NEXT from Port 2 to Port 4.

Although there is no industry standard for labeling a 4 or more port DUT, a practical way is to use the port order shown so that the 2-Port DUT is a subset of the top left quadrant of the 4-Port DUT. When you do this, the port order labeling is consistent as you increase the number of ports; with odd ports on the left and even ports on the right. S12 and S21 always describe the IL terms; while S13 and S31 define the NEXT terms.

But sometimes 3rd party 4-port S-parameters are labeled with ports 1 and 2 are on the left side, while ports 3 and 4 are on the right side. In this configuration, S31 and S42 are now the IL terms. This is counter intuitive when moving from 2-Port to 4 or more Port DUT and leading to potential confusion when cascading S-parameters to build a channel model, or converting to mixed-mode S-parameters. Whenever you get S-parameter files from 3rd party, it is always prudent to test it and compare IL plots against port order to ensure you are using them correctly.

Typically, 4-port S-parameters are saved in Touchstone format with a .snp extension, where n is the number of ports. Many Electronic Design Automation (EDA) and circuit simulation software tools allows you to view and plot S-parameters from Touchstone files.

Figure 2 is a schematic of a 4-port S-parameter component used in Keysight ADS. When the component is linked to appropriate .s4p touchstone file and ports connected as shown, the 16-port S-parameter matrix can be plotted and analyzed.


Figure 2 Keysight ADS schematic used to plot 4-Port single-ended S-parameters.

The 1-port and 2-port S-parameters are included in the same plot as the 4-port S-parameters plotted in Figure 3. The top left (red) and bottom right (green) quadrants plot the return loss (RL) and insertion loss (IL), while the top right (blue) and bottom left (magenta) quadrants plot the NEXT and FEXT.


Figure 3 An example of 4-Port S-parameter single-ended plots of a uniform transmission line.

Mixed-mode S-parameters

SI engineers often have to check channel models and S-parameter measurements against industry standard compliance plots. Many of those plots are in terms of mixed-mode S-parameters, which means the single-ended measurements need to be converted to mixed-mode matrix.

Two single-ended transmission lines with coupling are also known as a differential pair, as shown in Figure 4. When we talk about single-ended transmission lines with coupling, we are usually interested in their single-ended properties like characteristic impedance (Zo), phase delay, and NEXT/FEXT relationships as described above.

But when we talk about a differential pair, we are interested in the mixed-mode S-parameters like differential and common signals and how they interact within the pair. Because we are describing the exact same interconnect, they are equivalent.

When describing a differential pair, there are only four possible outcomes in response to an input signal as defined by the mixed-mode S-parameter matrix:

  • A differential signal enters the differential pair and a differential signal comes out
  • A differential signal enters the differential pair and a common signal comes out
  • A common signal enters the differential pair and a differential signal comes out
  • A common signal enters the differential pair and a common signal comes out


Figure 4 Single-ended vs mixed-mode S-parameter matrices of two coupled transmission lines.

Mixed-mode S-parameters in each quadrant are described as:

SDD Quadrant (Red):

  • SDD11 is the ratio of the differential signal coming out of Port 1 to the differential signal going into Port 1. It is the differential RL out of Port 1.
  • SDD12 is the ratio of the differential signal coming out of Port 1 to the differential signal going into Port 2. It is the differential IL from Port 2 to Port 1.
  • SDD21 is the ratio of the differential signal coming out of Port 2 to the differential signal going into Port 1. It is the differential IL from Port 1 to Port 2.
  • SDD22 is the ratio of the differential signal coming out of Port 2 to the differential signal going into Port 2. It is the differential RL out of Port 2.

    SDC Quadrant (Blue):

    • SDC11 is the ratio of the differential signal coming out of Port 1 to the common signal going into Port 1.
    • SDC12 is the ratio of the differential signal coming out of Port 1 to the common signal going into Port 2.
    • SDC21 is the ratio of the differential signal coming out of Port 2 to the common signal going into Port 1.
    • SDC22 is the ratio of the differential signal coming out of Port 2 to the common signal going into Port 2.

    SCD Quadrant (Magenta):

    • SCD11 is the ratio of the common signal coming out of Port 1 to the differential signal going into Port 1.
    • SCD12 is the ratio of the common signal coming out of Port 1 to the differential signal going into Port 2.
    • SCD21 is the ratio of the common signal coming out of Port 2 to the differential signal going into Port 1.
    • SCD22 is the ratio of the common signal coming out of Port 2 to the differential signal going into Port 2.

    SCC Quadrant (Green):

    • SCC11 is the ratio of the common signal coming out of Port 1 to the common signal going into Port 1.
    • SCC12 is the ratio of the common signal coming out of Port 1 to the common signal going into Port 2.
    • SCC21 is the ratio of the common signal coming out of Port 2 to the common signal going into Port 1.
    • SCC22 is the ratio of the common signal coming out of Port 2 to the common signal going into Port 2.

    Single-ended S-parameters, with port order shown in Figure 4, can be mathematically converted into mixed-mode S-parameters using equations shown in Table 1.


    Alternatively, Keysight ADS can simplify this process using equations on 4-Port single-ended or using 4-port Balun components, as shown in Figure 5.


    Figure 5 Keysight ADS schematic used to convert from 4-Port single-ended to 2-Port mixed-mode S-parameters using equations or 4-Port Balun components. Differential and common port numbering as D1, D2, C1, C2 respectively.

    Figure 6 plots mixed-mode S-parameters from equations in Table 1. Each quadrant is color coded to coincide with the respective table quadrants.


    Figure 6 An example of 4-Port S-parameter mixed-mode plots of a differential transmission line.


    [1] M. Resso, E. Bogatin, “Signal Integrity Characterization Techniques”, International Engineering Consortium, 300 West Adams Street, Suite 1210, Chicago, Illinois 60606-5114, USA, ISBN: 978-1-931695-93-0

    [2] A. Huynh, M. Karlsson, S. Gong (2010). Mixed-Mode S-Parameters and Conversion Techniques, Advanced Microwave Circuits and Systems, Vitaliy Zhurbenko (Ed.), ISBN: 978-953-307-087-2,InTech, Available from:

    [3] Alfred P. Neves, Mike Resso, and Chun-Ting Wang Lee, “S-parameters: Signal Integrity Analysis in the Blink of an Eye”, Signal Integrity Journal,

    Keysight Advanced Design System (ADS) [computer software], (Version 2020). URL:

    Written by Bert Simonovich

    July 24, 2020 at 11:53 am

    How Authorship Advances Your Career and Become an Industry Influencer

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    imageSo how can authorship advance your career and lead to becoming an industry influencer?

    Well first of all, it offers a chance for deep learning of a subject matter. When you have to capture your thoughts on paper, you suddenly realize you may not know as much about the subject as you think you know. It forces you to do more research on the topic so that the information you are trying to covey is accurate.

    It demonstrates thought leadership at your work and the industry. You become the subject matter expert on that topic. And over time, the path to your desk, is worn from all the traffic to your cubicle. If you are self employed as a consultant, it eventually leads to more business opportunities.

    It inspires your coworkers and peers to become subject matter experts in their own right by leading by example. Being a subject matter expert offers opportunities to work with other subject matter experts in your company on leading edge projects.

    It builds your personal brand. By writing papers and presenting at conferences you become known in the industry from the work you have accomplished and shared.

    It gives you a chance to network, meet and collaborate with new people with like interests in the industry. It’s a snowball effect. I can’t even begin to count now many new people from around the world I have met since starting to publish and attend conferences.

    It builds self confidence. Everyone at one time or another has had a fear of public speaking. By presenting your work in an audience of your peers, that fear of public speaking begins to dissipate.

    Personal pride. Just like a “runner’s high”, you get a dopamine hit every time you see your work published or you present. There is no greater feeling, after spending an enormous amount of time writing your paper, making your slides perfect, continually practicing your presentation, to anyone who will listen, then finally delivering to an audience. It becomes addictive so you will want to continually publish and present your work.

    It leaves a lasting legacy of part of your life’s work behind. Let’s face it, our time is limited on this earth. By publishing your work, it inspires future generations in their research, just like past generations of authors have inspired many of today’s authors, including myself.

    You don’t have to start big. A personal blog, web site is a good place to begin. Trade journals, and online magazines in your industry are always looking for quality content that is relevant to their readers.

    Formal societies, like IEEE, is a more recognized venue and is peer reviewed. Submitting a paper to industry conferences is another way and offers the opportunity to present your work. And finally, the ultimate, is publishing a book.

    Once your work is published, then you need to self promote what you have done. Use social media like LinkedIn, Facebook, Twitter or any other platform. You eventually will build a following, who will react and share your posts and soon become an industry influencer.

    Finally, I’d like to leave you with this final thought. Being Canadian, our national pastime is Hockey. We usually have a hockey analogy for almost anything. Everyone who follows hockey knows Wayne Gretzky, the greatest hockey player of all time. One of his famous quotes was, “You always miss 100% of the shots you don’t take.” And likewise, if you do not take the shot of writing a paper, book or an article, you cannot become a subject matter expert or industry influencer.

    Go for it!

    Written by Bert Simonovich

    April 10, 2020 at 2:20 pm

    Posted in Uncategorized

    DesignCon: The Place to Go to Find Out What You Don’t Know You Don’t Know

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    imageIn engineering, it’s what you don’t know you don’t know that can ruin your day and keep you awake at nights. Especially after you get your prototypes in the lab, or worse, field returns from the customer. This is one reason why I have been going to DesignCon for the last few years, and this year has been no exception.

    One of the sessions I attended was the Power Integrity Boot Camp, hosted by Heidi Barnes, from Keysight Technologies, and Steve Sandler from Picotest. What I didn’t know I didn’t know from this boot camp was how important it was to match the voltage regulator module (VRM) output impedance to the power distribution network (PDN) input impedance. Steve and Heidi recently presented a webcast which was a condensed version of the DesignCon Bootcamp session. If you are involved in PDN design, this webcast will provide you with an introduction to power integrity and give some insight into the latest tips and techniques to achieve flat impedance designs.

    Of course, I always try and attend some of Eric Bogatin’s presentations because I always come away with something I didn’t know I didn’t know. Eric is an Adjunct Professor at the University of Colorado and the Dean of Teledyne LeCroy’s SI Academy. He was honored at this year’s DesignCon with a well-deserved Engineer of the Year Award.

    The speed training event, he hosted along with Larry Smith from Qualcomm, was on the top of my list to attend. During the session, Eric described the most critical feature of PDN design was controlling the “Bandini Mountain”.

    The Bandini Mountain expression has often been used to describe a tall pile of manure. Originally it referred to a 100 foot tall mound of fertilizer built by the Bandini Fertilizer Company in California prior to the 1984 Los Angeles summer Olympics for advertisement purposes. When the company went bankrupt, this large mound of smelly fertilizer was left behind and everyone wished it would go away.

    Because of this little bit of trivia, it was the term coined by the late Steve Weir to describe the large resonant frequency peak formed by the parallel combination of the on die capacitance and the package lead inductance, as seen from the die looking into the PDN. This peak is inherent in all PDN networks, and almost impossible to get rid of. And like the Bandini Mountain, it was something PDN designers wish could go away.

    Steve used to be a regular Icon at past DesignCons until his sudden passing in August 2015. Steve was one of the smartest guys I knew, and I always looked forward to catching up with him when I visited DesignCon. If you knew Steve, like many of us did, you know that he often had very humorous analogies to describe empirical or simulated results. This example is no exception. He will be sorely missed for his contribution the engineering community.

    What I learned I didn’t know I didn’t know from Eric’s and Larry’s presentation was that every PDN design will have a “Bandini Mountain”, and unless you know what frequency it is at, and take steps to try and mitigate its peak, it could ruin your day! Even though the system seems to “work” in the lab, it doesn’t mean it’s robust enough and won’t fail under certain operating conditions in the field that affect the transient currents.

    Eric has made available the speed training slides and the associated video off his SI Academy web site. If you look under Video Recordings, Presentations and Webinars (VRPW) and scroll down to the bottom you will find the slides titled, “VRPW-60-35 DesignCon 2016 PDN speed training”. If you watch the whole presentation you will learn all about the “PDN Bandini Mountain” and techniques to mitigate its effects. And while you are there, have a look at the many other videos and presentations available for free and by paid subscription.

    Eric and Larry have also co-authored a new book, scheduled for release in June 2016 titled, “Principles of Power Integrity for PDN Design”. I can’t wait to buy this book to add to my library so that I can find out more of what I don’t know I don’t know about PDN design. If it’s anything like Eric’s other books, I won’t be disappointed.

    Written by Bert Simonovich

    March 14, 2016 at 2:11 pm

    Posted in Uncategorized


    leave a comment »

    Welcome to my Blog! I am Bert Simonovich, founder and president of Lamsim Enterprises Inc. I graduated in 1976 from Mohawk College of Applied Arts and Technology in Hamilton, Ontario, Canada as an Electronic Engineering Technologist. I started my consulting business after working 32 years at Bell Northern Research/Nortel. Throughout my career, I have held a variety of hardware design engineering positions and pioneered several advanced technologies into products. Currently I offer innovative signal integrity and backplane solutions as a consultant.

    From as far back as I can remember, I was always interested in how things worked. I would often take things apart just to see what was inside; -not always successful in putting them back together again though ;-o.  I was always fascinated with electricity and electronics. When I was about 10 or 11, I was mystified with how telephones worked. After reading about Alexander Graham Bell in a booklet published by The Bell Telephone Company of Canada, I became inspired to buy a pair of old push to talk handsets from a local army surplus store. I experimented with them using a drycell battery and lamp cord wire. When I finally was able to get two-way communications, it seemed like magic. I knew right then what my career choice would be.

    I have been fortunate throughout my career to have been a part of and contribute to some of the technology that enable the gadgets we enjoy today. I have met and worked with many smart and talented individuals who took the time to unselfishly share their knowledge and experience.

    And now, after all this time, the passion I had as kid to learn and understand new things is still there. Except now, like cradling a fine glass of wine, I am able to slowly swirl it around, sip it and savor the taste. This blog is about sharing some of that passion. It will cover a range of topics from signal integrity, PCBs, backplane design, circuit modeling, simulation tools and other practical engineering solutions. I hope you find my posts interesting and get inspired to explore them further on your own.

    Thanks for visiting. I invite you to constructively comment and share your own thoughts and experiences as well.

    Written by Bert Simonovich

    December 13, 2010 at 12:30 pm

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