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Field Solver Nuances: How to avoid GIGO
To avoid “garbage in, garbage out” (GIGO) with any field solver, first you need to understand the little nuances of PCB fabrication process and how to interpret manufacturers’ data sheets. But most importantly you need to understand the tool’s user interface and what it is asking for.
All 2D or 3D field solvers will give accurate impedance predictions. The differences are the type of solvers used under the hood and complexity of the user interface. Simple 2D field solvers, used in many of today’s stackup planners, simply give predicted characteristic impedance based on material properties and trace geometries. More complex, 2.5D or 3D field solvers, allow for additional material parameters and can predict insertion loss, phase delay and impedance over frequency. Some will even export RLGC and touchstone files for further signal integrity analysis.
Standard PCBs are fabricated using cores and prepreg material. Prepreg sheets are a mixture of fiberglass (glass) cloth and resin which is partially cured. Cores are simply cured prepreg sheets with copper bonded to one or both sides of the laminate. Copper is etched away on each side of the foil to leave the circuit pattern.
In a multilayer PCB, cores and prepreg sheets are alternately stacked symmetrically above and below the middle of the layup then pressed under heat and pressure. The prepreg layers gets thinner when pressed allowing the resin to fill the voids between the copper features that were etched away on the cores.
One important parameter for accurate impedance modeling is dielectric constant (Dk). The best source is from laminate suppliers’ data sheets. But all data sheets from laminate suppliers are not the same.
“Marketing” data sheets are data sheets easily found on laminate suppliers’ websites. They are meant for quick comparison of dielectric properties to narrow your search for the right laminate for your application. They include mostly thermal and mechanical properties, which are important for the physical structure of the material and how it will perform with other material properties in the stackup during processing [3].
Marketing data sheets usually only report a typical Dk value at fifty percent resin content at two or three frequency points. Depending on glass style, resin content and thickness, Dk and dissipation factor (Df), will be different for different cores and prepreg thicknesses for the same laminate chemistry. In the end, they are not representative of what is needed to design an actual stackup, or to do impedance and loss modeling. Using these numbers will almost always lead to inaccurate impedance and signal integrity (SI) results.
Instead, you need to use the same Dk/Df construction table data sheets PCB fabricators use for the stackup. Dk/Df construction tables provide the actual core and prepreg thicknesses, resin content, and Dk/Df for the different glass styles, over different frequencies. Depending on the stackup, a combination of thicknesses is often needed to meet impedance requirements and have different Dk values.
Many engineers assume Dk published is the intrinsic property of the material. But in fact, it is the effective Dk (Dkeff) measured by a specific industry standard test method. It does not guarantee the values directly correspond to design applications. When compared against measurements from a design application, there is often a discrepancy in Dkeff due to increased phase delay caused by surface roughness [1].
Dkeff is highly dependent on the test apparatus and conditions of how it is measured. One popular test method, IPCTM650 2.5.5.5C clamped stripline resonator test method, assures consistency of product during fabrication. Due to the nature of this test method, the materials under test are not physically bonded together, air is entrapped between the various layers. These small air gaps are caused by: roughness of the copper foil plates in the fixture; roughness profile imprint left on the surface from the foil that was removed from the test samples; copper removed on the resonant element pattern card. Air entrapment results in a lower Dkeff than what is measured because in a real PCB everything is bonded together, with no air entrapment [3].
All glass weave reinforced laminates are anisotropic, which means Efield orientation, relative to the glass weave, is different depending on test method. Efields produced from tests like IPCTM650 2.5.5.5C are transverse to the glass weave and Dkeff measured is outofplane.
Efields produced by TM6502.5.5.13 split post cavity resonators, are parallel to the fiberglass weave Dkeff measured this way is inplane. Dkeff is typically higher for inplane measurements, compared to outofplane, depending on the glass resin mixtures used in the stackup.
Another source of discrepancy is not accounting for increased Dkeff due to the pressed thickness of prepreg. Since prepreg sheets have a certain percentage of resin content for the thickness, after pressing the resin content is reduced and since Dk is a function of resin and glass mixture, there will be a higher percentage of glass after pressing and thus slightly higher Dkeff.
The most common PCB trace geometries are microstrip and stripline. A simple microstriip geometry is bare copper traces over a reference plane, separated by a dielectric height H, as shown in Figure 1. Depending on the stackup, there may be a core and prepreg layer between the outer layer and reference plane with the same or different Dk values for Dk1 and Dk2.
Simple stripline geometry has copper traces between two reference planes. For singleended (SE) signals, there is only one trace used in the field solver to calculate the SE impedance. For differential pairs, there are two traces separated by a space. Because resin fills the voids between copper features the Dk_{resin} will be lower than Dk1 or Dk2, shown in Figure 1.
The last thing to note is the wider side of the trace always faces the core material. This is a very important point to remember when using any field solver. If you get it reversed, it will lead to inaccurate results.
Figure 1 Generic microstrip and stripline geometries.
Thickness of copper traces is an important parameter for accurate impedance prediction. Copper thickness is usually specified in ounces per square foot. Most common thicknesses for inner layer traces are ½ oz. and 1 oz. foil. But field solvers expect an actual thickness dimension.
Most designers assume 0.7 mils (18um) thickness and 1.4 mils (36um) for ½ oz. and 1 oz. respectively. But because of the price of copper, the copper you get from foil manufacturers will likely be the minimum thickness allowed under IPC4562A. When you factor in the typical thickness after fabrication, the typical thickness can be 0.6 mils (15um) and 1.2 mils (30um). But the minimum thickness allowed under IPCA600G3.2.4 is 0.45 mils (11.4um) and 0.98 mils (24.9 um) for ½ oz. and 1 oz. respectively.
Due to the nature of the etching process, the traces will usually be trapezoidal in shape. This is known as the etch factor (EF), as defined by IPCA600G. It is the ratio of the thickness (t) to half the difference between W1 and W2.
Thus,
Some field solvers will define EF differently so it is important to understand how to specify it properly.
Once you’ve come up with a proposed stackup, the next step is to do some impedance modeling. Normally your fab shop comes up with this, but it is a good idea to validate their proposal, to ensure you are in sync with them.
The first thing to do, is identify the layers from which to model. Next, is to use your field solver, to model characteristic impedance. Since all field solvers are different, and user interfaces can be confusing, make sure you understand the little nuances of your tool.
The next thing is to identify the core layers in the stackup and input H1 and Dk1 for the dielectric. Then, input the pressed thickness for prepreg H2 and Dk2, not the thickness found in Dk/Df construction tables. You can usually trust the pressed thickness from your fab shop. But be careful how the field solver defines H2. Most field solvers define it as shown in Figure 1, but some solvers, like Polar Si9000e, define it as (H2+t), shown in Figure 2. Usually, you can trust the pressed thickness from your board shop stackup drawing.
Finally, if your field solver allows for it, fill in Dk_{resin} between two traces if you know it. It will be lower than Dk2. Since this number is generally hard to obtain, a rough estimate to use is the lowest Dk value from the highest resin content prepreg found in Dk/Df construction tables.
Once everything is set up, optimize the line width and space, until the desired characteristic impedance is reached. One last point to remember, is that all 2D field solvers only calculate lossless characteristic impedance. But when we measure an impedance test coupon with a time domain reflectometer (TDR), we are measuring the instantaneous impedance along the PCB trace.
More often than not, impedance is different than what was predicted. This is because a 2D field solver only calculates the lossless characteristic impedance of the crosssectional geometry; while a TDR measures the instantaneous impedance of a lossy transmission line at every point along its length.
A 2D field solver has no input for conductor resistivity, dielectric loss, or how long the conductor is. Resistive loss often results in a slow monotonic rise in the impedance profile. IPCTM650 specifies the measurement zone between 3070 % and most PCB fab shops, will measure an average impedance
In this example, shown in Figure 2, for a low loss dielectric, there is a 45 ohm difference depending on where the measurement is taken. When all input parameters are included correctly for a lossy transmission line model, you can see there is excellent correlation.
Figure 2 Lossless characteristic impedance from Polar SI9000 field solver (left) vs measured TDR plot from an impedance coupon and lossy transmission line model from Polar Si9000.
Although minor differences in individual parameters may have second order affects, collectively they could add up to give poor correlation to measurements. But if you consider all the nuances discussed in this article, you can get pretty good accuracy as shown in Figure 2.
[1] Bert Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”, DesignCon 2017, Santa Clara, CA
[2] Bert Simonovich, “PCB Fabrication: What SI/PI Engineers Need to Know for First Time Modeling Success”, DesignCon 2021 Spring Break Webinar, April 12, 2021
[3] Bert Simonovich, A Tale of Two Data Sheets and How Foil Roughness Affects Dk, White paper
A Tale of Two Data Sheets Part 2: Making Sense of “Design” Dk
Originally published in Signal Integrity Journal, May 31, 2022
In part one, “A Tale of Two Data Sheets”, I explained how air entrapment, due to IPCTM6502.5.5.5 test method manual [7], is the primary reason for effective dielectric constant (Dkeff) and phase delay discrepancies between simulation and device under test (DUT) measurements. Entrapped air of the test fixture results in a lower Dk published in laminate suppliers’ Dk/Df tables than what would be measured in a real printed circuit board (PCB) application. This is because in a real PCB, everything is bonded together with no air entrapment, as shown in a crosssection view of Figure 1.
Figure 1. Example of foil bonded to core or prepreg dielectric. Rz is 10point mean roughness of foil as measured by a profilometer. Hsmooth is the thickness of the dielectric as if the foil was removed.
When copper foil with the same Rz roughness is bonded to each side of the core or prepeg, Dkeff is determined heuristically from published Dk by this simple correction factor [1]:
Equation 1.
where:
Hsmooth is the thickness of the dielectric as if the foil was removed
Dk = Dielectric constant published in laminate suppliers’ Dk/Df tables
Rz = 10point mean equivalent to Rz(JIS) or Rz(DIN) published in foil suppliers’ data sheets. This is not to be confused with Rq, which is RMS value of roughness.
Rogers Corporation [4] understands this. That’s why they provide the “design” Dk in addition to their bulk Dk, as measured by TM650 clamped stripline resonator test method [7]. Design Dk is an average number using a differential phase length method from several different tested lots of material and on the most common thickness. This method is based on measuring phase difference from two identical microstrip transmission line geometries, of different lengths on the same panel. Because this is a real microstrip application, the dielectric is fully bonded to the copper and there is no air entrapment. Knowing the phase and length difference, the effective Dk is empirically determined.
The accuracy of the resultant effective Dk depends on several factors like:


fixture design



length ratio between two transmission lines



material thickness of the sample under test



the thickness of the copper



actual roughness of the foil on the microstrip circuit.

In lieu of actual Dk/Df tables, Rogers provides a handy impedance calculator as shown in in the RO4003C example of Figure 2. There are three Dk options available to use:


Zaxis bulk Dk



Dk values for specific frequencies



Dk values for characteristic impedance

The first radio button, as shown in Figure 2, gives the zaxis bulk Dk value of 3.55, as measured by TM650 2.5.5.5 test method manual. However, the value does not change when different frequencies are selected. This makes the number suspect since clearly design Dk does change over frequency. Thus this number can be considered equivalent to marketing data sheets, and should not be used.
When the middle radio button is selected, a Dk value for a specific frequency is displayed, which corresponds to a frequency entered in the lower right frequency box of Figure 2. This is the most useful option, since it allows the user to choose the right design Dk at whatever frequency they choose for their application, including characteristic impedance. This option already factors in the foil roughness effect, so no correction factor is needed to use in your simulator.
The last radio button selects a Dk for characteristic impedance calculation. It is a “design” Dk with yet a different Dk. Similar to the Bulk Dk option, it does not change over frequency. For any simulation tool other than the Rogers’s calculator, Bulk Dk and Dk values for characteristic impedance values should not be used.
Figure 2. Example of Rogers Corporation impedance calculator. For an 8mil thick RO4003C dielectric, bulk Dk is 3.55 while design Dk over frequency is shown in bottom left window.
Under the information tab, the user can download design Dk over frequency, for a specified thickness, shown in the bottom left window of Figure 2. This data can be selected and copied to the clipboard and pasted into a spreadsheet for further processing.
Figure 3 plots design Dk vs. frequency for various thickness from 8 mils to 60 mils for RO4003C material. As can be seen, design Dk is not constant over frequency and furthermore it is different for different thicknesses, mainly due to the roughness of the foil that is already included in the measurement.
Thinner materials have a higher design Dk than thicker materials for the same roughness of foil. This is because when the foil teeth protrude into a thin dielectric material, there is a higher concentration of efields, resulting in higher capacitance between top and bottom copper layers. For thick dielectrics the foil teeth have less of an impact on capacitance and thus Dkeff, as described mathematically by Equation 1.
Since the roughness of the foil does not significantly influence the design Dk for thick laminates, we can assume the bulk Dk is roughly equivalent to design Dk over frequency for the 60mil laminate.
Figure 3. Design Dk vs. frequency for various thickness of RO4003C from 8 mils to 60 mils mainly due to the roughness of the foil. Thinner material has a higher design Dk than thicker material, for the same roughness of foil.
Heuristically, we can rearrange Equation 1 and estimate the Rz roughness of the foil used on RO4003C laminate to be 6.302 μm from Equation 2.
Equation 2.
where:
Hsmooth is the thickness of the 8 mil (203 μm) laminate
DkBulk = 3.55 at 60 GHz for 60 mil (1524 μm) laminate
Dkeff = design Dk of 8 mil (203 μm) laminate at 60 GHz
A crosssection sample from a time domain reflectometry (TDR) demo board, courtesy of Picotest [6], was measured and is shown in Figure 4. The TDR demo board was fabricated with 8mil thick Rogers RO4003C core laminate and cladded with 2 Oz copper foil.
Five highlighted random sample lengths of copper roughness, labeled Sample 1 to Sample 5 of Figure 4, were analyzed. The total length of each respective sample was then partitioned into five equal sections, similar to the blowup picture of Sample 1, to measure the maximum peak to valley height of each section. The five measurements of each sample length were then averaged to determine the Rz roughness, as described under IPC TM650 2.2.17A [8] and shown in the table of Figure 4.
The mean value of Rz for the five samples was 6.176 μm with a standard deviation (SD) of 1.090 μm. This compares favorably with the estimated roughness of 6.302 μm, determined from Equation 2.
Figure 4. A crosssection sample from a Rogers RO4003C based TDR demo board, courtesy of Picotest [6], used to determine Rz roughness of the foil.
When we use the actual roughness measured from Figure 4 and Equation 1, we can then calculate Dkeff at 60 GHz for different thicknesses, shown in Table 1. As can be seen there is, less than 1% delta compared with design Dk reported from the calculator!
Table 1. Comparison of Roger’s Design Dk vs. Dkeff when simple correction factor applied to Bulk Dk at 60 GHz.
Height 
Height 
Bulk Dk 
Design Dk 
Rz 
Dkeff 
Delta 
8.0 
203 
3.550 
3.785 
6.176 
3.780 
0.13% 
12.0 
304 
3.550 
3.702 
6.176 
3.700 
0.04% 
16.0 
406 
3.550 
3.657 
6.176 
3.661 
0.12% 
20.0 
508 
3.550 
3.625 
6.176 
3.638 
0.37% 
32.0 
812 
3.550 
3.580 
6.176 
3.605 
0.69% 
60.0 
1524 
3.550 
3.550 
6.176 
3.579 
0.82% 
Rogers Corporation provides a handy calculator in lieu of Dk/Df tables in which “design” Dk values over frequency can be used directly without correcting for roughness. When an actual crosssection was analyzed, there was excellent correlation from corrected Dkeff using heuristic methods compared to design Dk from the calculator. Therefore, “design” Dk should be used for impedance modeling and PCB stackup design when using Rogers laminates.
References:


B. Simonovich, “A Tale of Two Data Sheets and What You Need to Know About Dielectric Constant (DK),” Signal Integrity Journal article, April 2022.



L. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness,” DesignCon 2017, Santa Clara, USA.



Isola Group, 6565 West Frye, Chandler, AZ 85226.



Rogers Corporation, 2225 W. Chandler Blvd., Chandler, AZ 85224.



J. Coonrod, “Managing PCB Materials: Dielectric Constant (Dk)”, Rogers Corporation, Blog Article, Sep 11, 2018.



Picotest, Phoenix, AZ 85085.



IPCTM650, 2.2.17A, Test Methods Manual, “Surface Roughness and Profile of Metallic Foils (Contacting Stylus Technique).”



Bereskin, A. B. “Microwave Dielectric Property Measurements”, Microwave Journal, vol. 35, no.7, pp. 98 – 112.

A Tale of Two Data Sheets: Part1
Originally published SI Journal April 26, 2022
When doing printed circuit board (PCB) stackup and signal integrity (SI) impedance modeling, we need to get the dielectric material properties from the right sources. One important parameter for accurate impedance modeling is relative permittivity (ε_{r}) of the dielectric material, otherwise known as dielectric constant (Dk). The best source is from laminate suppliers’ data sheets. Though there is an issue with these I like to think of as, “a tale of two data sheets.”
Marketing data sheets, like the example shown in Figure 1 [6], are easily found on laminate suppliers’ websites. They are meant for quick comparison of dielectric properties to narrow your search for the right laminate for your application. Dielectric properties on marketing data sheets include mostly thermal and mechanical properties, which are important for the physical structure of the material and how it will perform with other material properties in the stackup during processing.
But marketing data sheets are not representative of what is needed to design an actual stackup, or to do impedance and SI loss modeling. Depending on glass style, resin content, thickness, Dk, and dissipation factor (Df) will be different for different cores and prepreg thicknesses for the same laminate. Marketing data sheets usually only report a typical Dk/Df at fifty percent resin content and two or three frequency points. Thickness is not specified. Furthermore, Dk and Df are not constant over frequency. So, using numbers from these data sheets will lead to inaccurate impedance and phase delay results.
Figure 1. Example of a “Marketing” data sheet easily obtained from laminate supplier’s web site. Source Isola Group [6].
Instead, for transmission line modeling, one needs to use the same Dk/Df table data sheets PCB fabricators use to build the stackup. An example Dk/Df table is shown in Figure 2. Dk/Df tables provide the actual core and prepreg thicknesses, resin content, and Dk/Df for the different glass styles, over different frequencies. Depending on the stackup, a combination of thicknesses is often needed to meet impedance requirements. Each thickness will have a different Dk value.
In the example of Figure 2, Dk varies from 2.92 at 10 GHz for 1080 glass style to 3.19 at 10 GHz for 2116 glass style. This represents a Dk variation of 3.3% to 5.6% when compared to a Dk of 3.02 at 10 GHz specified in Figure 1.
Figure 2. Example of a typical “Engineering” data sheet showing Dk/Df table for different glass styles and resin content over frequency. Source Isola Group [6].
Many engineers assume Dk published is the intrinsic property of the material. But, in fact, it is the effective Dk (Dkeff) measured by a specific industry standard test method. When they are compared against real measurements from a design application, there is often a discrepancy in Dkeff due to increased phase delay caused by surface roughness [1].
Dkeff is highly dependent on the test apparatus and conditions of how it is measured. One method commonly used by many laminate suppliers is the clamped stripline resonator test method, as described by IPCTM650 2.5.5.5, Rev C, Test Methods Manual [10].
Since all glass reinforced laminates are anisotropic, any stripline based test method, like TM650 2.5.5.5, or Bereskin stripline test method [13], reports Dk values in which the Efields are transverse to signal propagation. That is, if the signal propagation is in the xy axis direction, then the Dk measured by this method is when Efields are in the zaxis direction.
For Isola’s Dk/Df table [6], shown in Figure 2, Dk values were measured by TM650 2.5.5.5 test method. From that data, the values for most of the constructions are calculated. Additional verification runs are performed to gather statistical data over time and validate that the calculations are reasonable and accurate.
The measurements are done under stripline conditions using a carefully designed resonant element pattern card. It is made with the same dielectric material to be tested. As shown in Figure 3, the card is sandwiched between two sheets of uncladded dielectric material under test. Then the whole structure is clamped between two large plates; each lined with copper foil and grounded. They act as reference planes for the stripline.
Figure 3. Illustration of clamped stripline resonator test method, as described by IPCTM650, 2.5.5.5, Rev C, Test Methods Manual [10].
This test method assures consistency of product when used in fabricated boards. It does not guarantee the values directly correspond to design applications.
Here is why:
Since the resonant element pattern card and material under test are not physically bonded together, air is entrapped between the various layers. These small air gaps are caused by the:

roughness of the copper foil plates in the fixture

roughness profile imprint left on the surface from the foil that was removed from the test samples

copper removed on the resonant element pattern card
Air entrapment, due to the TM650 test method, is the primary reason for effective Dk and phase delay discrepancies between simulation using laminate suppliers’ Dk/Df tables and real measurements from a design application. The small air gaps result in a lower effective Dk than what would be measured in a real PCB because everything is pressed together with no air entrapment, as shown in a crosssection view of Figure 4.
Figure 4. Example of foil bonded to core or prepreg dielectric. Rz_{1 }is rougher than Rz_{2} and H_{smooth} is the thickness of the dielectric as if the foil was removed.
When copper roughness is different on each side of the dielectric, like the example shown in Figure 4, Dkeff is determined heuristically by this simple correction factor:
Equation 1.
where:

H_{smooth} is dielectric core thickness from laminate suppliers’ Dk/Df table data sheet or pressed prepreg thickness from the PCB stackup drawing.

Rz_{1} and Rz_{2} are the conductor roughness of the foil for the respective side of the dielectric from foil suppliers’ data sheet. Typically, Rz is the 10point mean roughness as measured by a mechanical profilometer.

Dk is dielectric constant from laminate supplier’s Dk/Df table data sheet.
In Figure 4, Rz_{1} is the roughness of the top foil, and Rz_{2} is the roughness of the bottom foil. In this example, Rz_{1} is rougher than Rz_{2}. H_{smooth} is the core thickness of the dielectric, as specified in the Dk/Df table, or pressed thickness of the prepreg, often shown on a stackup drawing. It is the thickness of the dielectric as if the foil was removed.
When copper foil with the same Rz roughness is bonded to each side of the core or prepeg, Dkeff can be simplified as:
Equation 2
Figure 5 plots Dkeff over frequency derived from S21 phase or time delay (TD); Dkeff=(TDc_{0 }∕ length)^{2} from a Megtron6 stripline case study [3]. This method is different than IPCTM650 test method in that it determines Dkeff from unwrapped phase delay rather than calculating Dk/Df from resonant peaks over the frequency range defined in the spec.
The blue plot is a simulated case based on core and prepreg Dk values from published Dk/Df tables at 12 GHz. When Dk is corrected due to roughness, using Equation 2, and resimulated, Dkeff is shown in pink. Although the Dkeff has improved, it still does not agree with the measured Dkeff from the device under test (DUT), shown in red.
Figure 5. Comparisons of simulated Dkeff over frequency vs. measured. The red plot is actual measured Dkeff from the DUT. The middle pink plot is a simulation using Dkeff corrected due to roughness. The bottom blue plot is simulated using Dk at 12 GHz as published in Dk/Df tables and noncausal roughness model. The green dashed plot is a simulation using Dkeff due to roughness; a causal HurayBracken roughness model was used. Modeled with Simbeor [11] and simulated with Keysight ADS [12].
The discrepancy between the pink and red plots is because Dkeff from Equation 2 only corrects the phase delay due to self capacitance (C_{11}) per unit length of the transmission line. But roughness of the foil also increases the self inductance (L_{11}) per unit length of the transmission line, which adds additional phase or time delay [4].
This is counter intuitive and can be confusing since we usually relate Dkeff to capacitance only. By definition, Dkeff is the ratio of the actual structure’s capacitance to the capacitance when the dielectric is replaced by air. But this is only true for static electric fields. For timevariant electromagnetic fields, Dkeff becomes frequencydependent [14].
If the propagation delay (tpd) for a single transmission line, in seconds per unit length, is determined by:
Equation 3.
and c_{0} is the speed of light (~3.0E8 m/s) =1/sqrt(μ_{0} ε_{0} ); μ_{0} (4πE−7 H/m) and ε_{0 }(8.8542E−12 F/m) is permeability and permittivity of free space respectively, then:
Equation 4.
where: L_{11}; C_{11} are self inductance in Henries per unit length and self capacitance in Farads per unit length respectively.
Equation 4 clearly shows that with an increase in self inductance there will be a proportional increase in Dkeff. This means for PCB transmission lines, calculating Dkeff=(TDc_{0 }∕ length)^{2} cannot be trusted to be the same as relative permittivity (ε_{r}) of the dielectric material. The consequence for doing so leads to inaccurate impedance predictions and noncausal time domain simulations, resulting in poor correlation to measurements.
A causal model, when simulated, does not produce any change in its output signal before there is a change in its input signal. When field solvers properly correct the self inductance, by applying the roughness correction factor to the imaginary portion of the complex impedance of the metal [4][5], the model is then causal. When combined with the corrected Dkeff for cores and prepregs from Equation 2, there is excellent correlation, as shown by the dashed green plot in Figure 5. Unfortunately, not all field solvers have causal roughness models to correct the inductance in the simulation.
Since there is no simple way to backtrack from a phase measurement to establish the right Dkeff to use for your modeling, especially for lossy stripline constructions, heuristic methods are an alternative.
Using the right Dkeff for your modeling ensures a correct time domain reflectometer (TDR) impedance prediction, as shown in Figure 6. The red plot is measured differential TDR from [3]. When core and prepreg Dk from Dk/Df tables were used along with a noncausal roughness model in the simulation, the blue plot shows an overestimate for impedance. When Dkeff from Equation 2, and a noncausal roughness model was used in the simulation, the pink plot shows an underestimate in the impedance plot.
It is only when we apply a causal HurayBracken roughness model from [11], along with Dkeff from Equation 2, that we see the effect of the increased self inductance, shown by the green dashed line plot in Figure 6.
At first glance of Figure 6, one might interpret the pink plot as having better correlation to the measured red plot. But because the measured plot has an impedance ripple along its length, it is difficult to conclude which is the correct model from the TDR plots alone. It is only when we compare Dkeff derived from the green dashed phase delay plot from Figure 5 that we can conclude the green dashed line TDR plot is the correct impedance.
Figure 6. Simulated vs. measured differential TDR plots when different Dkeff was used in the model. The blue plot overestimates impedance when Dk from data sheets was used. The pink plot underestimates the impedance when Dkeff (Equation 2) and noncausal roughness model was used. The green dashed line plot is when Dkeff (Equation 2) and a causal HurayBracken roughness model were used. Modeled with Simbeor [11] and simulated with Keysight ADS [12].
Summary:
Dielectric constants from marketing data sheets cannot be trusted to properly design PCB stackups and model transmission lines for impedance and phase delay. Instead, laminate suppliers’ Dk/Df tables should be used.
Many laminate suppliers provide Dk/Df tables derived from a clamped stripline resonator test method [10] or similar Bereskin test method [13]. But the numbers do not factor the actual roughness of the foil. When a simple correction factor, based on the thickness of laminate and Rz foil roughness is considered, a more accurate value for Dkeff along with a causal roughness model can be used for impedance and transmission line modeling.
For PCB transmission lines, calculating Dkeff from phase or time delay measurement method cannot be trusted to be the relative permittivity of the dielectric material. Using this value will lead to inaccurate simulation results.
References:
1. L. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness“, DesignCon 2017, Santa Clara, USA.
2. B. Simonovich, “Stackup Beware: Case Study of the Effects on Transmission Line Losses Due to Mixed Reference Plane Roughness”, Signal Integrity Journal article, August 10, 2021.
3. B. Simonovich, “PCB Fabrication: What SI/PI Engineers Need to Know for First Time Modeling Success”, DesignCon 2021 Spring Break Webinar Series, April 1216, 2021.
4. V. DmitrievZdorov, B. Simonovich, Igor Kochikov, “A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics“, DesignCon 2018, Santa Clara, USA.
5. J.E. Bracken, “A Causal Huray Model for Surface Roughness”, DesignCon 2012, Santa Clara, USA.
6. Isola Group, 6565 West Frye, Chandler, AZ 85226.
7. Circuit Foil, 6 Salzbaach, 9559 Wiltz, Grand Duchy of Luxembourg.
8. Rogers Corporation, 2225 W. Chandler Blvd., Chandler, AZ 85224.
9. J. Coonrod, “Managing PCB Materials: Dielectric Constant (Dk)”, Rogers Corporation, Blog Article, Sep 11, 2018
10. IPCTM650, 2.5.5.5, Rev C, Test Methods Manual
11. Simbeor THz [computer software].
12. Keysight ADS Keysight Advanced Design System (ADS) [computer software].
13. Bereskin, A. B. “Microwave Dielectric Property Measurements”, Microwave Journal, vol. 35, no.7, pp. 98 – 112
14. Wikipedia contributors. (2022, January 12). Relative permittivity. In Wikipedia, The Free Encyclopedia. Retrieved 18:14, January 14, 2022.
The Effects on Transmission Line Losses Due to Mixed Reference Plane Roughness Case Study
This article is an edited version of White Paper, “Heuristic Modeling of Transmission Lines due to Mixed Reference Plane Foil Roughness in Printed Circuit Board Stackups” [1].
Designing the right printed circuit board (PCB) stackup can make or break your product performance. If your product has circuitry that is transmission loss sensitive, then paying attention to conductor surface roughness is paramount.
Conductor surface roughness traditionally has been applied to copper foil to promote adhesion to the dielectric material. Early PCBs were only constructed with single or doublesided copper core laminates. The only important metric for copper was its purity and the roughness to improve peel strength. There was no such thing as a PCB stackup and nobody worried about impedance or transmission line losses.
But over the years PCBs have evolved into multilayer constructions with evermore attention being paid to impedance control and transmission line losses. Thus a PCB stackup definition became vital for consistent performance.
Like any construction project, you need a blueprint before you start building. Similarly for PCBs, you need a stackup drawing and detailed fabrication notes. Part of the stackup design process includes signal integrity (SI) modeling for characteristic impedance and transmission loss. If your design is running at 56Gig pulse amplitude modulation level 4 (PAM4), for example, you are probably looking at low loss dielectrics and low roughness copper for the signal traces.
But what is sometimes overlooked in the stackup, is the roughness of the reference planes. Often thin core laminate power and ground (GND) planes will specify reversetreated foils (RTF), which are rougher on the side that bonds to the prepreg. Sometimes one of these planes, usually GND, acts as a reference plane to an adjacent signal layer as shown in Figure 1. If that adjacent highspeed signal layer is using smoother copper than one or both reference planes, a higher insertion loss than expected for that layer will occur and possibly ruin your day.
A similar scenario could occur for high density interconnect (HDI) technology. This is a popular method to increase component density on modern PCBs. By the nature of their stackup construction, a rougher copper reference plane could sometimes also end up adjacent to a signal layer as well. Thus, if insertion loss is a concern, copper foil roughness of reference planes needs to be considered.
Figure 1 An example crosssection stripline geometry from a stackup showing thin core laminate (top) with RTF bonded to prepreg and adjacent to a highspeed differential pair with smooth foil.
So how do you know this before you design your stackup and build your first prototype? Since we do not have any empirical data to go by, we can rely on a heuristic, highlevel design (HLD) modeling method starting with published parameters found solely in manufacturer’s data sheets.
Heuristic HLD modeling is a practical technique that is not guaranteed to be perfect, but is still adequate in finding a satisfactory solution sooner, rather than later.
For dielectric parameters, we choose dielectric constant (Dk) / dissipation factor (Df) at or near the Nyquist frequency of the baud rate, then apply effective Dk (Dkeff) correction factor due to roughness, Equation 1 [5].
where:
H = thickness of core/prepreg; Rz is surface roughness of copper; Dk is as published in laminate supplier’s Dk/Df tables. Equation 1 assumes Rz of the foil on each side of the dielectric (core or prepreg) is the same.
For conductor loss, we use Rz roughness numbers from copper suppliers’ data sheets and oxide/oxide alternative Rz roughness numbers from your favorite fab shop, then apply the CannonballHuray roughness model [1][3].
CannonballHuray Model
The original Huray model is defined as:
Equation 2
The CannonballHuray model allows you to extract the right parameters using Rz roughness for core and prepreg sides of the foil [1]. Because the CannonballHuray model assumes the ratio of A_{matte}/A_{flat} = 1, and N_{i} = 14 spheres, the radius of a sphere (r) can be determined by:
and area of flat tile base (A_{flat}) by:
Equation 4
Wildriver Isola ITera® MT40 Custom Modeling Platform Case Study
To study the effect of reference plane roughness on transmission insertion loss, Wildriver Technology’s [7] custom modeling platform (CMP), shown in Figure 2, was used as a case study. This CMP was custom developed for Isola [6] to characterize their new ITera® MT40 very lowloss laminate material.
It combines 27 structures based on a consistent development of primitive structures; useful for performing a host of calibrations including automatic fixture removal, unknown THRU, WinCal XE™ calibration, and VNA gating and time transform analysis.
Figure 2 Wildriver Isola ITera® MT40 Custom Modeling Platform. Source: Wildriver Technology [7]
Stackup Validation
The PCB stackup is shown in Figure 3. Often PCB fab shop field application engineers (FAE) modify existing stackups and unintentionally make errors in transferring new parameters from data sheets into their software tools. Also, they may not necessarily know the design intent of the stackup. So the first step for any model correlation exercise is to sanitize the stackup, to ensure it meets the product design intent for signal integrity (SI) performance. In fact that is how the issue of different plane roughness was uncovered.
Since it is always a good practice to ensure the same roughness is specified for reference planes as the adjacent signal layers, I naively assumed it would be the case for any highspeed stackup. But that wasn’t the case here. Layers E1,E2 and E7, E8 specify 1oz RTF, while layers E3, E4 and E5, E6 specify 1oz VLP2 foil. Because the Isola ITera® MT40 CMP is intended to aid in modeling test structures, this is not a fatal flaw. On the contrary, it is a perfect platform to assess the effect of rougher reference planes.
Figure 3 Isola ITera® MT40 Custom Modeling Platform stackup. Source: Wildriver Technology [7]
Upon further review, it was discovered that the core laminates between E3,E4 and E5, E6 specified 1067/2×3313 glass styles, but this combination was not listed for 12 mil thickness. Instead, only 3×3313 core is offered. Because of that, the Dk shown is also wrong and will affect the impedance of the traces. The right Dk for 3×3313 is 3.53 instead if 3.33.
Foil Roughness
As mentioned earlier, the roughness of the foil affects the effective Dk, so we need to use the right number for our model validation. The standard VLP2 foil, used on ITera® MT40 core laminates is BFTZA foil. Optional RTF foil, used for layers E1, E2 and E7, E8, is TWLSB. Both are from Circuit Foil [8].
Relevant roughness parameters are shown in Figure 4. For the core side of the foil we are interested in the Rz parameters for the treated side listed in the table. But there are two Rz parameters, JIS B 601 and ISO 4287 specified. So which one do we use for modeling?
From IPCTM650 Section 1.2 [11] states, “The foil profile of foils shall be evaluated using the parameter Rz (DIN) or RTM, which is defined as the average maximum peak to valley height of five consecutive sampling lengths within the measurement length. This value is approximately equivalent to the values of profile determined from microsectioning techniques.”
and;
Section 1.3 states, “RZ (ISO) is a different parameter from Rz (DIN) and is not applicable to this method.”
Rz JIS represents the 10point mean value, which is the sum of the average of the 5 highest peaks and the 5 lowest valleys over the sample length. Rz DIN is similar; except it is defined as the average maximum peak to valley height of five consecutive sampling lengths within the measurement length. Thus we will use Rz JIS for modeling analysis.
Figure 4 Roughness parameters from Circuit Foil [8] data sheets. Top is VLP2 standard foil used on ITera® MT40, while bottom is RTF option used for relevant layers in the stackup
Determine Effective Dk Due to Roughness
The first step in HLD impedance modeling is to gather all the dielectric and foil data sheet parameters to determine the effective Dk.
Figure 5 summarizes thickness of core, prepreg and signal trace from the stackup geometry in Figure 3. Note that photos are for illustrative purposes only and are not actual crosssections from CMP PCB. Dk for core and prepreg were obtained from Isola ITera® MT40 Dk/Df tables [6].
Figure 5 Data sheet parameters for RTF/VLP2 foil roughness and dielectric properties for ITera® MT40 stackup geometry. Note: Photos are for illustrative purposes only and are not actual crosssections from CMP PCB. Surface roughness pictures source: Circuit Foil [8]
The top reference plane is TWLSB RTF foil with matte side 1 ≤ 7.5 JIS, obtained from Circuit Foil data sheet (Figure 4). The roughness surface profile is shown in the upper left. After OA smoothing, 1 ≤ 6.23 [1].
BFTZA foil is used for both sides of the core laminate. The top surface of the stripline trace, shown in the upper right picture, is the drum side of the foil, before OA treatment. After OA treatment, Rz2 ~ 1.9 μm [1].
The bottom surface profile of the stripline trace and the top surface of the bottom reference plane are the treated matte sides of the foil, shown in the bottom right and bottom left pictures respectively. They both share the same roughness (Rz3, Rz4 =2.5μm JIS) from the BFTZA data sheet (Figure 4).
The next step is to convert the imperial thickness units to metric, then use Equation 1 to determine Dkeff due to roughness for the prepreg and core.
Determine CannonballHuray Roughness Parameters
Several popular electronic design automation (EDA) tools include the CannonballHuray model directly as an option, so the respective Rz parameter is all that is needed.
Any of these tools can be used for HLD modeling, but my favorite is Polar SI9000 [9] because of its simplicity and sufficient accuracy for prefabrication modeling and analysis. Many fab shops use this tool for impedance prediction, so it is easy to stay in sync with them during the HLD stage of your project. Plus, it has the added benefit of modeling transmission loss and exporting Sparameters in touchstone format for further channel modeling in other tools.
Because Polar Si9000 assumes all the reference planes have the same roughness, it only allows Rz roughness parameters to be inputted for the matte and drum side of the signal trace. The best we can do, is take the average roughness of Rz1,Rz2 and Rz3,Rz4:
Simulation Correlation
When Dkeff due to roughness values were used instead of published Dk values, the new impedance prediction is 48.24 ohms, as shown in Figure 6.
Figure 6 Polar Si9000 impedance prediction with Dkeff due to roughness
Dkeff/Df for H1, H2 was then inputted into the causal dielectric model at 10GHz, as shown in Figure 7 (left), while Rz_{matte}, Rz_{drum} was inputted into the CannonballHuray model (right).
Figure 7 Causal Dkeff/Df dielectric and CannonballHuray roughness model input panels in Polar Si9000
After a 6inch transmission line was simulated, the Sparameters were exported in touchstone format. Keysight Pathwave ADS [10] was used for further processing and analysis.
Figure 6 compares simulated insertion loss vs deembedded reflectionless generalized modal (GM) Sparameter measurements, provided by Wildriver Technology [7]. As you can see there is excellent correlation without fitting to measured data!
Figure 8 HLD Insertion Loss simulation correlation for as designed stackup from data sheet and stackup parameters
Figure 9 plots simulated Dkeff vs measurements. At 10 GHz, simulated Dkeff is 0.105 (2.8%) lower than measured value. Without actual crosssection microscopic measurements, it is difficult to conclude if the published Dk is wrong, or if there is process variation with roughness parameters used in the model.
But it is also interesting to note that measured Dkeff is not a constant value over frequency, as shown in the ITera® MT40 Dk/Df tables. Instead Figure 9 reveals it varies over frequency, so the Dk/Df data sheet numbers are suspect.
Regardless, for the HLD modeling process, the simulation results are within acceptable tolerance.
Figure 9 HLD Dkeff simulation correlation for as designed stackup
Exploring the Effects of Alternate Foil Roughness
Now that we have good correlation to measurements, we can repeat the HLD modeling process to explore different foil roughness options. Figure 10 summarizes the thickness of core, prepreg and signal trace for VLP2/VLP2 foil (top) and VLP1/VLP1 foil (bottom). Note that photos are for illustrative purposes only and are not actual crosssections from CMP PCB.
Respective Dkeff, and CannonballHuray roughness parameters were recalculated with same steps as VLP2/RTF case above.
Figure 10 Alternate foil options simulated for whatif loss comparison. Top is VLP2/VLP2 foil parameters for all copper layers and bottom is VLP1/VLP1 foil parameters for all copper layers. Note: Photos are for illustrative purposes only and are not actual crosssection from CMP PCB. Surface roughness pictures source: Circuit Foil [8]
Figure 11 presents the simulation results of all three scenarios. As expected. when the reference plane foil roughness went from RTF/VLP2 to VLP2/VLP2 there was improvement. At 14 GHz it was 0.5 dB and at 28GHz it was 1 dB improvement.
When VLP1/VLP1 foil was used, it was further improved by 0.8 dB and 1.7 dB at 14 GHz and 28 GHz respectively. So if your design is loss sensitive, you might want to consider VLP1 foil option.
When we compare Dkeff plots, we see effective Dk approaches actual Dk/Df data sheet values in the tables when smoother copper is used, as expected [5].
Since Dkeff was derived by phase delay, propagation delay will be affected by rougher copper.
Figure 11 Whatif simulation comparison of VLP2/RTF, VLP2/VLP2, VLP1/VLP1 foil options and their effect on insertion loss and Dkeff
Conclusions
1. Roughness of reference planes make a significant difference in loss and phase delay, especially if one of the reference planes is RTF. If loss is important then all highspeed reference planes should have the same foil roughness specified
2. Heuristic HLD modeling method is a useful and accurate way to determine prefabrication impedance and loss predictions using data sheet parameters.
3. Published Dk from ITera® MT40 Dk/Df data sheet tables is not a flat constant over frequency.
4. Confirmed Rz JIS is the right parameter to use from Circuit Foil data sheet, instead of Rz ISO.
Acknowledgements
· Al Neves, CTO Wildriver Technology, for providing the custom modeling platform design details and measured data for the case study.
· Michael Gay, Director Business Development – Strategic Accounts at Isola Group, for providing foil supplier’s data sheets used on ITera® MT40 laminates.
References
[1] B. Simonovich, “Heuristic Modeling of Transmission Lines due to Mixed Reference Plane Foil Roughness in Printed Circuit Board Stackups”, White Paper, Lamsim Enterprises Inc.
[2] B. Simonovich, “Practical Method for Modeling Conductor Surface Roughness Using The Cannonball Stack Principle”, White Paper, Lamsim Enterprises Inc.
[3] L. Simonovich, “Practical method for modeling conductor roughness using cubic closepacking of equal spheres,” 2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), 2016, pp. 917920, doi: 10.1109/ISEMC.2016.7571773.
[4] L. Simonovich, “PCB Interconnect Modeling Demystified”, DesignCon 2019, Proceedings, Santa Clara, CA, 2019
[5] B. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”. DesignCon 2017, Proceedings, Santa Clara, CA, 2017
[6] Isola Group S.a.r.l., 3100 West Ray Road, Suite 301, Chandler, AZ 85226, URL: http://www.isolagroup.com/
[7] Wild River Technology LLC 8311SW Charlotte Drive Beaverton, OR 97007, URL: https://wildrivertech.com/
[8] Circuit Foil 6 Salzbaach, 9559 Wiltz, Grand Duchy of Luxembourg URL: https://www.circuitfoil.com/portfolio/
[9] Polar Instruments Si9000e [computer software] Version 2018, URL: https://www.polarinstruments.com/index.html
[10] Keysight Pathwave Advanced Design System (ADS) [computer software], (Version 2021 update2). URL:http://www.keysight.com/en/pc1297113/advanceddesignsystemads?cc=US&lc=eng.
[11] IPCTM650 Test Methods Manual 2.2.17A, Surface Roughness and Profile of Metallic Foils (Contacting Stylus Technique), 2/2001 Rev. A
[12] IPCTM650, 2.5.5.5, Rev C, Test Methods Manual
Characteristic Impedance – Where SI/PI Worlds Collide
Originally published Signal Integrity Journal, February 23, 2021
Signal and power integrity (SI/PI) simulations, measurements, and analysis usually live in two different worlds, but occasionally these worlds collide. One such collision occurs when we refer to characteristic impedance, Z_{0}. Traditionally the PI world lives in the frequency domain while the SI world lives in the time domain.
When designing a power distribution network (PDN) in the PI world, we are mostly interested in engineering a flat impedance below a target impedance from DC to the highest frequency components of the transient current. Practically this is achieved with a network of capacitors with different values connected to the respective power planes as shown in Figure 1.
Figure 1 A simplified model of a typical PDN courtesy [1].
In the real world, there is no such thing as an ideal capacitor. There are always parasitic elements known as equivalent series inductance (ESL) and equivalent series resistance (ESR). Physical characteristics of the PCB, like component mounting inductance, plane spreading inductance, via and BGA ball inductance, along with voltage regulator module (VRM) characteristics also contribute to the impedance profile. When connected together, the interaction of capacitors and parasitic inductance and resistance create a transfer impedance profile with resonant peaks and antiresonant nulls as shown in Figure 2.
The transfer impedance between the VRM and the load is calculated and plotted in the frequency domain with a loglog scale. The resulted impedance curve is then compared to the target impedance (Z_{target}), which is estimated based on the allowed noise ripple and maximum transient current. The flat target impedance is frequency independent in the analysis.
Figure 2 Impedance profile of the PDN as viewed from the pads on the die power rail courtesy [1].
Resonant peaks are due to ESL of one capacitor connected in parallel with another capacitor. Antiresonant nulls are due to the series combination of ESR, ESL, and C for each capacitor. Different capacitor values will have antiresonant nulls at different frequencies.
But in the PI world, there is a rarely talked about characteristic impedance, Z_{0}. In this case, it refers to the geometric average of the reactive impedance of a capacitor (XC) and reactive impedance of an inductor (XL).
Equation 1
At resonance, XL and XC intersect at the characteristic impedance and are equal as shown in Figure 3.
Figure 3 Inductive and capacitive reactance plot of ideal inductor and capacitor versus frequency. At resonance, XL and XC are equal and intersect at the characteristic impedance, Z_{0}. Simulated with Pathwave ADS [6].
This is a very important observation, and it is where the SI/PI worlds collide.
In the SI world, characteristic impedance, Z_{0 }refers to the instantaneous ratio of the voltage to current of a wave front traveling along a uniform transmission line without reflections. For an infinitely long uniform transmission line, Z_{0 }equals the input impedance.
The characteristic impedance of a lossy transmission line is defined as:
Equation 2
Where R is resistance per unit length; G is conductance per unit length; L is inductance per unit length; and C is capacitance per unit length. For a lossless uniform transmission line, R and G are assumed to be zero and thus the characteristic impedance is reduced to:
Equation 3
Time Domain Reflectometer
In the SI world, we usually use a time domain reflectometer (TDR) to measure characteristic impedance, but more often than not, the measured impedance we get is not what we predicted with a 2D field solver. Many 2D field solvers used by most PCB FAB shops only calculate the lossless characteristic impedance of the crosssectional geometry at a single frequency, defined by the dielectric constant (D_{k}). It has no input for conductor resistivity, dielectric loss, or how long the conductor(s) is.
So the issue is: we design the stackup, then do our SI modeling analysis based on stackup parameters and matching characteristic impedance. But the PCB FAB shop will often adjust the line width(s), over and above normal process variation, so that when measured, the impedance will fall within the specified tolerance, usually +/10 percent.
Part of the problem lies with the method used to take the measurements. Most PCB FAB shops follow IPCTM650 Test Methods Manual [2]. But it has limitations because Z_{0 }measured is derived and cannot be directly measured. The reason is the measurements include resistive and dielectric losses, up to the point where the measurement takes place along the TDR plot.
Resistive loss often results in a slow monotonic rise in the impedance profile, shown in the example TDR plot of Figure 4. IPCTM650 specifies a measurement zone between 3070 percent to avoid probing induced ringing affecting the measurements. Most PCB FAB shops will measure an average impedance over this range, usually in the center region.
Depending on the linewidth, thickness and dielectric dissipation factor (D_{f}), the slope of the monotonic rise will vary.
Figure 4 Example TDR plot showing slow monotonic rise in impedance due to resistive losses and IPCTM650 measurement zone.
The problem is that the IPCTM650 test method was last updated back in 2004, when higher dielectric loss, along with wider line widths and thicker copper weights, were used more often. A higher D_{f} tends to compensate for resistive loss by flattening the slope as shown in Figure 5.
On the bottom left is a simulated TDR plot using a high loss dielectric with D_{f} = 0.024. The right side has the exact same geometry properties except D_{f} = 0.004. The average impedance, when measured at the 50 percent point, is 49.8 Ohms on the left side vs. 51.4 Ohms on the right side. We also confirm flatter slope for high loss material.
The actual characteristic impedance predicted by a Polar SI9000 2D field solver [5] in Figure 5 is 49 Ohms. For higher loss material, measuring within the measurement zone would pass without any issues. But for lower loss material, the resistive loss dominates and measuring within the measurement zone will give ~5 percent higher impedance reading compared to the higher loss material. The correct measurement point for Z_{0 }is, in fact, the initial dip, equivalent to the field solver prediction. Depending on the tolerance specified, this may affect yield and cost.
Figure 5 Characteristic impedance prediction by Polar SI9000 2D field solver [5] (top). Simulated 2 inch TDR plots using a high loss dielectric (bottom left) vs. low loss dielectric with exactly the same geometry (bottm right). A higher Df compensates for higher resistive loss thereby flattening the curve. Simulated with Pathwave ADS [6].
Today, with the push to low loss dielectric and finer line widths with thinner copper weights, measuring the true transmission line characteristic impedance using a TDR becomes more challenging. This is even more so when measuring differential impedance, because a change in line width space geometry can have a more profound effect on measured differential impedance.
Using the first article build of a new design, as an example, let’s assume the correct characteristic impedance, when measured at the beginning of the slow monotonic rise of a TDR plot, is on the high end of nominal +10 percent tolerance. Let’s say it’s 54 Ohms. But because of the low loss dielectric and high resistive loss, the TDR measurement at the midpoint is now reading 5% higher at 57 Ohms. This would imply the impedance is now out of spec over nominal and the board would be scrapped.
The PCB fab shop will then go back and adjust the linewidth accordingly for the next build to bring the measurement within range to their measurement set up. Doing this effectively lowers the true nominal characteristic impedance!
If subsequent manufacturing variations pushes the measured impedance within the measurement zone on the low end of the 10 percent tolerance, say 44 Ohms, then the true characteristic impedance, if measured at the initial dip, will be 5 percent lower at 42 Ohms and be out of spec. But the board will pass because it was measured following IPCTM650 test method.
2port Shunt Measurement
But what if there were another way? What if we could borrow impedance measuring techniques from the PI world to determine the true transmission line characteristic impedance in the SI world? Well there is. Enter the 2port shunt measurement technique.
For example, in the PI world, to measure ESL and ESR of a chip capacitor, of a device under test (DUT), a 2port shunt measurement is often used. It is much like the 4point Kelvin measurement technique used to measure very low DC resistance.
The 2port shunt measurement is usually done with a 2port vector network analyzer (VNA). Port 1 of the VNA sends out a calibrated signal, and port 2 measures the voltage signal across the DUT. Often an isolation transformer is also used to break the inherent ground loop when measuring ultralow impedances [3].
Once the measurements have been completed and Sparameters saved in touchstone format, further analysis can be done in your favorite SPICE simulator. Figure 6 is a generic schematic using popular Pathwave ADS [5] that can be used for 2port shunt analysis.
When port 1 and port 2 are connected to port 1 of the DUT and port 2 of the DUT is grounded, the impedance of the DUT can be determined by [3];
Equation 4
Figure 6 Generic Pathwave ADS [6] schematic used for 2port shunt analysis on a S2P file for DUT.
If we replace the DUT in Figure 6 with a capacitor and inductor, we get an impedance plot shown in Figure 7. As we saw earlier, when we take the geometric average of the inductive and capacitive reactance using Equation 1, we get the characteristic impedance. If we apply Equation 4 to the results of a 2port shunt measurements of a capacitor and inductor, we get exactly the same results as shown in the top of Figure 7.
When we replace the capacitor and inductor with a Sparameter file of a transmission line model from Figure 5, we get the plot shown at the bottom of Figure 7. Except for the resonant nulls and peaks, up to a certain frequency, the impedance of a transmission line looks like the impedance of a capacitor when the farend is open, and looks like the impedance of an inductor when the farend is shorted. And because of that, this is where the two worlds collide!
If we take the geometric average of the impedance when the farend is open (Z_{open}) or shorted (Z_{short}), we get the characteristic impedance at that frequency. We note where the red and blue impedance lines first intersect, is exactly the geometric average characteristic impedance at that frequency.
Also worth noting, the lines intersect at half of the frequency between the peaks and valleys at higher frequencies as well.
Figure 7 Impedance of inductive and capacitive reactance vs. frequency (top) and impedance of a transmission line vs. frequency (bottom) when the farend is open (solid red) compared to when the farend is shorted (solid blue). The intersection of the red and blue lines is exactly the characteristic impedance. Simulated with Pathwave ADS [5].
We can see this more clearly if we replot Figure 7 bottom using a linear scale for the xaxis, as shown in Figure 8. This is a very powerful observation. What this means is that when we measure the impedance half way between a peak and adjacent valley, of either the red or blue plot, it is the characteristic impedance of the transmission line at that frequency.
Thus, only an open or shorted end measurement is all that is needed to determine the characteristic impedance. For example, if we look at the red curve alone, then measure the first resonant null (m14) and adjacent peak (m15), the characteristic impedance (mag(Zopen) is measured exactly at one half the frequency between the two (m16).
Figure 8 Impedance of a transmission line vs. frequency on a linear scale when the farend is open (solid red) compared to when the farend is shorted (solid blue). The intersection of the red and blue lines half way between respective peaks and valleys is the characteristic impedance. Simulated with Pathwave ADS [6].
The first resonant red null and blue peak represent the quarterwave resonant frequency due to open and shorted end. Each respective red null and blue peak following are the odd harmonics of the first quarterwave resonant frequency.
Knowing this, we can now determine the phase or time delay (TD) of the transmission line as being one quarter of the period of the resonant frequency (f_{0}).
Equation 5
Because resonant nulls and peaks occur at the resonant frequency, we can also determine the effective dielectric constant (D_{keff}). Given the speed of light (c) = 11.8 in. per nanosecond, the length of the transmission line (len) in in. and quarterwave resonant frequency (f_{0}), D_{keff} can be determined by:
Equation 6
CMP28 Case Study
Figure 9 Photo of a portion of CMP28 test platform courtesy of Wildriver Technology [8] used for measurement validation.
To test the accuracy of this method, measured data from a CMP28 test platform, shown in Figure 9, was used for measurement validation. Sparameter (s2p) files from 2 inch and 8 inch singleended stripline traces were provided as part of CMP28 design kit courtesy of Wildriver Technologies [8]. The 6inch transmission line segment Sparameter data was deembedded courtesy of AtaiTec Corporation [9].
The characteristic impedance, based on trace geometry and stackup parameters, was modeled in Polar SI9000 [5]. Using D_{k }from data sheet tables @ 10GHz, and correcting for conductor roughness [10], the characteristic impedance predicted was 49.66 Ohms, as shown in Figure 10.
Figure 10 Polar SI9000 fieldsolver [5] characteristic impedance prediction of CMP28 trace geometry.
Touchstone Sparameter DUT files were connected with farend open, shorted, and terminated as shown in Figure 11. The TDR plot, with farend terminated, shows an impedance of 50.57 Ohms, when measured at the initial peak. Then it takes an immediate dip to approximately 50 Ohms before continuing with a slow monotonic rise with some ripples. If the DUT was a uniform trace, with connector discontinuity deembedded, we would not see the initial peak followed by the dip. This signature strongly suggests that the DUT is not uniform and thus it is very difficult to determine the actual characteristic impedance using IPCTM650 test method alone.
But only after taking 2port shunt measurements can we confirm the true characteristic impedance. As shown, Zoavg is 50.68 Ohms where the red and blue curves cross at 122.5 MHz, and confirms the true measurement point in the TDR plot is the initial peak. Both are about 1 Ohm higher compared with 2D field solver results in Figure 10.
If the length of the transmission line simulated above is 6 in. and f_{0 }=248.2 MHz, then TD = 1 ns and D_{keff} = 3.92, using Equation 5 and Equation 6 respectively.
Figure 11 Measured results from a CMP28 test platform design kit, courtesy of Wildriver Technology [8].
But wait a minute. Why is D_{keff} is higher than what was used in the 2D field solver in Figure 10?
One reason is due to process variation of the material and fabrication. The actual D_{keff} is determined by the final thickness of dielectric and the roughness of the copper, which also increases inductance affecting TD [10] [11]. But the main reason is D_{k }is frequency dependent and the value used in the field solver was at 10 GHz, based on laminate supplier’s D_{k}/D_{f} tables.
Since TD, ultimately determines D_{keff}, it does not represent the intrinsic property of the dielectric material. Because D_{keff} varies with frequency, it was calculated at the first resonant null of 248.2 MHz, which is at a much lower frequency for D_{k} than the frequency originally used to select D_{k }in the field solver.
As can be seen in Figure 12, a simulated vs. measured 2port shunt frequency plot, with farend open and shorted, we get exactly the same information, compared to the traditional method used to validate characteristic impedance and D_{keff}.
If we measure the 39^{th} odd harmonic frequency (H) at 9.884GHz for the resonant null closest to 10GHz, equating to the value of D_{k} used in Polar Si9000 2D field solver, D_{keff} can be calculated with Equation 7:
Equation 7
The bottom right plot of Figure 12, shows D_{keff} simulated (blue) vs. measured (red). As we can see, the measured D_{keff} at 248.7 MHz is 3.94; pretty much agreeing with our earlier calculation of 3.92 using Equation 6. Furthermore, when we compare D_{keff} = 3.76 at 9.884 GHz, it agrees with our calculation for the 39^{th} harmonic frequency from Equation 7. The reason there is still a slight difference in D_{keff} is because the added delay due to inductance due to roughness [11] was not factored into the simulated model.
The bottom left is a TDR plot that shows measured impedance (red) vs. simulated (blue) over time. The marker at the beginning of the initial dip (m6) represents the characteristic impedance with highest frequency harmonics included in the incident step edge of TDR waveform. The marker at the end (m16) represents the impedance at twice the TD with high frequency harmonics attenuated due to dispersion of the lossy dielectric and resistance of trace length.
When we measure Zoavg_meas impedance of DUT at 9.884GHz, at the top plot of Figure 12, it agrees pretty well with the simulated and measured TDR plot at the initial step.
Figure 12 Comparison of PI world 2port shunt measurement results for transmission line characteristic impedance and D_{keff} compared to traditional SI world measurement results. Top plot is the 2port shunt simulated vs. DUT impedance measurements at the fundamental and 39^{th} harmonic frequencies. Bottom left is beginning and end impedance measurements on TDR plot. Bottom right measuring equivalent D_{keff} at fundamental and 39^{th} harmonic frequencies.
Summary and Conclusion
Sometimes, when SI and PI worlds collide, we get the best of both worlds. By borrowing a simple 2port shunt impedance measuring technique from the PI world, we have another tool at our disposal to measure true characteristic impedance, TD, and effective D_{k} from a uniformly designed transmission line in the SI world. The advantage is, unlike a TDR measurement, measuring true characteristic impedance using 2port shunt method is not influenced by resistive or dielectric losses.
References

L. Smith, S. Sandler, E. Bogatin, “Target Impedance Is Not Enough,” Signal Integrity Journal, Vol. 1, Issue 1, January 2019; URL: https://www.signalintegrityjournal.com/ext/resources/MEDIAKIT2019/January2019PrintIssue/SIJJanuary2019Issue_eBook_V2.pdf

IPCTM650 Test methods Manual, Number 2.5.5.7, “Characteristic Impedance of Lines on Printed Boards by TDR”, Rev. A, March, 2004

I. Novak, J. Millar, “FrequencyDomain Characterization of Power Distribution Networks,” Artech House, 685 Canton St., Norwood, MA, 02062, 2007.

Pathwave Advanced Design System (ADS) [computer software], Version 2021, URL: http://www.keysight.com/en/pc1297113/advanceddesignsystemads?nid=34346.0&cc=CA&lc=eng

Polar Instruments Si9000e [computer software], Version 2018, URL: https://www.polarinstruments.com/index.html

Keysight Pathwave Advanced Design System (ADS) [computer software], Version 2021, URL: http://www.keysight.com/en/pc1297113/advanceddesignsystemads?cc=US&lc=eng.

E. Bogatin, “Bogatin’s Practical Guide to Transmission Line Design and Characterization for Signal Integrity”, Artech House, 685 Canton St., Norwood, MA, 02062, 2020

Wild River Technology LLC 8311 SW Charlotte Drive Beaverton, OR 97007. URL: https://wildrivertech.com/

AtaiTec Corporation, URL: http://ataitec.com/products/isd/

B. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness“, DesignCon 2017 proceedings, Santa Clara CA.

V. DmitrievZdorov, B. Simonovich, I. Kochikov, “A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics”, DesignCon 2018 proceedings, Santa Clara, CA.

I. Novak et al, “Determining PCB Trace Impedance by TDR: Challenges and Possible Solutions”, DesignCon 2013 proceedings, Santa Clara, CA.

S. Sandler, “Easy trick to measure plane impedance with VNA”, EDN Asia, 2014, URL: https://archive.ednasia.com/www.ednasia.com/STATIC/PDF/201410/EDNAOL_2014OCT21_TEST_TA_01.pdf%3FSOURCES=DOWNLOAD
Singleended to MixedMode Conversions
Originally published in Signal Integrity Journal Magazine, July 2020
Signal Integrity (SI) engineers almost always have to work with Sparameters. If you haven’t had to work with them yet, then chances are you will sometime in your SI career. As speed moves up in the doubledigit GB/s regime, many industry standards are moving to serial linkbased architectures and are using frequency domain compliance limits based on Sparameter measurements.
A vector network analyzer (VNA) is the test instrument of choice to measure Sparameters from a device under test (DUT). By definition, each Sparameter (S_{ij}) is the ratio of the sine wave voltage coming out of a port to the sine wave voltage that was going in to a port (Equation 1). Each Sparameter is complex with a magnitude and a phase.
Equation 1
Sufficed to say, for mathematical reasons, the indexes refer to the port in which the voltages are coming or going. This is counter intuitive to our normal train of thought and is important to be cognisant of this relationship when working with Sparameters.
Singleended Sparameters
Figure 1 shows an example of a 1Port, 2Port and 4Port DUTs and their respective Sparameter matrices representing uniform transmission lines with respective port index labelling. Each Sparameter in the matrix are singleended measurements from one port to another.
A 1Port DUT has one Sparameter (S_{11}) shown in red. It is the ratio of the voltage coming out of Port 1 to the voltage going into Port 1. As a measure of reflected energy out of Port 1, it is also known as return loss (RL)
A 2Port DUT has 4 Sparameters shown in blue. Sparameters with the same index subscript numbers, i.e. S_{11,} S_{22} are RL. Sparameters with alternate index subscript numbers, are a measure of transmitted energy and is the ratio of the voltage coming out of a Port to the voltage going into the opposite Port. It is also known as insertion loss (IL). For example, S_{12} is the ratio of the voltage coming out of Port 1 to the voltage going into Port 2, whereas S_{21} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 1.
Figure 1 From left to right examples of 1Port (Red), 2Port (Blue), 4Port (Black) DUTs and their respective Sparameter matrices.
A 4Port DUT has 16 Sparameters, divided into 4 quadrants, shown in black. As you can see the number of Sparameter combinations is the square of the number of ports. In this example, the top left quadrant 1 and bottom right quadrant 4 are the same as individual 2Port DUTs with different port indices. They are described as:
Quadrant 1:

S_{11} is the ratio of the voltage coming out of Port 1 to the voltage going into Port 1. It is the RL out of Port 1.

S_{12} is the IL and is the ratio of the voltage coming out of Port 1 to the voltage going into Port 2. It is the IL from Port 2 to Port 1.

S_{21} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 1. It is the IL from Port 1 to Port 2. For a uniform transmission line, S_{21} = S_{12}.

S_{22} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 2. It is the RL out of Port 2. For a uniform transmission line, S_{22} = S_{11}.
Quadrant 4:

S_{33} is the ratio of the voltage coming out of Port 3 to the voltage going into Port 3. It is the RL out of Port 3

S_{34} is the ratio of the voltage coming out of Port 3 to the voltage going into Port 4. It is the IL from Port 4 to Port 3

S_{43} is the ratio of the voltage coming out of Port 4 to the voltage going into Port 3. It is the IL from Port 3 to Port 4. For a uniform transmission line, S_{43} = S_{34}.

S_{44} is the ratio of the voltage coming out of Port 4 to the voltage going into Port 4. It is the RL out of Port 4. For a uniform transmission line, S_{44} = S_{33}
Sparameters in the top right quadrant 2 and bottom left quadrant 3 describe the nearend and farend coupling of the respective ports. When unwanted coupling happens at the nearend, it is referred to as nearend cross talk, or NEXT. When it happens at the farend, it is known as farend crosstalk, or FEXT.
Quadrant 2:

S_{13} is the ratio of the voltage coming out of Port 1 to the voltage going into Port 3. It is the coupling or NEXT from Port 3 to Port 1.

S_{14} is the ratio of the voltage coming out of Port 1 to the voltage going into Port 4. It is coupling or FEXT from Port 4 to Port 1.

S_{23} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 3. It is coupling or FEXT from Port 3 to Port 2.

S_{24} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 4. It is coupling or NEXT from Port 4 to Port 2.
Quadrant 3:

S_{31} is the ratio of the voltage coming out of Port 3 to the voltage going into Port 1. It is the coupling or NEXT from Port 1 to Port 3.

S_{32} is the ratio of the voltage coming out of Port 3 to the voltage going into Port 2. It is coupling or FEXT from Port 2 to Port 3.

S_{41} is the ratio of the voltage coming out of Port 4 to the voltage going into Port 1. It is coupling or FEXT from Port 1 to Port 4.

S_{42} is the ratio of the voltage coming out of Port 4 to the voltage going into Port 2. It is coupling or NEXT from Port 2 to Port 4.
Although there is no industry standard for labeling a 4 or more port DUT, a practical way is to use the port order shown so that the 2Port DUT is a subset of the top left quadrant of the 4Port DUT. When you do this, the port order labeling is consistent as you increase the number of ports; with odd ports on the left and even ports on the right. S_{12} and S_{21} always describe the IL terms; while S_{13 }and S_{31} define the NEXT terms.
But sometimes 3^{rd} party 4port Sparameters are labeled with ports 1 and 2 are on the left side, while ports 3 and 4 are on the right side. In this configuration, S_{31} and S_{42} are now the IL terms. This is counter intuitive when moving from 2Port to 4 or more Port DUT and leading to potential confusion when cascading Sparameters to build a channel model, or converting to mixedmode Sparameters. Whenever you get Sparameter files from 3^{rd} party, it is always prudent to test it and compare IL plots against port order to ensure you are using them correctly.
Typically, 4port Sparameters are saved in Touchstone format with a .snp extension, where n is the number of ports. Many Electronic Design Automation (EDA) and circuit simulation software tools allows you to view and plot Sparameters from Touchstone files.
Figure 2 is a schematic of a 4port Sparameter component used in Keysight ADS. When the component is linked to appropriate .s4p touchstone file and ports connected as shown, the 16port Sparameter matrix can be plotted and analyzed.
Figure 2 Keysight ADS schematic used to plot 4Port singleended Sparameters.
The 1port and 2port Sparameters are included in the same plot as the 4port Sparameters plotted in Figure 3. The top left (red) and bottom right (green) quadrants plot the return loss (RL) and insertion loss (IL), while the top right (blue) and bottom left (magenta) quadrants plot the NEXT and FEXT.
Figure 3 An example of 4Port Sparameter singleended plots of a uniform transmission line.
Mixedmode Sparameters
SI engineers often have to check channel models and Sparameter measurements against industry standard compliance plots. Many of those plots are in terms of mixedmode Sparameters, which means the singleended measurements need to be converted to mixedmode matrix.
Two singleended transmission lines with coupling are also known as a differential pair, as shown in Figure 4. When we talk about singleended transmission lines with coupling, we are usually interested in their singleended properties like characteristic impedance (Zo), phase delay, and NEXT/FEXT relationships as described above.
But when we talk about a differential pair, we are interested in the mixedmode Sparameters like differential and common signals and how they interact within the pair. Because we are describing the exact same interconnect, they are equivalent.
When describing a differential pair, there are only four possible outcomes in response to an input signal as defined by the mixedmode Sparameter matrix:

A differential signal enters the differential pair and a differential signal comes out

A differential signal enters the differential pair and a common signal comes out

A common signal enters the differential pair and a differential signal comes out

A common signal enters the differential pair and a common signal comes out
Figure 4 Singleended vs mixedmode Sparameter matrices of two coupled transmission lines.
Mixedmode Sparameters in each quadrant are described as:
SDD Quadrant (Red):

SDD_{11} is the ratio of the differential signal coming out of Port 1 to the differential signal going into Port 1. It is the differential RL out of Port 1.

SDD_{12} is the ratio of the differential signal coming out of Port 1 to the differential signal going into Port 2. It is the differential IL from Port 2 to Port 1.

SDD_{21} is the ratio of the differential signal coming out of Port 2 to the differential signal going into Port 1. It is the differential IL from Port 1 to Port 2.

SDD_{22} is the ratio of the differential signal coming out of Port 2 to the differential signal going into Port 2. It is the differential RL out of Port 2.
SDC Quadrant (Blue):

SDC_{11} is the ratio of the differential signal coming out of Port 1 to the common signal going into Port 1.

SDC_{12} is the ratio of the differential signal coming out of Port 1 to the common signal going into Port 2.

SDC_{21} is the ratio of the differential signal coming out of Port 2 to the common signal going into Port 1.

SDC_{22} is the ratio of the differential signal coming out of Port 2 to the common signal going into Port 2.
SCD Quadrant (Magenta):

SCD_{11} is the ratio of the common signal coming out of Port 1 to the differential signal going into Port 1.

SCD_{12} is the ratio of the common signal coming out of Port 1 to the differential signal going into Port 2.

SCD_{21} is the ratio of the common signal coming out of Port 2 to the differential signal going into Port 1.

SCD_{22} is the ratio of the common signal coming out of Port 2 to the differential signal going into Port 2.
SCC Quadrant (Green):

SCC_{11} is the ratio of the common signal coming out of Port 1 to the common signal going into Port 1.

SCC_{12} is the ratio of the common signal coming out of Port 1 to the common signal going into Port 2.

SCC_{21} is the ratio of the common signal coming out of Port 2 to the common signal going into Port 1.

SCC_{22} is the ratio of the common signal coming out of Port 2 to the common signal going into Port 2.
Singleended Sparameters, with port order shown in Figure 4, can be mathematically converted into mixedmode Sparameters using equations shown in Table 1.
Alternatively, Keysight ADS can simplify this process using equations on 4Port singleended or using 4port Balun components, as shown in Figure 5.
Figure 5 Keysight ADS schematic used to convert from 4Port singleended to 2Port mixedmode Sparameters using equations or 4Port Balun components. Differential and common port numbering as D1, D2, C1, C2 respectively.
Figure 6 plots mixedmode Sparameters from equations in Table 1. Each quadrant is color coded to coincide with the respective table quadrants.
Figure 6 An example of 4Port Sparameter mixedmode plots of a differential transmission line.
References:
[1] M. Resso, E. Bogatin, “Signal Integrity Characterization Techniques”, International Engineering Consortium, 300 West Adams Street, Suite 1210, Chicago, Illinois 606065114, USA, ISBN: 9781931695930
https://www.amazon.com/SignalIntegrityCharacterizationTechniquesBogatinebook/dp/B07P9277WY/ref=sr_1_fkmr0_1?keywords=bogaitn+resso&qid=1581289220&sr=81fkmr0
[2] A. Huynh, M. Karlsson, S. Gong (2010). MixedMode SParameters and Conversion Techniques, Advanced Microwave Circuits and Systems, Vitaliy Zhurbenko (Ed.), ISBN: 9789533070872,InTech, Available from: http://www.intechopen.com/books/advancedmicrowavecircuitsandsystems/mixedmodesparametersandconversiontechniques.
[3] Alfred P. Neves, Mike Resso, and ChunTing Wang Lee, “Sparameters: Signal Integrity Analysis in the Blink of an Eye”, Signal Integrity Journal, https://www.signalintegrityjournal.com/articles/432sparameterssignalintegrityanalysisintheblinkofaneye
Keysight Advanced Design System (ADS) [computer software], (Version 2020). URL: http://www.keysight.com/en/pc1297113/advanceddesignsystemads?cc=US&lc=eng.
How Authorship Advances Your Career and Become an Industry Influencer
So how can authorship advance your career and lead to becoming an industry influencer?
Well first of all, it offers a chance for deep learning of a subject matter. When you have to capture your thoughts on paper, you suddenly realize you may not know as much about the subject as you think you know. It forces you to do more research on the topic so that the information you are trying to covey is accurate.
It demonstrates thought leadership at your work and the industry. You become the subject matter expert on that topic. And over time, the path to your desk, is worn from all the traffic to your cubicle. If you are self employed as a consultant, it eventually leads to more business opportunities.
It inspires your coworkers and peers to become subject matter experts in their own right by leading by example. Being a subject matter expert offers opportunities to work with other subject matter experts in your company on leading edge projects.
It builds your personal brand. By writing papers and presenting at conferences you become known in the industry from the work you have accomplished and shared.
It gives you a chance to network, meet and collaborate with new people with like interests in the industry. It’s a snowball effect. I can’t even begin to count now many new people from around the world I have met since starting to publish and attend conferences.
It builds self confidence. Everyone at one time or another has had a fear of public speaking. By presenting your work in an audience of your peers, that fear of public speaking begins to dissipate.
Personal pride. Just like a “runner’s high”, you get a dopamine hit every time you see your work published or you present. There is no greater feeling, after spending an enormous amount of time writing your paper, making your slides perfect, continually practicing your presentation, to anyone who will listen, then finally delivering to an audience. It becomes addictive so you will want to continually publish and present your work.
It leaves a lasting legacy of part of your life’s work behind. Let’s face it, our time is limited on this earth. By publishing your work, it inspires future generations in their research, just like past generations of authors have inspired many of today’s authors, including myself.
You don’t have to start big. A personal blog, web site is a good place to begin. Trade journals, and online magazines in your industry are always looking for quality content that is relevant to their readers.
Formal societies, like IEEE, is a more recognized venue and is peer reviewed. Submitting a paper to industry conferences is another way and offers the opportunity to present your work. And finally, the ultimate, is publishing a book.
Once your work is published, then you need to self promote what you have done. Use social media like LinkedIn, Facebook, Twitter or any other platform. You eventually will build a following, who will react and share your posts and soon become an industry influencer.
Finally, I’d like to leave you with this final thought. Being Canadian, our national pastime is Hockey. We usually have a hockey analogy for almost anything. Everyone who follows hockey knows Wayne Gretzky, the greatest hockey player of all time. One of his famous quotes was, “You always miss 100% of the shots you don’t take.” And likewise, if you do not take the shot of writing a paper, book or an article, you cannot become a subject matter expert or industry influencer.
Go for it!
DesignCon: The Place to Go to Find Out What You Don’t Know You Don’t Know
In engineering, it’s what you don’t know you don’t know that can ruin your day and keep you awake at nights. Especially after you get your prototypes in the lab, or worse, field returns from the customer. This is one reason why I have been going to DesignCon for the last few years, and this year has been no exception.
One of the sessions I attended was the Power Integrity Boot Camp, hosted by Heidi Barnes, from Keysight Technologies, and Steve Sandler from Picotest. What I didn’t know I didn’t know from this boot camp was how important it was to match the voltage regulator module (VRM) output impedance to the power distribution network (PDN) input impedance. Steve and Heidi recently presented a webcast which was a condensed version of the DesignCon Bootcamp session. If you are involved in PDN design, this webcast will provide you with an introduction to power integrity and give some insight into the latest tips and techniques to achieve flat impedance designs.
Of course, I always try and attend some of Eric Bogatin’s presentations because I always come away with something I didn’t know I didn’t know. Eric is an Adjunct Professor at the University of Colorado and the Dean of Teledyne LeCroy’s SI Academy. He was honored at this year’s DesignCon with a welldeserved Engineer of the Year Award.
The speed training event, he hosted along with Larry Smith from Qualcomm, was on the top of my list to attend. During the session, Eric described the most critical feature of PDN design was controlling the “Bandini Mountain”.
The Bandini Mountain expression has often been used to describe a tall pile of manure. Originally it referred to a 100 foot tall mound of fertilizer built by the Bandini Fertilizer Company in California prior to the 1984 Los Angeles summer Olympics for advertisement purposes. When the company went bankrupt, this large mound of smelly fertilizer was left behind and everyone wished it would go away.
Because of this little bit of trivia, it was the term coined by the late Steve Weir to describe the large resonant frequency peak formed by the parallel combination of the on die capacitance and the package lead inductance, as seen from the die looking into the PDN. This peak is inherent in all PDN networks, and almost impossible to get rid of. And like the Bandini Mountain, it was something PDN designers wish could go away.
Steve used to be a regular Icon at past DesignCons until his sudden passing in August 2015. Steve was one of the smartest guys I knew, and I always looked forward to catching up with him when I visited DesignCon. If you knew Steve, like many of us did, you know that he often had very humorous analogies to describe empirical or simulated results. This example is no exception. He will be sorely missed for his contribution the engineering community.
What I learned I didn’t know I didn’t know from Eric’s and Larry’s presentation was that every PDN design will have a “Bandini Mountain”, and unless you know what frequency it is at, and take steps to try and mitigate its peak, it could ruin your day! Even though the system seems to “work” in the lab, it doesn’t mean it’s robust enough and won’t fail under certain operating conditions in the field that affect the transient currents.
Eric has made available the speed training slides and the associated video off his SI Academy web site. If you look under Video Recordings, Presentations and Webinars (VRPW) and scroll down to the bottom you will find the slides titled, “VRPW6035 DesignCon 2016 PDN speed training”. If you watch the whole presentation you will learn all about the “PDN Bandini Mountain” and techniques to mitigate its effects. And while you are there, have a look at the many other videos and presentations available for free and by paid subscription.
Eric and Larry have also coauthored a new book, scheduled for release in June 2016 titled, “Principles of Power Integrity for PDN Design”. I can’t wait to buy this book to add to my library so that I can find out more of what I don’t know I don’t know about PDN design. If it’s anything like Eric’s other books, I won’t be disappointed.
Introduction
Welcome to my Blog! I am Bert Simonovich, founder and president of Lamsim Enterprises Inc. I graduated in 1976 from Mohawk College of Applied Arts and Technology in Hamilton, Ontario, Canada as an Electronic Engineering Technologist. I started my consulting business after working 32 years at Bell Northern Research/Nortel. Throughout my career, I have held a variety of hardware design engineering positions and pioneered several advanced technologies into products. Currently I offer innovative signal integrity and backplane solutions as a consultant.
From as far back as I can remember, I was always interested in how things worked. I would often take things apart just to see what was inside; not always successful in putting them back together again though ;o. I was always fascinated with electricity and electronics. When I was about 10 or 11, I was mystified with how telephones worked. After reading about Alexander Graham Bell in a booklet published by The Bell Telephone Company of Canada, I became inspired to buy a pair of old push to talk handsets from a local army surplus store. I experimented with them using a drycell battery and lamp cord wire. When I finally was able to get twoway communications, it seemed like magic. I knew right then what my career choice would be.
I have been fortunate throughout my career to have been a part of and contribute to some of the technology that enable the gadgets we enjoy today. I have met and worked with many smart and talented individuals who took the time to unselfishly share their knowledge and experience.
And now, after all this time, the passion I had as kid to learn and understand new things is still there. Except now, like cradling a fine glass of wine, I am able to slowly swirl it around, sip it and savor the taste. This blog is about sharing some of that passion. It will cover a range of topics from signal integrity, PCBs, backplane design, circuit modeling, simulation tools and other practical engineering solutions. I hope you find my posts interesting and get inspired to explore them further on your own.
Thanks for visiting. I invite you to constructively comment and share your own thoughts and experiences as well.