Bert Simonovich's Design Notes

Innovative Signal Integrity & Backplane Solutions

DesignCon: The Place to Go to Find Out What You Don’t Know You Don’t Know

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imageIn engineering, it’s what you don’t know you don’t know that can ruin your day and keep you awake at nights. Especially after you get your prototypes in the lab, or worse, field returns from the customer. This is one reason why I have been going to DesignCon for the last few years, and this year has been no exception.

One of the sessions I attended was the Power Integrity Boot Camp, hosted by Heidi Barnes, from Keysight Technologies, and Steve Sandler from Picotest. What I didn’t know I didn’t know from this boot camp was how important it was to match the voltage regulator module (VRM) output impedance to the power distribution network (PDN) input impedance. Steve and Heidi recently presented a webcast which was a condensed version of the DesignCon Bootcamp session. If you are involved in PDN design, this webcast will provide you with an introduction to power integrity and give some insight into the latest tips and techniques to achieve flat impedance designs.

Of course, I always try and attend some of Eric Bogatin’s presentations because I always come away with something I didn’t know I didn’t know. Eric is an Adjunct Professor at the University of Colorado and the Dean of Teledyne LeCroy’s SI Academy. He was honored at this year’s DesignCon with a well-deserved Engineer of the Year Award.

The speed training event, he hosted along with Larry Smith from Qualcomm, was on the top of my list to attend. During the session, Eric described the most critical feature of PDN design was controlling the “Bandini Mountain”.

The Bandini Mountain expression has often been used to describe a tall pile of manure. Originally it referred to a 100 foot tall mound of fertilizer built by the Bandini Fertilizer Company in California prior to the 1984 Los Angeles summer Olympics for advertisement purposes. When the company went bankrupt, this large mound of smelly fertilizer was left behind and everyone wished it would go away.

Because of this little bit of trivia, it was the term coined by the late Steve Weir to describe the large resonant frequency peak formed by the parallel combination of the on die capacitance and the package lead inductance, as seen from the die looking into the PDN. This peak is inherent in all PDN networks, and almost impossible to get rid of. And like the Bandini Mountain, it was something PDN designers wish could go away.

Steve used to be a regular Icon at past DesignCons until his sudden passing in August 2015. Steve was one of the smartest guys I knew, and I always looked forward to catching up with him when I visited DesignCon. If you knew Steve, like many of us did, you know that he often had very humorous analogies to describe empirical or simulated results. This example is no exception. He will be sorely missed for his contribution the engineering community.

What I learned I didn’t know I didn’t know from Eric’s and Larry’s presentation was that every PDN design will have a “Bandini Mountain”, and unless you know what frequency it is at, and take steps to try and mitigate its peak, it could ruin your day! Even though the system seems to “work” in the lab, it doesn’t mean it’s robust enough and won’t fail under certain operating conditions in the field that affect the transient currents.

Eric has made available the speed training slides and the associated video off his SI Academy web site. If you look under Video Recordings, Presentations and Webinars (VRPW) and scroll down to the bottom you will find the slides titled, “VRPW-60-35 DesignCon 2016 PDN speed training”. If you watch the whole presentation you will learn all about the “PDN Bandini Mountain” and techniques to mitigate its effects. And while you are there, have a look at the many other videos and presentations available for free and by paid subscription.

Eric and Larry have also co-authored a new book, scheduled for release in June 2016 titled, “Principles of Power Integrity for PDN Design”. I can’t wait to buy this book to add to my library so that I can find out more of what I don’t know I don’t know about PDN design. If it’s anything like Eric’s other books, I won’t be disappointed.

Written by Bert Simonovich

March 14, 2016 at 2:11 pm

Posted in Uncategorized

Practical Conductor Roughness Modeling with Cannonballs

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image

In the GB/s regime, accurate modeling of conductor losses is a precursor to successful high-speed serial link designs. Failure to model roughness effects can ruin you day. For example, Figure 1 shows the simulated total loss of a 40 inch printed circuit board (PCB) trace without roughness compared to measured data. Total loss is the sum of dielectric and conductor losses. With  just -3dB delta in insertion loss between simulated and measured data at 12.5 GHz, there is half the eye height opening with rough copper at 25GB/s.

So what do cannon balls have to do with modeling copper roughness anyway? Well, other than sharing the principle of close packing of equal spheres, and having a cool name, not very much.

According to Wikipedia, close-packing of equal spheres is defined as “a dense arrangement of congruent spheres in an infinite, regular arrangement (or lattice)[8].  The cubic close-packed and hexagonal close-packed are examples of two regular lattices.  The cannonball stack is an example of a cubic close-packing of equal spheres, and is the basis of modeling the surface roughness of a conductor in this design note.

image

Figure 1 Comparisons of measured insertion loss of a 40 inch trace vs simulation. Eye diagrams show that with -3dB delta in insertion loss at 12.5GHz there is half the eye opening at 25GB/s. Modeled and simulated with Keysight EEsof EDA ADS software [14].

Background

In printed circuit (PCB) construction there is no such thing as a perfectly smooth conductor surface. There is always some degree of roughness that promotes adhesion to the dielectric material. Unfortunately this roughness also contributes to additional conductor loss.

Electro-deposited (ED) copper is widely used in the PCB industry. A finished sheet of ED copper foil has a matte side and drum side. The drum side is always smoother than the matte side.

The matte side is usually attached to the core laminate. For high frequency boards, sometimes the drum side of the foil is laminated to the core. In this case it is referred to as reversed treated (RT) foil.

Various foil manufacturers offer ED copper foils with varying degrees of roughness. Each supplier tends to market their product with their own brand name. Presently, there seems to be three distinct classes of copper foil roughness:

·         Standard

·         Very-low profile (VLP)

·         Ultra-low profile (ULP) or profile free (PF)

Some other common names referring to ULP class are HVLP or eVLP.

Profilometers are often used to quantify the roughness tooth profile of electro-deposited copper. Tooth profiles are typically reported in terms of 10-point mean roughness (Rz ) for both sides, but sometimes the drum side reports average roughness (Ra ) in manufacturers’ data sheets. Some manufacturers also report RMS roughness (Rq ).

Modeling Roughness

Several modeling methods were developed over the years to determine a roughness correction factor (KSR ). When multiplicatively applied to the smooth conductor attenuation (αsmooth ), the attenuation due to roughness (αrough ) can be determined by:

Equation 1

image

The most popular method, for years, has been the Hammerstad and Jensen (H&J) model, based on work done in 1949 by S. P. Morgan. The H&J roughness correction factor (KHJ ), at a particular frequency, is solely based on a mathematical fit to S. P. Morgan’s power loss data and is determined by [2]:

Equation 2

image

Where:

KHJ = H&J roughness correction factor;

= RMS tooth height in meters;

δ = skin depth in meters.

Alternating current (AC) causes conductor loss to increase in proportion to the square root of frequency. This is due to the redistribution of current towards the outer edges caused by skin-effect. The resulting skin-depth (δ ) is the effective thickness where the current flows around the perimeter and is a function of frequency.

Skin-depth at a particular frequency is determined by:

Equation 3

image

Where:

δ = skin-depth in meters;

f = sine-wave frequency in Hz;

μ0= permeability of free space =1.256E-6 Wb/A-m;

σ = conductivity in S/m. For annealed copper σ = 5.80E7 S/m.

The model has correlated well for microstrip geometries up to about 15 GHz, for surface roughness of less than 2  RMS. However, it proved less accurate for frequencies above about 5GHz for very rough copper [3] .

In recent years, the Huray model [4] has gained popularity due to the continually increasing data rate’s need for better modeling accuracy. It takes a real world physics approach to explain losses due to surface roughness. The model is based on a non-uniform distribution of spherical shapes resembling “snowballs” and stacked together forming a pyramidal geometry, as shown by the scanning electron microscope (SEM) photo in Figure 2.

image

Figure 2 SEM photograph of electrodeposited copper nodules on a matte surface resembling “snowballs” on top of heat treated base foil. Photo credit Oak-Mitsui.

By applying electromagnetic wave analysis, the superposition of the sphere losses can be used to calculate the total loss of the structure. Since the losses are proportional to the surface area of the roughness profile, an accurate estimation of a roughness correction factor (KSRH) can be analytically solved by [1]:

                                                                                                                                                                                                                                                                                                    

Equation 4

image

Where:

KSRH (f ) = roughness correction factor, as a function of frequency, due to surface roughness based on the Huray model;

Aflat= relative area of the matte base compared to a flat surface;

 ai = radius of the copper sphere (snowball) of the ith size, in meters;

 Ni = number of copper spheres of the ith size per unit flat area in sq. meters;

 δ (f ) = skin-depth, as a function of frequency, in meters.

Cannonball Model

Using the concept of cubic close-packing of equal spheres, the radius of the spheres (ai ) and tile area (Aflat ) parameters for the Huray model can now be determined solely by the roughness parameters published in manufacturers’ data sheets.  

Why is this important? Well, as my friend Eric Bogatin often says, “Sometimes an OK answer NOW! is more important than a good answer late”. For example, often during the architectural phase of a backplane design, you are going through some what-if scenarios to decide on a final physical configuration. Having a method to accurately predict loss from data sheets alone rather than go through a design feedback method, described in [7] can save an enormous amount of time and money.

Another reason is that it gives you a sense of intuition on what to expect with measurements to help determine root cause of differences; or sanitize simulation results from commercial modeling tools. If you are like me, I always like to have alternate ways to verify that I have used the tool properly.

Recalling that losses are proportional to the surface area of the roughness profile, the Cannonball model can be used to optimally represent the surface roughness. As illustrated in Figure 3, there are three rows of spheres stacked on a square tile base. Nine spheres are on the first row, four spheres in the middle row, and one sphere on top.

image

Figure 3 Cannonball model showing a stack of 14 uniform size spheres (left). Top and front views (right) shows the area (Aflat) of base, height (HRMS) and radius of sphere (r).

Because the Cannonball model assumes the ratio of Amatte/Aflat = 1, and there are 14 spheres, Equation 4 can be simplified to:

Equation 5

image

Where:

KSR (f ) = roughness correction factor, as a function of frequency, due to surface roughness based on the Cannonball model;

r = sphere radius in meters; δ (f ) = skin-depth, as a function of frequency in meters;

Aflat = area of square tile base surrounding the 9 base spheres in sq. meters.

In my white paper [16] the radius of a single sphere is:

image

And the area of the square flat base is:

image

You can approximate the RMS heights of the drum and matte sides by Equation 6 and Equation 7 below:

Equation 6

image

Where: Rz_drum is the 10-point mean roughness in meters. If the data sheet reports average roughness, then Ra_drum is used instead.

Equation 7

image

Where: Rz_matte is the 10-point mean roughness in meters.

Practical Example

To test the accuracy of the model, board parameters from a PCBDesign007 February 2014 article, by Yuriy Shlepnev [5] was used. Measured data was obtained from Simbeor software design examples courtesy of Simberian Inc. [9]. The extracted de-embedded generalized modal S-parameter (GMS) data was computed from 2 inch and 8 inch single-ended stripline traces. They were originally measured from the CMP-28 40 GHz High-Speed Channel Modeling Platform from Wild River Technology [14].

imageThe CMP-28 Channel Modeling Platform, (Figure 4 left -credit Wild River Technology) is a powerful tool for development of high-speed systems up to 40 GHz, and is an excellent platform for model development and analysis. It contains a total of 27 microstrip and stripline interconnect structures. All are equipped with 2.92mm connectors to facilitate accurate measurements with a vector network analyzer (VNA).

The PCB was fabricated with Isola FR408HR material and reverse treated (RT) 1oz. foil. The dielectric constant (Dk) and dissipation factor (Df), at 10GHz for FR408HR 3313 material, was obtained from Isola’s isoStack® web-based online design tool [10]. This tool is a free, but you need to register to use it. An example is shown in Figure 5.

Typical traces usually have a trapezoidal cross-section after etching due to etch factor. Since the tool does not handle trapezoidal cross-sections in the impedance calculation, an equivalent rectangular trace width was determined based on a 2:1 etch-factor (60 deg taper).  The as designed nominal trace width of 11 mils, and a 1oz trace thickness of 1.25 mils per isoStack® was used in the analysis.

image

Figure 5 Example of Isola’s isoStack® online software used to determine dielectric thicknesses, Dk, Df and characteristic impedance for the CMP-28 board.

The default foil used on FR408HR core laminates is MLS, Grade 3, controlled elongation RT foil. The roughness parameters were easily obtained from Oak-mitsui [11]. Reviewing the data sheet, 1 oz. copper roughness parameters Rz for drum and matte sides are 120μin (3.175 μm) and 225μin (5.715μm) respectively. Because this is RT foil, the drum side is the treated side and bonded to the core laminate.

An oxide or micro-etch treatment is usually applied to the copper surfaces prior to final lamination. This provides enhanced adhesion to the prepreg material. CO-BRA BOND® [12] or MultiBond MP [13] are two examples of oxide alternative micro-etch treatments commonly used in the industry. Typically 50 μin (1.27μm) of copper is removed when the treatment is completed. But depending on the board shop’s process control, this can be 70-100 μin (1.78-2.54μm) or higher.

The etch treatment creates a surface full of micro-voids which follows the underlying rough profile and allows the resin to squish in and fill the voids providing a good anchor. Because some of the copper is removed during the micro-etch treatment, we need to reduce the published roughness parameter of the matte side by nominal 50 μin (1.27 μm) for a new thickness of 175μin (4.443μm).

Figure 6 shows SEM photos of typical surfaces for MLS RT foil courtesy of Oak-mitsui. The left and center photos are the treated drum side and untreated matte side respectively. The right photo is a 5000x SEM photo of the matte side showing micro-voids after etch treatment.

image

Figure 6 Example SEM photos of MLS RT foil courtesy of Oak-mitsui. Left is the treated drum side and center is untreated matte side. SEM photo on the right is the matte side after etch treatment.

The data sheet and design parameters are summarized in Table 1. Respective Dk, Df, core, prepreg and trace thickness were obtained from the isoStack® software, shown in Figure 5. Roughness parameters were obtained from Oak-mitsui data sheet. Rz of the matte side after micro-etch treatment (Rz = 4.443μm) was used to determine KSR_matte .

Table 1 CMP-28 test board parameters obtained from manufacturers’ data sheets and design objective.

Parameter

           FR408HR

Dk Core/Prepreg

3.65/3.59 @10GHz

Df Core/Prepreg

0.0094/0.0095 @ 10GHz

Rz Drum side

3.175 μm

Rz Matte side before Micro-etch

5.715 μm

Rz Matte side  after Micro-etch

4.443 μm

Trace Thickness, t

31.730 μm

Trace Etch Factor

2:1 (60 deg taper)

Trace Width, w

11 mils (279.20 μm)

Core thickness, H1

12 mils (304.60 μm)

Prepreg thickness, H2

10.6 mils (269.00 μm)

GMS trace length

6 in (15.23 cm)

 

Keysight EEsof EDA ADS software [14] was used for modeling and simulation analysis. A new controlled impedance line (CIL) designer enhancement, in version 2015.01, makes modeling the transmission line substrate easy. Unlike earlier substrate models, the CIL model allows you to model trapezoidal traces.

Figure 7 is the general schematic used for analysis. There are three transmission line substrates; one for dielectric loss; one for conductor loss and the other for total loss without roughness.

image

Figure 7 Keysight EEsof EDA ADS generic schematic of controlled impedance line designer used in the modeling and simulation analysis.

Dielectric loss was modeled using the Svensson/Djordjevic wideband Debye model to ensure causality. By setting the conductivity parameter to a value much-much greater than the normal conductivity of copper ensures the conductor is lossless for the simulation. Similarly the conductor loss model sets the Df to zero to ensure lossless dielectric.

Total insertion loss (IL) of the PCB trace, as a function of frequency, is the sum of dielectric and rough conductor insertion losses.

Equation 8

image

To accurately model the effect of roughness, the respective roughness correction factor (KSR ) must be multiplicatively applied to the AC resistance of the drum and matte sides of the traces separately. Unfortunately ADS, and many other commercial simulators, do not allow access to these surfaces to apply the correction properly. The best you can do is to apply the average of (KSR_drum ) and (KSR_matte ) side to the smooth conductor loss (ILsmooth ), as described above.

The following are the steps to determine KSR_avg (f ) and total IL with roughness:

1. Determine HRMS_drum and HRMS_matte from Equation 6 and Equation 7. 

  image

2. Determine the radius of spheres for drum and matte sides:
image

3. Determine the area of the square flat base for drum and matte sides:
image

4. Determine KSR_drum (f ) and KSR_matte (f ) :
image

5. Determine the average KSR_drum (f ) and KSR_matte (f ):
image

6. Apply Equation 8 to determine total insertion loss of the PCB trace.

image

Summary and Results

The results are plotted in Figure 8. The left plot compares the simulated vs measured insertion loss for data sheet values and design parameters.  Also plotted is the total smooth insertion loss (crosses) which is the sum of conductor loss (circles) and dielectric loss (squares). Remarkably there is excellent agreement up to about 30GHz by just using algebraic equations and published data sheet values for Dk, Df and roughness.

The plot shown on the right is the simulated (blue) vs measured (red) effective dielectric constant (Dkeff ), and is determined by the equations shown. As can be seen, the measured curve has a slightly higher Dkeff (3.76 vs 3.63 @ 10GHz) than published. According to [6], the small increase in the Dk is due to the anisotropy of the material.

When the measured Dkeff (3.76) was used in the model, for core and prepreg, the IL results shown in Figure 9 (left) are even more remarkable up to 50 GHz!

image

Figure 8 IL (left) for a 6 inch trace in FR408HR RTF using supplier data sheet values for Dk, Df and Rz. Effective Dk is shown right.

image

Figure 9 IL (left) for a 6 inch trace in FR408HR RTF and effective Dk (right).

Figure 10 compares the Cannonball model against the H&J model. The results show that the H&J is only accurate up to approximately 15 GHz compared to the Cannonball model’s accuracy to 50GHz.

image

Figure 10 Cannonball Model (left) vs Hammerstad-Jensen model (right).

Conclusions

Using the concept of cubic close-packing of equal spheres to model copper roughness, a practical method to accurately calculate sphere size and tile area was devised for use in the Huray model. By using published roughness parameters and dielectric properties from manufacturers’ data sheets,  it has been demonstrated that the need for further SEM analysis or experimental curve fitting, may no longer be required for preliminary design and analysis.

When measurements from CMP-28 modeling platform, fabricated with FR408HR and RT foil, was compared to this method, there was excellent correlation up to 50GHz compared to the H&J model accuracy to 15GHz.

The Cannonball model looks promising for a practical alternative to building a test board and extracting fitting parameters from measured results to predict insertion loss due to surface roughness.

For More Information

If you liked this design note and want to learn more, or get more details on this innovative roughness modeling methodology, you can visit my web site, LAMSIM Enterprises.com , and download a copy of the white paper [16], or my award winning DesignCon 2015 paper, [1]. And while you are there, feel free to investigate my other white papers and publications.

If you would like more information on our signal integrity and backplane services, or how we can help you achieve your next high-speed design challenge, email us at: info@lamsimenterprises.com

References

[1]   Simonovich, Bert, “Practical Method for Modeling Conductor Surface Roughness Using Close Packing of Equal Spheres”, DesignCon 2015 Proceedings, Santa Clara, CA, 2015, URL: http://lamsimenterprises.com/Copyright2.html

[2]   Hammerstad, E.; Jensen, O., “Accurate Models for Microstrip Computer-Aided Design,” Microwave symposium Digest, 1980 IEEE MTT-S International , vol., no., pp.407,409, 28-30 May 1980 doi: 10.1109/MWSYM.1980.1124303 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1124303&isnumber=24840

[3]   S. Hall, H. Heck, “Advanced Signal Integrity for High-Speed Digital Design”, John Wiley & Sons, Inc., Hoboken, NJ, USA., 2009

[4]   Huray, P. G. (2009) “The Foundations of Signal Integrity”, John Wiley & Sons, Inc., Hoboken, NJ, USA., 2009

[5]   Y. Shlepnev, “PCB and package design up to 50 GHz: Identifying dielectric and conductor roughness models”, The PCB Design Magazine, February 2014, p. 12-28. URL: http://iconnect007.uberflip.com/i/258943-pcbd-feb2014/12

[6]   Y. Shlepnev, “Sink or swim at 28 Gbps”, The PCB Design Magazine, October 2014, p. 12-23. URL: http://www.magazines007.com/pdf/PCBD-Oct2014.pdf

[7]    E. Bogatin, D. DeGroot , P. G. Huray, Y. Shlepnev , “Which one is better? Comparing Options to Describe Frequency Dependent Losses”, DesignCon2013 Proceedings, Santa Clara, CA, 2013.

[8]   Wikipedia, “Close-packing of equal spheres”. URL: http://en.wikipedia.org/wiki/Close-packing_of_equal_spheres

[9]   Simberian Inc., 3030 S Torrey Pines Dr. Las Vegas, NV 89146, USA. URL: http://www.simberian.com/

[10]    Isola Group S.a.r.l., 3100 West Ray Road, Suite 301, Chandler, AZ 85226. URL: http://www.isola-group.com/

[11]    Oak-mitsui 80 First St, Hoosick Falls, NY, 12090. URL: http://www.oakmitsui.com/pages/company/company.asp

[12]    Electrochemicals Inc. CO-BRA BOND®. URL: http://www.electrochemicals.com/ecframe.html

[13]    Macdermid Inc., Multibond. URL: http://electronics.macdermid.com/cms/products-services/printed-circuit-board/surface-treatments/innerlayer-bonding/index.shtml

[14]    Keysight Technologies, EEsof EDA, Advanced Design System, 2015.01 software. URL: http://www.keysight.com/en/pc-1297113/advanced-design-system-ads?cc=US&lc=eng

[15]    Wild River Technology LLC 8311 SW Charlotte Drive Beaverton, OR 97007. URL: http://wildrivertech.com/home/

[16]    Simonovich, Bert, “Practical Method for Modeling Conductor Surface Roughness Using The Cannonball Stack Principle”, White Paper, Issue 1.0, April 8, 2015,
URL:
http://lamsimenterprises.com/Copyright.html

Dr. Eric Bogatin Launches New Signal Integrity Academy

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imageLast year, Signal Integrity Evangelist, Dr. Eric Bogatin announced the end of his famous signal integrity classes. At the time I remember thinking to myself, “What’s next for Eric”? If you know Eric, like I do, you realize that the end of one phase of his career usually means the start of the next one. And now we know what that is. You see, Eric has been busy the last six months (January-June-2014) preparing to launch his new Teledyne Lecroy Signal Integrity Academy web portal.

Eric is currently a Signal Integrity Evangelist with Teledyne LeCroy, and on the faculty at the University of Colorado at Boulder, where he recently moved to from Kansas. He has a BS degree in physics from MIT, and MS and PhD degrees in physics from the University of Arizona in Tucson. He has held senior engineering and management positions at Bell Labs, Raychem, Sun Microsystems, Ansoft, and Interconnect Devices. Prior to being acquired by Teledyne Lecroy, he ran his successful company, Bogatin Enterprises, along with his wife Susan, where they provided signal integrity training.

I met and got to know Eric back in 2008, when we collaborated on our first DesignCon paper for 2009 titled, “Practical Analysis of Backplane Vias”. We were privileged to win a best paper award that year. Since that time we have worked on several projects together, and have become good friends. The last project we worked on was for a DesignCon2013 paper titled, “Dramatic Noise Reduction using Guard Traces with Optimized Shorting Vias”, which also won a best paper award.

Over the years, I have studied much of Eric’s work through his many papers, articles, webinars, blogs and content from his previous web site. I always made it a point to attend all of his presentations at any conferences I attended. I have his first edition “Signal Integrity Simplified” book as well. It has been one of my go-to books when starting any of my research projects or concepts I am trying to grasp. Like my other go-to signal integrity books in my library, it is well marked and used; although this one seems more so than others. Having the privilege of working with Eric has also enriched my learning experience.

Over the years, I always wished I could have attended some of his classes; but due to travel cost and time away from the office, it could never be justified. Now, with the beauty of the internet, the classes can come to me. I can choose to watch what I want; when I want; as many times as I want; on whatever device I want. My iPad is a perfect choice! For a yearly subscription fee for individuals or corporations, you have the opportunity of watching any class or lesson anytime.

All the content is in the form of short, concise video lessons lasting 5 to 15 minutes. Slides are available for download and I suggest downloading the respective slides prior to watching the presentation so you can make notes as you go along. The initial three courses: Essential Principles of SI; Advanced Gigabit Channel Design; S-Parameters for SI; are based on his most popular public classes. Once subscribed, you are offered an “all you can eat buffet” of all the lessons. There are more courses and lessons planned in the future.

If you have always wanted to accelerate your signal integrity learning curve, then the Teledyne Lecroy Signal Integrity Academy may be the right place for you to start. You can learn more by visiting Eric’s web site at: Bethesignal.com

Written by Bert Simonovich

June 28, 2014 at 1:11 pm

Posted in Signal Integrity

Dr. Howard Johnson; a great teacher, mentor and friend.

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clip_image001The other day, in my inbox, I received the link to the June 2013 electronic edition of EDN magazine, and promptly clicked to Howard Johnson’s signal integrity column. I have looked forward to reading them for many years now, and when I used to receive the magazine, in print, I faithfully cut out the respective month’s articles, and filed them away for future reference. This month I was saddened to read it was to be his last article for EDN. After a long and distinguished career, he decided to retire from his consulting and seminar business. I knew it was going to happen soon, but when I actually read it in print, I started to think about my career, and how influential he has been teaching me about signal integrity. Ironically, the title of the article, “Seek inspiration”, touched on the importance of mentorship and has inspired me to write this post.

Dictionary.com defines a mentor as “a wise and trusted counsellor or teacher”. Over the years H.J. became mentor to thousands of engineers and students all over the world, including myself, through his teachings, publications and films. The main thing I learned from him was to think about problems differently and try to apply other disciplines to understand what’s going on.

H.J. always had a way of presenting complex signal integrity topics simply by relating the subject to other things in life we are most familiar with. I remember one article he wrote, years ago, about wave propagation along a transmission line, and how it was analogous to slowly filling an ice-cube tray by tilting it at one end, and letting the water slowly fill each compartment at a time before overflowing and filling the next, and the next, and the next, until all were full. Now, I cannot fill an ice-cube tray without thinking about transmission lines, or my friend.

I was first introduced to his teachings by reading, “High-speed Digital Design, a handbook of black magic”. Back in 1999 it was my first book on signal integrity, and ultimately was the lure that got me hooked. I remember going through each section, taking notes, highlighting some text, and book marking certain sections throughout with little cut-up strips of post-it notes. The F_knee = 0.5/tr equation is still etched in my non-volatile memory. Not everything made sense to me the first time, but over the years I found myself going back to those sections and re-reading them, depending on the problem of the day I was trying to solve.

Over the years, I would occasionally email him with questions and ask for clarification of parts of his books. Each time he was more than willing to respond back with a more detailed explanation. When email didn’t work, he took time from his busy schedule to arrange a phone meeting where we could discuss the subject in more detail.

When I look back now, I realized just how much I have grown and learned, thanks to Howard Johnson sharing his knowledge and experience. But then again, it is only natural for a true mentor to do. How has Howard Johnson mentored and inspired your career?

Written by Bert Simonovich

June 27, 2013 at 9:07 am

Posted in Signal Integrity

Are Guard Traces Worth It?

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Originally  published in, The PCB Design Magazine, April 2013 issue.

clip_image002By definition, a guard trace is a trace routed coplanar between an aggressor line and a victim line. There has always been an argument on whether to use guard traces in high-speed digital and mixed signal applications to reduce the noise coupled from an aggressor transmission line to a victim transmission line.

On one side of the debate, the argument is that the guard trace should be shorted to ground at regular intervals along its length using stitching vias spaced at 1/10th of a wavelength of the highest frequency component of the aggressor’s signal. By doing so, it is believed the guard trace will act as a shield between the aggressor and victim traces.

On the other side, merely separating the victim trace to at least three times the line width from the aggressor is good enough. The reasoning here is that crosstalk falls off rapidly with increased spacing anyways, and by adding a guard trace, you will already have at least three times the trace separation to fit it in.

In our DesignCon2013 paper titled, “Dramatic Noise Reduction using Guard Traces with Optimized Shorting Vias”, I coauthored along with Eric Bogatin, we showed that sometimes guard traces were effective, and sometime they were not; depending on how the guard trace was terminated. By correct management of the ends of the guard trace, we demonstrated it can reduce coupled noise on a victim line by an order of magnitude over not having the guard trace present. But if the guard trace was not optimized, the noise on the victim line can also be larger with the guard trace, than without.

Analysis Using Circuit Models

We started out the investigation by building circuit models for the topologies studied. Agilent’s EEsof EDS ADS software was used exclusively to model and simulate both stripline and microstrip configurations. The generic circuit model, with a guard trace, is shown in the top half of Figure 1. The circuit model, without a guard trace, is shown in the bottom half.

For the analysis, we used lossless transmission line models. The guard trace length was exactly matched to the coupled length. The ground stitching and the end-termination resistors, on the guard trace, could be deactivated, and/or shorted, as required. The line-width space geometry was set at 5-5-5 mils, and the spacing for the non-guarded topologies was set to three times the line width.

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Figure 1 ADS schematic for generic topologies with a guard trace (top) and without (bottom). The transmission line were segmented and parameterized to easily change the lengths as required. The ground stitching and the end-termination resistors, shown in top schematic, can be deactivated and/or shorted as required.

Figure 2 is a summary of results when a guard trace was terminated in the characteristic impedance, left open, or shorted to ground at each end. The red waveforms are the results for topologies without a guard trace, and the blue waveforms are with a guard trace.

Depending on the nature of the termination, the reinfected noise on the guard trace can add or subtract to the directly coupled noise on the victim line. This often makes the net noise on the victim line worse than without a guard trace.

Unlike a simple two-line coupled model, where the near end crosstalk (NEXT) and far end crosstalk (FEXT) can be easily predicted from the RLGC matrix elements, trying to predict the same for a three-line coupled model is more difficult. Manually keeping track of all the noise induced on the guard trace, and its reinfection onto the victim line, is extremely tedious. First you must identify the directly coupled reinfected backward and forward noise on the victim line from the voltage on the guard trace. Then the problem is keeping track of the multiple reflections of the noise on the guard trace. Because of this, the only real way to analyse the effect is through circuit modeling and simulation.

In microstrip topologies, as you can see, there is little to no benefit to adding a guard trace; regardless of how the ends are terminated. This is because microstrip topologies are inherently prone to far end crosstalk. Therefore any far end noise, coupled onto the guard trace, will subsequently reinfect the victim with additional far end noise; as seen by the additional ringing superimposed on the blue waveform.

In stripline topologies, without a guard trace, there is no far-end cross talk generated. But when a guard trace is added, and depending on how the ends are terminated, any near end coupled noise on the guard trace can reinfect the victim. It is only when the ends are shorted to ground we see such a dramatic reduction of both near and far end noise.

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Figure 2 Summary of simulation results when the ends of the guard trace was terminated, left open or shorted to ground for microstrip and stripline geometries.

Distributed Shorting Vias

When practically implementing a guard trace, to act as a shield, a rough rule of thumb suggests the spacing of shorting vias should be at least 1/10 the wavelength of the highest frequency content of the signal. For a risetime of 100 psec, the stitching via spacing, to meet l/10, is 0.18 inches; or 9 stitching vias over 1.5 inches.

Figure 3 summarizes the results when a guard trace was stitched to ground at multiple wavelengths; compared to the case of no guard. As you can see, in the case of microstrip, when the guard trace is shorted with fewer than 9 vias, there is still considerable ringing noise on the guard trace which can reinfect the victim line. But in the case of stripline, having two shorting vias at each end, or any number up to 9 shorting vias has the same result. This suggests there is no need for multiple shorting vias, other than at the end of the guard trace; as long as the guard trace is the same length as the coupled length. This dramatically simplifies the use of guard traces in stripline.

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Figure 3 Summary of simulation results with guard trace stitched for microstrip and stripline geometries.

Practical Design Considerations

Up until now we have modeled and simulated ideal cases of shorting the guard traces to ground. But in reality, there are additional practical design considerations to consider. First is via size, and the impact it has on the line to line spacing. Next is the finite via inductance; since its impedance will prevent complete suppression of the noise on the guard trace. And finally, the extension of the guard trace compared to the coupled length.

Because through hole manufacturing design rules limit the smallest via and capture pads, the smallest mechanical drill size most PCB vendors will spec is 8 mils. By the time you factor in the minimum pad diameter and pad to copper spacing, the minimum space between the aggressor and victim lines would have to be at least 28 mils, as shown in Figure 4; just to fit a guard trace with grounding vias down its length.

At this point, you have to ask yourself if it is even worth it; especially for microstrip topologies. If the two signal lines were to be increased to 28 mils, the reduction in cross talk from just the added separation would likely be more significant than adding the shorted guard trace.

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Figure 4 Minimum track to track spacing to fit an 8 mil drilled via and pad in through-hole technology.

Fortunately, the circuit analysis has shown there is little benefit to adding a guard trace to microstrip topologies, even if it was ground stitched appropriately. But to gain a dramatic reduction in cross talk in stripline all that is required is to short the guard trace at each end, and ensure the guard trace is exactly the same length as the coupled length. This means the minimum space to fit a via and guard trace can remain at three times the line width; as long as the guard trace is extended slightly, as shown in Figure 5(a). Alternatively, the guard trace can be made equal to the coupled length, as illustrated in Figure 5(b).

Agilent’s ADS Momentum planar 3D field solver was used to explore and quantify the implications vias and guard trace lengths have on noise reinfection. Figure 5 details a portion of the 3D model on the left end of the respective topologies. The right hand sides are identical. The reference planes are not shown for clarity.

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Figure 5 Two examples of adding a grounded guard trace with minimum spacing of 3 x line width. Figure (a): guard trace is extended past the coupled length (A) by dimension B on both sides in order to satisfy minimum 5 mil pad-track spacing requirements. Figure (b): guard trace is equal to coupled length by separating the traces at each ends. Modeled in Agilent Momentum 3D field solver. Reference planes are not shown for clarity.

After simulation, the S-parameter data was saved in Touchstone format and brought into ADS for transient simulation analysis and comparison. Figure 6 shows the results. The plot on the left used 100 psec risetime for the step edge, while the plot on the right used 50 psec. Both plots are consistent with the dramatic noise reduction observed in Figure 2, except here we see some added noise ripple after about 0.8 nsec.

At 100 psec risetime, there is effectively no difference in near end noise signature for either (a) or (b) topology. But when the risetime was reduced to 50 psec, the noise ripple is more pronounced. The blue waveform shows that even when dimension B is 0 mils, there is still a small amount of noise due to the inductive length of the vias to the reference plane. The red waveform shows that adding just 12 mils to the guard trace length, at each end, the ripple magnitude is almost doubled.

It is a well-known fact that technology advancements over time results in faster and faster rise times. If you have engineered your design on the technology of the day, any future substitution of parts, with faster rise time, may cause your product to fail, or worse be intermittent.

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Figure 6 Momentum transient simulation results comparing near end crosstalk at Port 1 when aggressor voltage was applied to Port 3. The red and blue waveforms are with a guard trace. The green waveform is with no guard and 15 mils separation. Aggressor voltage = 1V, 100 psec risetime (left) and 50 psec risetime(right)..

To explore this phenomenon, the guard trace was varied by 50 and 100 mils at each end, as illustrated in Figure 7. Here we can see that as the guard trace gets longer at each end, the noise ripple grows in magnitude quite rapidly. It is remarkable to note that when the guard trace is just 100 mils longer, at each end, the peak-peak amplitude of the noise just about equals the peak magnitude of the no guard case.

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Figure 7 Momentum transient simulation results with guard trace extended. B = 12 mils (red), B = 50 mils (blue) and B = 100 mils (magenta) compared to no guard (green). Aggressor voltage = 1V, 100 psec risetime. Dimensions in mils.

When the guard trace was removed, and the space was increased to five times the line width, the near end crosstalk was reduced in magnitude and was approximately equal to the guard trace scenario, as seen in Figure 8. Furthermore, because there is no guard trace, there is no additional noise ripple.

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Figure 8 Momentum transient simulation results comparing near end crosstalk at Port 1 when aggressor voltage was applied to Port 3. Aggressor voltage = 1V, 100 psec risetime.

So getting back to the original question, “Are guard traces worth it?” You be the judge. Using a guard trace, shorted at each end, can be effective, if you need the isolation. But it does have caveats. If you decide to go down this path, it is imperative for you to model and simulate your topology, preferably with a 3D field solver, before signing off on the design.

Reference

  1. Eric Bogatin, Bert Simonovich,Dramatic Noise Reduction using Guard Traces with Optimized Shorting Vias, DesignCon2013, Santa Clara, CA, USA, Jan 28-31, 2013.

Written by Bert Simonovich

April 12, 2013 at 2:36 pm

Non-contact Interconnect: When Crosstalk Is Your Friend

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Originally  published in, The PCB Design Magazine, November 2012 issue.

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In normal PCB designs, crosstalk is usually an unwanted effect, due to electro-magnetic coupling, of two or more traces routed in close proximity to one another. We usually consider it to be our enemy, in any high-speed design, and go to great lengths to avoid it. So how, you may ask, can crosstalk ever be your friend?

To answer that question, I would like to start out by taking you back to the fall of 1994. This was the era of wide parallel busses running up to 33 MHz across backplanes. High-speed serial, point-point interfaces, and serdes technology, as we know and love today, was just a twinkle in some bright young engineer’s eye.

Nortel, a.k.a. Northern Telecom at the time, was looking to replace the computing module shelf of the DMS Supernode platform because it was projected to run out of steam a few years later. In order to address the issue, the system architects decided that a scalable, multi-processing, shared memory, computing architecture was needed to replace it.

My job was to develop a concept to package all these cards in a shelf, and then design a backplane to interconnect everything. It quickly became evident that a single shared bus could not support the bandwidth required for multi-processing. Nor could multiple parallel buses solve the problem, because of the lack of high-density backplane connector technology needed for all the I/O. Even if we had a suitable connector, and it could magically fit within the confines of the card slot, then the layer count of the backplane would have grown exponentially.

No, something else was needed. Fortunately, Bell Northern Research (BNR), the R&D lab of Nortel where I was working at the time, had an advanced technology group, that liked to play in the sand. I remember going to a meeting one day to see some presentations on some of the neat technology they were playing with.

One presentation they gave, was of a unique non-contact interconnect technology. I immediately saw the practical application that technology offered for our architecture, and it instantly became my friend. It allowed us to eventually invent a patented, proprietary point to multi-point interconnect solution, running at 1GB/s per pair [1].

The non-contact technology actually relied on controlled electro-magnetic coupling, or simply crosstalk. See Figure 1. In this simple high-level block diagram, each card on the shelf would transmit their data differentially across the backplane. As the differential pairs traversed through the connector fields of the card slots, the transmit signal was edge-coupled to an adjacent small trace, about three quarters of an inch long, connected to the respective receiver pin. After the last card slot, the transmit differential pairs switched layers where they returned back to the originating card and were terminated.

The beauty of this architecture was that each card only needed one set of transmitters to broadcast its data to all the other cards. Since each card had enough receivers to listen to the other cards, the point to multi-point interconnect achieved the equivalent of a multipoint to multipoint architecture; but without the overhead of additional pins and PCB layers. Furthermore, an effective line rate of 1GB/s was achieved using simple, inexpensive 2mm connectors; the same ones chosen for compact PCI standard.

imageFigure 2 is a photograph of an inner layer, double-sided core of the backplane, prior to lamination and drilling. It shows the couplers in more detail. The round pads are for the connector vias, and are used to attach the coupler traces to the connector pins. The rows of pads on the left are for one card slot, while the rows of pads on the right are for another card slot.

If we look at the two traces entering the picture from the bottom left side, we can see how they are routed through the connector field. These two traces are part of a differential pair where each are routed as single-ended traces, i.e. with no coupling to one another. As these traces approach the first row of pads, they jog down to minimum spacing to ensure close coupling to the coupler traces attached to the pads. The close spacing continues to ensure maximum coupling to the next set of pads, where the pattern stars all over again at the bottom right. This pattern repeats all the way up the photo for each differential pair.

You may be astute to notice that the bottom coupler trace connects to a pad at each end, while the mate coupler, above it does not. When two, coplanar parallel traces are in close proximity to one another, there are two types of crosstalk generated; backward or Near-End crosstalk (NEXT); and forward or Far-End crosstalk (FEXT).

As the transmit signal propagates, from left to right in the photo, the rising edge of the signal initiates NEXT at the beginning of the coupled length. The NEXT voltage saturates after a critical length equal to the risetime divided by twice the propagation delay; where the risetime is in seconds, and propagation delay is in seconds per unit length. It stays saturated for twice the time delay of the coupled length. Because of differential signalling, the NEXT voltages are of opposite phase on the respective couplers.

At the coupler pin, there is a reflection caused by the via. Since the couplers, at the far-end, are not terminated, in the characteristic impedance, and left open, any secondary reflections due to coupler via reflects back towards the receiver, again with opposite phase. When both reflections arrive back at the receiver, they will add together and add additional noise to the eye, causing inter-symbol interference, as shown by the shoulder in Figure 3(A). By leaving one end open, and shorting the other one to ground, means that any secondary noise will have the same phase, and when they arrive at the receiver, they will cancel, thereby eliminating the inter-symbol interference and increasing the eye amplitude as shown in Figure 3(B).

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You will notice that the eye waveforms do not resemble the traditional eye diagram we are used to seeing. Instead we observe a typical NEXT eye, when the coupled length is short, compared to the bit time. There is also a line right in the middle.

imageFigure 4 can help to explain the reason. The blue waveform is the NEXT voltage, seen at the near-end of the coupler, in response to the red transmitted waveform. Notice that there are only pulses at an edge transition of the transmitted waveform. A rising edge creates a positive pulse, and a falling edge generates a negative pulse. The duration of each pulse is twice the time delay of the coupler length.

The receiver uses simple peak-detectors and latch to regenerate the signal back to the original waveform. A positive going pulse is detected by the positive peak-detector. When it crosses the positive voltage threshold (+Vth), it sets the latch output to logic high. The output remains high until a negative pulse crosses the negative threshold (-Vth), of the negative peak-detector, and resets the latch to logic low.

And that is how crosstalk can be your friend! Of course the small coupled crosstalk signal means we have to guard against CROSSTALK from other digital signals on board. But that’s nothing that mixed signal layout design rules can’t solve. ……Wait a minute! ……We both share the same enemy? …….. Who would have thought an old Proverb, “The enemy of my enemy is my friend” [sic], would apply here too?

Reference:

[1] L. Simonovich et al, U.S. Patent 6,091,739, “HIGH SPEED DATA BUS UTILIZING POINT TO MULTI-POINT INTERCONNECT NON-CONTACT COUPLER TECHNOLOGY ACHIEVING A MULTI-POINT TO MULTI-POINT INTERCONNECT.”

[2] J. Williamson et al, U.S. Patent 6,016,086, “NOISE CANCELLATION MODIFICATION TO NON-CONTACT BUS.”

[3] Alexandre Guterman, Robert J.Zani, “Point-to-Multipoint Gigabit Backplane Design”, IEEE International Symposium on EMC, May 11-16, 2003.

Written by Bert Simonovich

November 21, 2012 at 7:15 pm

To Know The Bit Error Rate Is To Know The Bit Error Ratio

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Recently I came across a blog post titled, “Can Oscilloscopes Really Calculate BERs?”, written by Ransom Stephens.

I liked this article. I liked it because, as usual, Ransom likes to challenge your way of thinking and makes you go back to basics in order to understand. For example, when he debates whether BER is “bit error ratio” or “bit error rate”, it stopped me in my tracks to question if I was using the correct terminology, and why. For the record, when I started my career working on T1 line repeaters, I was taught it was “rate”. But, technically, Ransom’s assertion that it really is “ratio” is also correct.

Before you discount this and say, “In mathematics, there can be only one answer”, stay with me here, and let me try to explain where I’m coming from. According to Merriam-Webster dictionary, the definition of ratio is, “the indicated quotient of two mathematical expressions”, or “the relationship in quantity, amount, or size between two or more things: proportion”. If you take the number of bit errors and divide them by the total number of bits, then you have, by definition, a ratio, as Ransom claims. For example, if you have 1 error in 1 TBits of data, then you have a “bit error ratio” of 1E-12.

When you look up the word rate, in the same dictionary, the definition is, “reckoned value: valuation” or “a fixed ratio between two things”. In terms of BER, when it is defined as rate, the fixed ratio between two things is the number of errors over some period of time. Since a bit has a time component associated with it, you can convert the total number of bits into time by multiplying it by the bit time. For example, at 10 GB/s, the bit time is 100 ps. So 1TB of data takes 100 seconds to transmit all of the bits. If there was 1 bit error during that time, you would have a “bit error rate” of 1 error per 100 seconds.

In mission critical applications, we usually aspire to have error-free performance for the life of the product. As bit rates continue to climb, that’s an awful lot of bits. Theoretically, if you want your product to have a bit error rate of 1 error in 25 yrs, then, at 10GB/s, you would need to transmit 7.884E+18 bits;[25yrs*(60*60*24*365)sec/yr*10GB/s] to have a bit error ratio of 1.268E-19!

Bit error ratio, or bit error rate? It kind of reminds me of part of the song, “Let’s Call the Whole Thing Off”, by George and Ira Gershwin; “You like to-may-toes, and I like to-mah-toes”. At the end of the day, it’s still tomatoes. In the right context, I think both terms are equally valid. You need to be ambidextrous, so to speak, in your analysis and how you quote the number.

Written by Bert Simonovich

May 23, 2012 at 10:23 am