The Effects on Transmission Line Losses Due to Mixed Reference Plane Roughness Case Study
This article is an edited version of White Paper, “Heuristic Modeling of Transmission Lines due to Mixed Reference Plane Foil Roughness in Printed Circuit Board Stackups” [1].
Designing the right printed circuit board (PCB) stackup can make or break your product performance. If your product has circuitry that is transmission loss sensitive, then paying attention to conductor surface roughness is paramount.
Conductor surface roughness traditionally has been applied to copper foil to promote adhesion to the dielectric material. Early PCBs were only constructed with single or doublesided copper core laminates. The only important metric for copper was its purity and the roughness to improve peel strength. There was no such thing as a PCB stackup and nobody worried about impedance or transmission line losses.
But over the years PCBs have evolved into multilayer constructions with evermore attention being paid to impedance control and transmission line losses. Thus a PCB stackup definition became vital for consistent performance.
Like any construction project, you need a blueprint before you start building. Similarly for PCBs, you need a stackup drawing and detailed fabrication notes. Part of the stackup design process includes signal integrity (SI) modeling for characteristic impedance and transmission loss. If your design is running at 56Gig pulse amplitude modulation level 4 (PAM4), for example, you are probably looking at low loss dielectrics and low roughness copper for the signal traces.
But what is sometimes overlooked in the stackup, is the roughness of the reference planes. Often thin core laminate power and ground (GND) planes will specify reversetreated foils (RTF), which are rougher on the side that bonds to the prepreg. Sometimes one of these planes, usually GND, acts as a reference plane to an adjacent signal layer as shown in Figure 1. If that adjacent highspeed signal layer is using smoother copper than one or both reference planes, a higher insertion loss than expected for that layer will occur and possibly ruin your day.
A similar scenario could occur for high density interconnect (HDI) technology. This is a popular method to increase component density on modern PCBs. By the nature of their stackup construction, a rougher copper reference plane could sometimes also end up adjacent to a signal layer as well. Thus, if insertion loss is a concern, copper foil roughness of reference planes needs to be considered.
Figure 1 An example crosssection stripline geometry from a stackup showing thin core laminate (top) with RTF bonded to prepreg and adjacent to a highspeed differential pair with smooth foil.
So how do you know this before you design your stackup and build your first prototype? Since we do not have any empirical data to go by, we can rely on a heuristic, highlevel design (HLD) modeling method starting with published parameters found solely in manufacturer’s data sheets.
Heuristic HLD modeling is a practical technique that is not guaranteed to be perfect, but is still adequate in finding a satisfactory solution sooner, rather than later.
For dielectric parameters, we choose dielectric constant (Dk) / dissipation factor (Df) at or near the Nyquist frequency of the baud rate, then apply effective Dk (Dkeff) correction factor due to roughness, Equation 1 [5].
where:
H = thickness of core/prepreg; Rz is surface roughness of copper; Dk is as published in laminate supplier’s Dk/Df tables. Equation 1 assumes Rz of the foil on each side of the dielectric (core or prepreg) is the same.
For conductor loss, we use Rz roughness numbers from copper suppliers’ data sheets and oxide/oxide alternative Rz roughness numbers from your favorite fab shop, then apply the CannonballHuray roughness model [1][3].
CannonballHuray Model
The original Huray model is defined as:
Equation 2
The CannonballHuray model allows you to extract the right parameters using Rz roughness for core and prepreg sides of the foil [1]. Because the CannonballHuray model assumes the ratio of A_{matte}/A_{flat} = 1, and N_{i} = 14 spheres, the radius of a sphere (r) can be determined by:
and area of flat tile base (A_{flat}) by:
Equation 4
Wildriver Isola ITera® MT40 Custom Modeling Platform Case Study
To study the effect of reference plane roughness on transmission insertion loss, Wildriver Technology’s [7] custom modeling platform (CMP), shown in Figure 2, was used as a case study. This CMP was custom developed for Isola [6] to characterize their new ITera® MT40 very lowloss laminate material.
It combines 27 structures based on a consistent development of primitive structures; useful for performing a host of calibrations including automatic fixture removal, unknown THRU, WinCal XE™ calibration, and VNA gating and time transform analysis.
Figure 2 Wildriver Isola ITera® MT40 Custom Modeling Platform. Source: Wildriver Technology [7]
Stackup Validation
The PCB stackup is shown in Figure 3. Often PCB fab shop field application engineers (FAE) modify existing stackups and unintentionally make errors in transferring new parameters from data sheets into their software tools. Also, they may not necessarily know the design intent of the stackup. So the first step for any model correlation exercise is to sanitize the stackup, to ensure it meets the product design intent for signal integrity (SI) performance. In fact that is how the issue of different plane roughness was uncovered.
Since it is always a good practice to ensure the same roughness is specified for reference planes as the adjacent signal layers, I naively assumed it would be the case for any highspeed stackup. But that wasn’t the case here. Layers E1,E2 and E7, E8 specify 1oz RTF, while layers E3, E4 and E5, E6 specify 1oz VLP2 foil. Because the Isola ITera® MT40 CMP is intended to aid in modeling test structures, this is not a fatal flaw. On the contrary, it is a perfect platform to assess the effect of rougher reference planes.
Figure 3 Isola ITera® MT40 Custom Modeling Platform stackup. Source: Wildriver Technology [7]
Upon further review, it was discovered that the core laminates between E3,E4 and E5, E6 specified 1067/2×3313 glass styles, but this combination was not listed for 12 mil thickness. Instead, only 3×3313 core is offered. Because of that, the Dk shown is also wrong and will affect the impedance of the traces. The right Dk for 3×3313 is 3.53 instead if 3.33.
Foil Roughness
As mentioned earlier, the roughness of the foil affects the effective Dk, so we need to use the right number for our model validation. The standard VLP2 foil, used on ITera® MT40 core laminates is BFTZA foil. Optional RTF foil, used for layers E1, E2 and E7, E8, is TWLSB. Both are from Circuit Foil [8].
Relevant roughness parameters are shown in Figure 4. For the core side of the foil we are interested in the Rz parameters for the treated side listed in the table. But there are two Rz parameters, JIS B 601 and ISO 4287 specified. So which one do we use for modeling?
From IPCTM650 Section 1.2 [11] states, “The foil profile of foils shall be evaluated using the parameter Rz (DIN) or RTM, which is defined as the average maximum peak to valley height of five consecutive sampling lengths within the measurement length. This value is approximately equivalent to the values of profile determined from microsectioning techniques.”
and;
Section 1.3 states, “RZ (ISO) is a different parameter from Rz (DIN) and is not applicable to this method.”
Rz JIS represents the 10point mean value, which is the sum of the average of the 5 highest peaks and the 5 lowest valleys over the sample length. Rz DIN is similar; except it is defined as the average maximum peak to valley height of five consecutive sampling lengths within the measurement length. Thus we will use Rz JIS for modeling analysis.
Figure 4 Roughness parameters from Circuit Foil [8] data sheets. Top is VLP2 standard foil used on ITera® MT40, while bottom is RTF option used for relevant layers in the stackup
Determine Effective Dk Due to Roughness
The first step in HLD impedance modeling is to gather all the dielectric and foil data sheet parameters to determine the effective Dk.
Figure 5 summarizes thickness of core, prepreg and signal trace from the stackup geometry in Figure 3. Note that photos are for illustrative purposes only and are not actual crosssections from CMP PCB. Dk for core and prepreg were obtained from Isola ITera® MT40 Dk/Df tables [6].
Figure 5 Data sheet parameters for RTF/VLP2 foil roughness and dielectric properties for ITera® MT40 stackup geometry. Note: Photos are for illustrative purposes only and are not actual crosssections from CMP PCB. Surface roughness pictures source: Circuit Foil [8]
The top reference plane is TWLSB RTF foil with matte side 1 ≤ 7.5 JIS, obtained from Circuit Foil data sheet (Figure 4). The roughness surface profile is shown in the upper left. After OA smoothing, 1 ≤ 6.23 [1].
BFTZA foil is used for both sides of the core laminate. The top surface of the stripline trace, shown in the upper right picture, is the drum side of the foil, before OA treatment. After OA treatment, Rz2 ~ 1.9 μm [1].
The bottom surface profile of the stripline trace and the top surface of the bottom reference plane are the treated matte sides of the foil, shown in the bottom right and bottom left pictures respectively. They both share the same roughness (Rz3, Rz4 =2.5μm JIS) from the BFTZA data sheet (Figure 4).
The next step is to convert the imperial thickness units to metric, then use Equation 1 to determine Dkeff due to roughness for the prepreg and core.
Determine CannonballHuray Roughness Parameters
Several popular electronic design automation (EDA) tools include the CannonballHuray model directly as an option, so the respective Rz parameter is all that is needed.
Any of these tools can be used for HLD modeling, but my favorite is Polar SI9000 [9] because of its simplicity and sufficient accuracy for prefabrication modeling and analysis. Many fab shops use this tool for impedance prediction, so it is easy to stay in sync with them during the HLD stage of your project. Plus, it has the added benefit of modeling transmission loss and exporting Sparameters in touchstone format for further channel modeling in other tools.
Because Polar Si9000 assumes all the reference planes have the same roughness, it only allows Rz roughness parameters to be inputted for the matte and drum side of the signal trace. The best we can do, is take the average roughness of Rz1,Rz2 and Rz3,Rz4:
Simulation Correlation
When Dkeff due to roughness values were used instead of published Dk values, the new impedance prediction is 48.24 ohms, as shown in Figure 6.
Figure 6 Polar Si9000 impedance prediction with Dkeff due to roughness
Dkeff/Df for H1, H2 was then inputted into the causal dielectric model at 10GHz, as shown in Figure 7 (left), while Rz_{matte}, Rz_{drum} was inputted into the CannonballHuray model (right).
Figure 7 Causal Dkeff/Df dielectric and CannonballHuray roughness model input panels in Polar Si9000
After a 6inch transmission line was simulated, the Sparameters were exported in touchstone format. Keysight Pathwave ADS [10] was used for further processing and analysis.
Figure 6 compares simulated insertion loss vs deembedded reflectionless generalized modal (GM) Sparameter measurements, provided by Wildriver Technology [7]. As you can see there is excellent correlation without fitting to measured data!
Figure 8 HLD Insertion Loss simulation correlation for as designed stackup from data sheet and stackup parameters
Figure 9 plots simulated Dkeff vs measurements. At 10 GHz, simulated Dkeff is 0.105 (2.8%) lower than measured value. Without actual crosssection microscopic measurements, it is difficult to conclude if the published Dk is wrong, or if there is process variation with roughness parameters used in the model.
But it is also interesting to note that measured Dkeff is not a constant value over frequency, as shown in the ITera® MT40 Dk/Df tables. Instead Figure 9 reveals it varies over frequency, so the Dk/Df data sheet numbers are suspect.
Regardless, for the HLD modeling process, the simulation results are within acceptable tolerance.
Figure 9 HLD Dkeff simulation correlation for as designed stackup
Exploring the Effects of Alternate Foil Roughness
Now that we have good correlation to measurements, we can repeat the HLD modeling process to explore different foil roughness options. Figure 10 summarizes the thickness of core, prepreg and signal trace for VLP2/VLP2 foil (top) and VLP1/VLP1 foil (bottom). Note that photos are for illustrative purposes only and are not actual crosssections from CMP PCB.
Respective Dkeff, and CannonballHuray roughness parameters were recalculated with same steps as VLP2/RTF case above.
Figure 10 Alternate foil options simulated for whatif loss comparison. Top is VLP2/VLP2 foil parameters for all copper layers and bottom is VLP1/VLP1 foil parameters for all copper layers. Note: Photos are for illustrative purposes only and are not actual crosssection from CMP PCB. Surface roughness pictures source: Circuit Foil [8]
Figure 11 presents the simulation results of all three scenarios. As expected. when the reference plane foil roughness went from RTF/VLP2 to VLP2/VLP2 there was improvement. At 14 GHz it was 0.5 dB and at 28GHz it was 1 dB improvement.
When VLP1/VLP1 foil was used, it was further improved by 0.8 dB and 1.7 dB at 14 GHz and 28 GHz respectively. So if your design is loss sensitive, you might want to consider VLP1 foil option.
When we compare Dkeff plots, we see effective Dk approaches actual Dk/Df data sheet values in the tables when smoother copper is used, as expected [5].
Since Dkeff was derived by phase delay, propagation delay will be affected by rougher copper.
Figure 11 Whatif simulation comparison of VLP2/RTF, VLP2/VLP2, VLP1/VLP1 foil options and their effect on insertion loss and Dkeff
Conclusions
1. Roughness of reference planes make a significant difference in loss and phase delay, especially if one of the reference planes is RTF. If loss is important then all highspeed reference planes should have the same foil roughness specified
2. Heuristic HLD modeling method is a useful and accurate way to determine prefabrication impedance and loss predictions using data sheet parameters.
3. Published Dk from ITera® MT40 Dk/Df data sheet tables is not a flat constant over frequency.
4. Confirmed Rz JIS is the right parameter to use from Circuit Foil data sheet, instead of Rz ISO.
Acknowledgements
· Al Neves, CTO Wildriver Technology, for providing the custom modeling platform design details and measured data for the case study.
· Michael Gay, Director Business Development – Strategic Accounts at Isola Group, for providing foil supplier’s data sheets used on ITera® MT40 laminates.
References
[1] B. Simonovich, “Heuristic Modeling of Transmission Lines due to Mixed Reference Plane Foil Roughness in Printed Circuit Board Stackups”, White Paper, Lamsim Enterprises Inc.
[2] B. Simonovich, “Practical Method for Modeling Conductor Surface Roughness Using The Cannonball Stack Principle”, White Paper, Lamsim Enterprises Inc.
[3] L. Simonovich, “Practical method for modeling conductor roughness using cubic closepacking of equal spheres,” 2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), 2016, pp. 917920, doi: 10.1109/ISEMC.2016.7571773.
[4] L. Simonovich, “PCB Interconnect Modeling Demystified”, DesignCon 2019, Proceedings, Santa Clara, CA, 2019
[5] B. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”. DesignCon 2017, Proceedings, Santa Clara, CA, 2017
[6] Isola Group S.a.r.l., 3100 West Ray Road, Suite 301, Chandler, AZ 85226, URL: http://www.isolagroup.com/
[7] Wild River Technology LLC 8311SW Charlotte Drive Beaverton, OR 97007, URL: https://wildrivertech.com/
[8] Circuit Foil 6 Salzbaach, 9559 Wiltz, Grand Duchy of Luxembourg URL: https://www.circuitfoil.com/portfolio/
[9] Polar Instruments Si9000e [computer software] Version 2018, URL: https://www.polarinstruments.com/index.html
[10] Keysight Pathwave Advanced Design System (ADS) [computer software], (Version 2021 update2). URL:http://www.keysight.com/en/pc1297113/advanceddesignsystemads?cc=US&lc=eng.
[11] IPCTM650 Test Methods Manual 2.2.17A, Surface Roughness and Profile of Metallic Foils (Contacting Stylus Technique), 2/2001 Rev. A
[12] IPCTM650, 2.5.5.5, Rev C, Test Methods Manual
Characteristic Impedance – Where SI/PI Worlds Collide
Originally published Signal Integrity Journal, February 23, 2021
Signal and power integrity (SI/PI) simulations, measurements, and analysis usually live in two different worlds, but occasionally these worlds collide. One such collision occurs when we refer to characteristic impedance, Z_{0}. Traditionally the PI world lives in the frequency domain while the SI world lives in the time domain.
When designing a power distribution network (PDN) in the PI world, we are mostly interested in engineering a flat impedance below a target impedance from DC to the highest frequency components of the transient current. Practically this is achieved with a network of capacitors with different values connected to the respective power planes as shown in Figure 1.
Figure 1 A simplified model of a typical PDN courtesy [1].
In the real world, there is no such thing as an ideal capacitor. There are always parasitic elements known as equivalent series inductance (ESL) and equivalent series resistance (ESR). Physical characteristics of the PCB, like component mounting inductance, plane spreading inductance, via and BGA ball inductance, along with voltage regulator module (VRM) characteristics also contribute to the impedance profile. When connected together, the interaction of capacitors and parasitic inductance and resistance create a transfer impedance profile with resonant peaks and antiresonant nulls as shown in Figure 2.
The transfer impedance between the VRM and the load is calculated and plotted in the frequency domain with a loglog scale. The resulted impedance curve is then compared to the target impedance (Z_{target}), which is estimated based on the allowed noise ripple and maximum transient current. The flat target impedance is frequency independent in the analysis.
Figure 2 Impedance profile of the PDN as viewed from the pads on the die power rail courtesy [1].
Resonant peaks are due to ESL of one capacitor connected in parallel with another capacitor. Antiresonant nulls are due to the series combination of ESR, ESL, and C for each capacitor. Different capacitor values will have antiresonant nulls at different frequencies.
But in the PI world, there is a rarely talked about characteristic impedance, Z_{0}. In this case, it refers to the geometric average of the reactive impedance of a capacitor (XC) and reactive impedance of an inductor (XL).
Equation 1
At resonance, XL and XC intersect at the characteristic impedance and are equal as shown in Figure 3.
Figure 3 Inductive and capacitive reactance plot of ideal inductor and capacitor versus frequency. At resonance, XL and XC are equal and intersect at the characteristic impedance, Z_{0}. Simulated with Pathwave ADS [6].
This is a very important observation, and it is where the SI/PI worlds collide.
In the SI world, characteristic impedance, Z_{0 }refers to the instantaneous ratio of the voltage to current of a wave front traveling along a uniform transmission line without reflections. For an infinitely long uniform transmission line, Z_{0 }equals the input impedance.
The characteristic impedance of a lossy transmission line is defined as:
Equation 2
Where R is resistance per unit length; G is conductance per unit length; L is inductance per unit length; and C is capacitance per unit length. For a lossless uniform transmission line, R and G are assumed to be zero and thus the characteristic impedance is reduced to:
Equation 3
Time Domain Reflectometer
In the SI world, we usually use a time domain reflectometer (TDR) to measure characteristic impedance, but more often than not, the measured impedance we get is not what we predicted with a 2D field solver. Many 2D field solvers used by most PCB FAB shops only calculate the lossless characteristic impedance of the crosssectional geometry at a single frequency, defined by the dielectric constant (D_{k}). It has no input for conductor resistivity, dielectric loss, or how long the conductor(s) is.
So the issue is: we design the stackup, then do our SI modeling analysis based on stackup parameters and matching characteristic impedance. But the PCB FAB shop will often adjust the line width(s), over and above normal process variation, so that when measured, the impedance will fall within the specified tolerance, usually +/10 percent.
Part of the problem lies with the method used to take the measurements. Most PCB FAB shops follow IPCTM650 Test Methods Manual [2]. But it has limitations because Z_{0 }measured is derived and cannot be directly measured. The reason is the measurements include resistive and dielectric losses, up to the point where the measurement takes place along the TDR plot.
Resistive loss often results in a slow monotonic rise in the impedance profile, shown in the example TDR plot of Figure 4. IPCTM650 specifies a measurement zone between 3070 percent to avoid probing induced ringing affecting the measurements. Most PCB FAB shops will measure an average impedance over this range, usually in the center region.
Depending on the linewidth, thickness and dielectric dissipation factor (D_{f}), the slope of the monotonic rise will vary.
Figure 4 Example TDR plot showing slow monotonic rise in impedance due to resistive losses and IPCTM650 measurement zone.
The problem is that the IPCTM650 test method was last updated back in 2004, when higher dielectric loss, along with wider line widths and thicker copper weights, were used more often. A higher D_{f} tends to compensate for resistive loss by flattening the slope as shown in Figure 5.
On the bottom left is a simulated TDR plot using a high loss dielectric with D_{f} = 0.024. The right side has the exact same geometry properties except D_{f} = 0.004. The average impedance, when measured at the 50 percent point, is 49.8 Ohms on the left side vs. 51.4 Ohms on the right side. We also confirm flatter slope for high loss material.
The actual characteristic impedance predicted by a Polar SI9000 2D field solver [5] in Figure 5 is 49 Ohms. For higher loss material, measuring within the measurement zone would pass without any issues. But for lower loss material, the resistive loss dominates and measuring within the measurement zone will give ~5 percent higher impedance reading compared to the higher loss material. The correct measurement point for Z_{0 }is, in fact, the initial dip, equivalent to the field solver prediction. Depending on the tolerance specified, this may affect yield and cost.
Figure 5 Characteristic impedance prediction by Polar SI9000 2D field solver [5] (top). Simulated 2 inch TDR plots using a high loss dielectric (bottom left) vs. low loss dielectric with exactly the same geometry (bottm right). A higher Df compensates for higher resistive loss thereby flattening the curve. Simulated with Pathwave ADS [6].
Today, with the push to low loss dielectric and finer line widths with thinner copper weights, measuring the true transmission line characteristic impedance using a TDR becomes more challenging. This is even more so when measuring differential impedance, because a change in line width space geometry can have a more profound effect on measured differential impedance.
Using the first article build of a new design, as an example, let’s assume the correct characteristic impedance, when measured at the beginning of the slow monotonic rise of a TDR plot, is on the high end of nominal +10 percent tolerance. Let’s say it’s 54 Ohms. But because of the low loss dielectric and high resistive loss, the TDR measurement at the midpoint is now reading 5% higher at 57 Ohms. This would imply the impedance is now out of spec over nominal and the board would be scrapped.
The PCB fab shop will then go back and adjust the linewidth accordingly for the next build to bring the measurement within range to their measurement set up. Doing this effectively lowers the true nominal characteristic impedance!
If subsequent manufacturing variations pushes the measured impedance within the measurement zone on the low end of the 10 percent tolerance, say 44 Ohms, then the true characteristic impedance, if measured at the initial dip, will be 5 percent lower at 42 Ohms and be out of spec. But the board will pass because it was measured following IPCTM650 test method.
2port Shunt Measurement
But what if there were another way? What if we could borrow impedance measuring techniques from the PI world to determine the true transmission line characteristic impedance in the SI world? Well there is. Enter the 2port shunt measurement technique.
For example, in the PI world, to measure ESL and ESR of a chip capacitor, of a device under test (DUT), a 2port shunt measurement is often used. It is much like the 4point Kelvin measurement technique used to measure very low DC resistance.
The 2port shunt measurement is usually done with a 2port vector network analyzer (VNA). Port 1 of the VNA sends out a calibrated signal, and port 2 measures the voltage signal across the DUT. Often an isolation transformer is also used to break the inherent ground loop when measuring ultralow impedances [3].
Once the measurements have been completed and Sparameters saved in touchstone format, further analysis can be done in your favorite SPICE simulator. Figure 6 is a generic schematic using popular Pathwave ADS [5] that can be used for 2port shunt analysis.
When port 1 and port 2 are connected to port 1 of the DUT and port 2 of the DUT is grounded, the impedance of the DUT can be determined by [3];
Equation 4
Figure 6 Generic Pathwave ADS [6] schematic used for 2port shunt analysis on a S2P file for DUT.
If we replace the DUT in Figure 6 with a capacitor and inductor, we get an impedance plot shown in Figure 7. As we saw earlier, when we take the geometric average of the inductive and capacitive reactance using Equation 1, we get the characteristic impedance. If we apply Equation 4 to the results of a 2port shunt measurements of a capacitor and inductor, we get exactly the same results as shown in the top of Figure 7.
When we replace the capacitor and inductor with a Sparameter file of a transmission line model from Figure 5, we get the plot shown at the bottom of Figure 7. Except for the resonant nulls and peaks, up to a certain frequency, the impedance of a transmission line looks like the impedance of a capacitor when the farend is open, and looks like the impedance of an inductor when the farend is shorted. And because of that, this is where the two worlds collide!
If we take the geometric average of the impedance when the farend is open (Z_{open}) or shorted (Z_{short}), we get the characteristic impedance at that frequency. We note where the red and blue impedance lines first intersect, is exactly the geometric average characteristic impedance at that frequency.
Also worth noting, the lines intersect at half of the frequency between the peaks and valleys at higher frequencies as well.
Figure 7 Impedance of inductive and capacitive reactance vs. frequency (top) and impedance of a transmission line vs. frequency (bottom) when the farend is open (solid red) compared to when the farend is shorted (solid blue). The intersection of the red and blue lines is exactly the characteristic impedance. Simulated with Pathwave ADS [5].
We can see this more clearly if we replot Figure 7 bottom using a linear scale for the xaxis, as shown in Figure 8. This is a very powerful observation. What this means is that when we measure the impedance half way between a peak and adjacent valley, of either the red or blue plot, it is the characteristic impedance of the transmission line at that frequency.
Thus, only an open or shorted end measurement is all that is needed to determine the characteristic impedance. For example, if we look at the red curve alone, then measure the first resonant null (m14) and adjacent peak (m15), the characteristic impedance (mag(Zopen) is measured exactly at one half the frequency between the two (m16).
Figure 8 Impedance of a transmission line vs. frequency on a linear scale when the farend is open (solid red) compared to when the farend is shorted (solid blue). The intersection of the red and blue lines half way between respective peaks and valleys is the characteristic impedance. Simulated with Pathwave ADS [6].
The first resonant red null and blue peak represent the quarterwave resonant frequency due to open and shorted end. Each respective red null and blue peak following are the odd harmonics of the first quarterwave resonant frequency.
Knowing this, we can now determine the phase or time delay (TD) of the transmission line as being one quarter of the period of the resonant frequency (f_{0}).
Equation 5
Because resonant nulls and peaks occur at the resonant frequency, we can also determine the effective dielectric constant (D_{keff}). Given the speed of light (c) = 11.8 in. per nanosecond, the length of the transmission line (len) in in. and quarterwave resonant frequency (f_{0}), D_{keff} can be determined by:
Equation 6
CMP28 Case Study
Figure 9 Photo of a portion of CMP28 test platform courtesy of Wildriver Technology [8] used for measurement validation.
To test the accuracy of this method, measured data from a CMP28 test platform, shown in Figure 9, was used for measurement validation. Sparameter (s2p) files from 2 inch and 8 inch singleended stripline traces were provided as part of CMP28 design kit courtesy of Wildriver Technologies [8]. The 6inch transmission line segment Sparameter data was deembedded courtesy of AtaiTec Corporation [9].
The characteristic impedance, based on trace geometry and stackup parameters, was modeled in Polar SI9000 [5]. Using D_{k }from data sheet tables @ 10GHz, and correcting for conductor roughness [10], the characteristic impedance predicted was 49.66 Ohms, as shown in Figure 10.
Figure 10 Polar SI9000 fieldsolver [5] characteristic impedance prediction of CMP28 trace geometry.
Touchstone Sparameter DUT files were connected with farend open, shorted, and terminated as shown in Figure 11. The TDR plot, with farend terminated, shows an impedance of 50.57 Ohms, when measured at the initial peak. Then it takes an immediate dip to approximately 50 Ohms before continuing with a slow monotonic rise with some ripples. If the DUT was a uniform trace, with connector discontinuity deembedded, we would not see the initial peak followed by the dip. This signature strongly suggests that the DUT is not uniform and thus it is very difficult to determine the actual characteristic impedance using IPCTM650 test method alone.
But only after taking 2port shunt measurements can we confirm the true characteristic impedance. As shown, Zoavg is 50.68 Ohms where the red and blue curves cross at 122.5 MHz, and confirms the true measurement point in the TDR plot is the initial peak. Both are about 1 Ohm higher compared with 2D field solver results in Figure 10.
If the length of the transmission line simulated above is 6 in. and f_{0 }=248.2 MHz, then TD = 1 ns and D_{keff} = 3.92, using Equation 5 and Equation 6 respectively.
Figure 11 Measured results from a CMP28 test platform design kit, courtesy of Wildriver Technology [8].
But wait a minute. Why is D_{keff} is higher than what was used in the 2D field solver in Figure 10?
One reason is due to process variation of the material and fabrication. The actual D_{keff} is determined by the final thickness of dielectric and the roughness of the copper, which also increases inductance affecting TD [10] [11]. But the main reason is D_{k }is frequency dependent and the value used in the field solver was at 10 GHz, based on laminate supplier’s D_{k}/D_{f} tables.
Since TD, ultimately determines D_{keff}, it does not represent the intrinsic property of the dielectric material. Because D_{keff} varies with frequency, it was calculated at the first resonant null of 248.2 MHz, which is at a much lower frequency for D_{k} than the frequency originally used to select D_{k }in the field solver.
As can be seen in Figure 12, a simulated vs. measured 2port shunt frequency plot, with farend open and shorted, we get exactly the same information, compared to the traditional method used to validate characteristic impedance and D_{keff}.
If we measure the 39^{th} odd harmonic frequency (H) at 9.884GHz for the resonant null closest to 10GHz, equating to the value of D_{k} used in Polar Si9000 2D field solver, D_{keff} can be calculated with Equation 7:
Equation 7
The bottom right plot of Figure 12, shows D_{keff} simulated (blue) vs. measured (red). As we can see, the measured D_{keff} at 248.7 MHz is 3.94; pretty much agreeing with our earlier calculation of 3.92 using Equation 6. Furthermore, when we compare D_{keff} = 3.76 at 9.884 GHz, it agrees with our calculation for the 39^{th} harmonic frequency from Equation 7. The reason there is still a slight difference in D_{keff} is because the added delay due to inductance due to roughness [11] was not factored into the simulated model.
The bottom left is a TDR plot that shows measured impedance (red) vs. simulated (blue) over time. The marker at the beginning of the initial dip (m6) represents the characteristic impedance with highest frequency harmonics included in the incident step edge of TDR waveform. The marker at the end (m16) represents the impedance at twice the TD with high frequency harmonics attenuated due to dispersion of the lossy dielectric and resistance of trace length.
When we measure Zoavg_meas impedance of DUT at 9.884GHz, at the top plot of Figure 12, it agrees pretty well with the simulated and measured TDR plot at the initial step.
Figure 12 Comparison of PI world 2port shunt measurement results for transmission line characteristic impedance and D_{keff} compared to traditional SI world measurement results. Top plot is the 2port shunt simulated vs. DUT impedance measurements at the fundamental and 39^{th} harmonic frequencies. Bottom left is beginning and end impedance measurements on TDR plot. Bottom right measuring equivalent D_{keff} at fundamental and 39^{th} harmonic frequencies.
Summary and Conclusion
Sometimes, when SI and PI worlds collide, we get the best of both worlds. By borrowing a simple 2port shunt impedance measuring technique from the PI world, we have another tool at our disposal to measure true characteristic impedance, TD, and effective D_{k} from a uniformly designed transmission line in the SI world. The advantage is, unlike a TDR measurement, measuring true characteristic impedance using 2port shunt method is not influenced by resistive or dielectric losses.
References

L. Smith, S. Sandler, E. Bogatin, “Target Impedance Is Not Enough,” Signal Integrity Journal, Vol. 1, Issue 1, January 2019; URL: https://www.signalintegrityjournal.com/ext/resources/MEDIAKIT2019/January2019PrintIssue/SIJJanuary2019Issue_eBook_V2.pdf

IPCTM650 Test methods Manual, Number 2.5.5.7, “Characteristic Impedance of Lines on Printed Boards by TDR”, Rev. A, March, 2004

I. Novak, J. Millar, “FrequencyDomain Characterization of Power Distribution Networks,” Artech House, 685 Canton St., Norwood, MA, 02062, 2007.

Pathwave Advanced Design System (ADS) [computer software], Version 2021, URL: http://www.keysight.com/en/pc1297113/advanceddesignsystemads?nid=34346.0&cc=CA&lc=eng

Polar Instruments Si9000e [computer software], Version 2018, URL: https://www.polarinstruments.com/index.html

Keysight Pathwave Advanced Design System (ADS) [computer software], Version 2021, URL: http://www.keysight.com/en/pc1297113/advanceddesignsystemads?cc=US&lc=eng.

E. Bogatin, “Bogatin’s Practical Guide to Transmission Line Design and Characterization for Signal Integrity”, Artech House, 685 Canton St., Norwood, MA, 02062, 2020

Wild River Technology LLC 8311 SW Charlotte Drive Beaverton, OR 97007. URL: https://wildrivertech.com/

AtaiTec Corporation, URL: http://ataitec.com/products/isd/

B. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness“, DesignCon 2017 proceedings, Santa Clara CA.

V. DmitrievZdorov, B. Simonovich, I. Kochikov, “A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics”, DesignCon 2018 proceedings, Santa Clara, CA.

I. Novak et al, “Determining PCB Trace Impedance by TDR: Challenges and Possible Solutions”, DesignCon 2013 proceedings, Santa Clara, CA.

S. Sandler, “Easy trick to measure plane impedance with VNA”, EDN Asia, 2014, URL: https://archive.ednasia.com/www.ednasia.com/STATIC/PDF/201410/EDNAOL_2014OCT21_TEST_TA_01.pdf%3FSOURCES=DOWNLOAD
Singleended to MixedMode Conversions
Originally published in Signal Integrity Journal Magazine, July 2020
Signal Integrity (SI) engineers almost always have to work with Sparameters. If you haven’t had to work with them yet, then chances are you will sometime in your SI career. As speed moves up in the doubledigit GB/s regime, many industry standards are moving to serial linkbased architectures and are using frequency domain compliance limits based on Sparameter measurements.
A vector network analyzer (VNA) is the test instrument of choice to measure Sparameters from a device under test (DUT). By definition, each Sparameter (S_{ij}) is the ratio of the sine wave voltage coming out of a port to the sine wave voltage that was going in to a port (Equation 1). Each Sparameter is complex with a magnitude and a phase.
Equation 1
Sufficed to say, for mathematical reasons, the indexes refer to the port in which the voltages are coming or going. This is counter intuitive to our normal train of thought and is important to be cognisant of this relationship when working with Sparameters.
Singleended Sparameters
Figure 1 shows an example of a 1Port, 2Port and 4Port DUTs and their respective Sparameter matrices representing uniform transmission lines with respective port index labelling. Each Sparameter in the matrix are singleended measurements from one port to another.
A 1Port DUT has one Sparameter (S_{11}) shown in red. It is the ratio of the voltage coming out of Port 1 to the voltage going into Port 1. As a measure of reflected energy out of Port 1, it is also known as return loss (RL)
A 2Port DUT has 4 Sparameters shown in blue. Sparameters with the same index subscript numbers, i.e. S_{11,} S_{22} are RL. Sparameters with alternate index subscript numbers, are a measure of transmitted energy and is the ratio of the voltage coming out of a Port to the voltage going into the opposite Port. It is also known as insertion loss (IL). For example, S_{12} is the ratio of the voltage coming out of Port 1 to the voltage going into Port 2, whereas S_{21} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 1.
Figure 1 From left to right examples of 1Port (Red), 2Port (Blue), 4Port (Black) DUTs and their respective Sparameter matrices.
A 4Port DUT has 16 Sparameters, divided into 4 quadrants, shown in black. As you can see the number of Sparameter combinations is the square of the number of ports. In this example, the top left quadrant 1 and bottom right quadrant 4 are the same as individual 2Port DUTs with different port indices. They are described as:
Quadrant 1:

S_{11} is the ratio of the voltage coming out of Port 1 to the voltage going into Port 1. It is the RL out of Port 1.

S_{12} is the IL and is the ratio of the voltage coming out of Port 1 to the voltage going into Port 2. It is the IL from Port 2 to Port 1.

S_{21} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 1. It is the IL from Port 1 to Port 2. For a uniform transmission line, S_{21} = S_{12}.

S_{22} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 2. It is the RL out of Port 2. For a uniform transmission line, S_{22} = S_{11}.
Quadrant 4:

S_{33} is the ratio of the voltage coming out of Port 3 to the voltage going into Port 3. It is the RL out of Port 3

S_{34} is the ratio of the voltage coming out of Port 3 to the voltage going into Port 4. It is the IL from Port 4 to Port 3

S_{43} is the ratio of the voltage coming out of Port 4 to the voltage going into Port 3. It is the IL from Port 3 to Port 4. For a uniform transmission line, S_{43} = S_{34}.

S_{44} is the ratio of the voltage coming out of Port 4 to the voltage going into Port 4. It is the RL out of Port 4. For a uniform transmission line, S_{44} = S_{33}
Sparameters in the top right quadrant 2 and bottom left quadrant 3 describe the nearend and farend coupling of the respective ports. When unwanted coupling happens at the nearend, it is referred to as nearend cross talk, or NEXT. When it happens at the farend, it is known as farend crosstalk, or FEXT.
Quadrant 2:

S_{13} is the ratio of the voltage coming out of Port 1 to the voltage going into Port 3. It is the coupling or NEXT from Port 3 to Port 1.

S_{14} is the ratio of the voltage coming out of Port 1 to the voltage going into Port 4. It is coupling or FEXT from Port 4 to Port 1.

S_{23} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 3. It is coupling or FEXT from Port 3 to Port 2.

S_{24} is the ratio of the voltage coming out of Port 2 to the voltage going into Port 4. It is coupling or NEXT from Port 4 to Port 2.
Quadrant 3:

S_{31} is the ratio of the voltage coming out of Port 3 to the voltage going into Port 1. It is the coupling or NEXT from Port 1 to Port 3.

S_{32} is the ratio of the voltage coming out of Port 3 to the voltage going into Port 2. It is coupling or FEXT from Port 2 to Port 3.

S_{41} is the ratio of the voltage coming out of Port 4 to the voltage going into Port 1. It is coupling or FEXT from Port 1 to Port 4.

S_{42} is the ratio of the voltage coming out of Port 4 to the voltage going into Port 2. It is coupling or NEXT from Port 2 to Port 4.
Although there is no industry standard for labeling a 4 or more port DUT, a practical way is to use the port order shown so that the 2Port DUT is a subset of the top left quadrant of the 4Port DUT. When you do this, the port order labeling is consistent as you increase the number of ports; with odd ports on the left and even ports on the right. S_{12} and S_{21} always describe the IL terms; while S_{13 }and S_{31} define the NEXT terms.
But sometimes 3^{rd} party 4port Sparameters are labeled with ports 1 and 2 are on the left side, while ports 3 and 4 are on the right side. In this configuration, S_{31} and S_{42} are now the IL terms. This is counter intuitive when moving from 2Port to 4 or more Port DUT and leading to potential confusion when cascading Sparameters to build a channel model, or converting to mixedmode Sparameters. Whenever you get Sparameter files from 3^{rd} party, it is always prudent to test it and compare IL plots against port order to ensure you are using them correctly.
Typically, 4port Sparameters are saved in Touchstone format with a .snp extension, where n is the number of ports. Many Electronic Design Automation (EDA) and circuit simulation software tools allows you to view and plot Sparameters from Touchstone files.
Figure 2 is a schematic of a 4port Sparameter component used in Keysight ADS. When the component is linked to appropriate .s4p touchstone file and ports connected as shown, the 16port Sparameter matrix can be plotted and analyzed.
Figure 2 Keysight ADS schematic used to plot 4Port singleended Sparameters.
The 1port and 2port Sparameters are included in the same plot as the 4port Sparameters plotted in Figure 3. The top left (red) and bottom right (green) quadrants plot the return loss (RL) and insertion loss (IL), while the top right (blue) and bottom left (magenta) quadrants plot the NEXT and FEXT.
Figure 3 An example of 4Port Sparameter singleended plots of a uniform transmission line.
Mixedmode Sparameters
SI engineers often have to check channel models and Sparameter measurements against industry standard compliance plots. Many of those plots are in terms of mixedmode Sparameters, which means the singleended measurements need to be converted to mixedmode matrix.
Two singleended transmission lines with coupling are also known as a differential pair, as shown in Figure 4. When we talk about singleended transmission lines with coupling, we are usually interested in their singleended properties like characteristic impedance (Zo), phase delay, and NEXT/FEXT relationships as described above.
But when we talk about a differential pair, we are interested in the mixedmode Sparameters like differential and common signals and how they interact within the pair. Because we are describing the exact same interconnect, they are equivalent.
When describing a differential pair, there are only four possible outcomes in response to an input signal as defined by the mixedmode Sparameter matrix:

A differential signal enters the differential pair and a differential signal comes out

A differential signal enters the differential pair and a common signal comes out

A common signal enters the differential pair and a differential signal comes out

A common signal enters the differential pair and a common signal comes out
Figure 4 Singleended vs mixedmode Sparameter matrices of two coupled transmission lines.
Mixedmode Sparameters in each quadrant are described as:
SDD Quadrant (Red):

SDD_{11} is the ratio of the differential signal coming out of Port 1 to the differential signal going into Port 1. It is the differential RL out of Port 1.

SDD_{12} is the ratio of the differential signal coming out of Port 1 to the differential signal going into Port 2. It is the differential IL from Port 2 to Port 1.

SDD_{21} is the ratio of the differential signal coming out of Port 2 to the differential signal going into Port 1. It is the differential IL from Port 1 to Port 2.

SDD_{22} is the ratio of the differential signal coming out of Port 2 to the differential signal going into Port 2. It is the differential RL out of Port 2.
SDC Quadrant (Blue):

SDC_{11} is the ratio of the differential signal coming out of Port 1 to the common signal going into Port 1.

SDC_{12} is the ratio of the differential signal coming out of Port 1 to the common signal going into Port 2.

SDC_{21} is the ratio of the differential signal coming out of Port 2 to the common signal going into Port 1.

SDC_{22} is the ratio of the differential signal coming out of Port 2 to the common signal going into Port 2.
SCD Quadrant (Magenta):

SCD_{11} is the ratio of the common signal coming out of Port 1 to the differential signal going into Port 1.

SCD_{12} is the ratio of the common signal coming out of Port 1 to the differential signal going into Port 2.

SCD_{21} is the ratio of the common signal coming out of Port 2 to the differential signal going into Port 1.

SCD_{22} is the ratio of the common signal coming out of Port 2 to the differential signal going into Port 2.
SCC Quadrant (Green):

SCC_{11} is the ratio of the common signal coming out of Port 1 to the common signal going into Port 1.

SCC_{12} is the ratio of the common signal coming out of Port 1 to the common signal going into Port 2.

SCC_{21} is the ratio of the common signal coming out of Port 2 to the common signal going into Port 1.

SCC_{22} is the ratio of the common signal coming out of Port 2 to the common signal going into Port 2.
Singleended Sparameters, with port order shown in Figure 4, can be mathematically converted into mixedmode Sparameters using equations shown in Table 1.
Alternatively, Keysight ADS can simplify this process using equations on 4Port singleended or using 4port Balun components, as shown in Figure 5.
Figure 5 Keysight ADS schematic used to convert from 4Port singleended to 2Port mixedmode Sparameters using equations or 4Port Balun components. Differential and common port numbering as D1, D2, C1, C2 respectively.
Figure 6 plots mixedmode Sparameters from equations in Table 1. Each quadrant is color coded to coincide with the respective table quadrants.
Figure 6 An example of 4Port Sparameter mixedmode plots of a differential transmission line.
References:
[1] M. Resso, E. Bogatin, “Signal Integrity Characterization Techniques”, International Engineering Consortium, 300 West Adams Street, Suite 1210, Chicago, Illinois 606065114, USA, ISBN: 9781931695930
https://www.amazon.com/SignalIntegrityCharacterizationTechniquesBogatinebook/dp/B07P9277WY/ref=sr_1_fkmr0_1?keywords=bogaitn+resso&qid=1581289220&sr=81fkmr0
[2] A. Huynh, M. Karlsson, S. Gong (2010). MixedMode SParameters and Conversion Techniques, Advanced Microwave Circuits and Systems, Vitaliy Zhurbenko (Ed.), ISBN: 9789533070872,InTech, Available from: http://www.intechopen.com/books/advancedmicrowavecircuitsandsystems/mixedmodesparametersandconversiontechniques.
[3] Alfred P. Neves, Mike Resso, and ChunTing Wang Lee, “Sparameters: Signal Integrity Analysis in the Blink of an Eye”, Signal Integrity Journal, https://www.signalintegrityjournal.com/articles/432sparameterssignalintegrityanalysisintheblinkofaneye
Keysight Advanced Design System (ADS) [computer software], (Version 2020). URL: http://www.keysight.com/en/pc1297113/advanceddesignsystemads?cc=US&lc=eng.
Differential Impedance and Why We Care
Originally published in Signal Integrity Journal April 14,2020
What is Differential Impedance and Why do We Care?
Simply put, differential impedance is the instantaneous impedance of a pair of transmission lines when two complimentary signals are transmitted with opposite polarity. For a printed circuit board (PCB) this is a pair of traces, also known as a differential pair. We care about maintaining the same differential impedance for the same reason we care about maintaining the same instantaneous impedance of a singleended (SE) transmission line: to avoid reflections.
There is really nothing special about differential pairs, other than maintaining the correct differential impedance. But you must understand the implications of the spacing between the traces in a pair.
The differential impedance is simply twice the oddmode impedance of each trace. SE impedance is the impedance of a single trace and only equals the oddmode impedance when there is little or no intrapair coupling between them. When the traces are brought closer together, the differential impedance is reduced, unless the line widths are adjusted to compensate. (More about this later.)
Figure 1 shows the effect on intrapair coupling of a pair of edgecoupled stripline traces driven differentially. The top figure shows electromagnetic fields surrounding a loosely coupled pair of traces 3.5 linewidths apart. The bottom figure shows a closely coupled pair at 1.5 linewidths apart. The red plus trace is current flowing into the page while the minus blue trace is current flowing out of the page.
The circular lines surrounding each trace are the magnetic fields representing loop inductance. The direction of rotation is based on current direction, using the righthand rule. The electric field (efield) lines are perpendicular to the magnetic field lines. They are a measure of capacitance.
Figure 1. Effect on intrapair coupling of a pair of edgecoupled stripline traces driven differentially. Top figure shows electromagnetic fields surrounding a loosely coupled pair of traces 3.5 linewidths apart. Bottom figure shows a closely coupled pair at 1.5 linewidths apart.
When the traces are loosely coupled, the electric and magnetic field lines are fairly symmetrical around each trace, and are mirror images of one another about the center line between them. Most of the respective efield coupling is to the reference ground planes. As the traces are moved closer to one another, the counterrotating rings compress about the centerline, lowering the inductance. At the same time, more of the efield lines along the inside edge of each trace tend to couple to one another, increasing the capacitance.
Because of the way the EMfields interact along the centerline, we can think of it as a virtual ground (VGND) reference plane. They behave exactly the same way as if there is a solid reference plane between them.
OddMode Impedance
Consider a pair of equal width microstrip line traces, labeled 1 and 2, with a constant spacing between them as shown in Figure 2. Assuming lossless transmission lines, each individual trace, when driven in isolation, will have a SE characteristic impedance Zo, defined by the selfloop inductance (L11, L22) and selfcapacitance (C11, C22) with respect to the GND reference plane.
When the pair of traces are driven differentially, the mode of propagation is odd. The electromagnetic field interaction is shown in Figure 1. When the intrapair spacing is close, there will be electromagnetic coupling defined by the mutual inductance (Lm) and mutual capacitance (Cm).
The proximity of the traces to a reference plane influences the amount of electromagnetic coupling between traces. The closer the traces are to the reference plane, the lower the selfloop inductance and stronger selfcapacitance; resulting in a lower mutual inductance, and weaker mutual capacitance between traces. The end result is a lower differential impedance.
Figure 2. Pair of microstrip traces showing selfloop inductance (L11, L22), selfcapacitance (C11, C22), mutual capacitance (Cm) and mutual inductance (Lm) when line 1 and line 2 are driven differentially.
A 2D field solver is usually used to extract the parameters for a given geometry. Once the resistance, inductance, conductance, and capacitance (RLGC) parameters are extracted, an L C matrix can be set up as follows:
L11 L12 C11 C12
L21 L22 C21 C22
The selfloop inductance and selfcapacitance for trace 1 and 2 are L11, C11, L22, C22 respectively. In a perfectly symmetrical differential pair, the offdiagonal (12, 21) terms in each matrix are the mutual inductance and mutual capacitance respectively. The LC matrix can be used to determine the oddmode impedance. It can be calculated by the following equation [1]:
Equation 1
Where:
Zodd = odd mode impedance
Ls = selfloop inductance = L11 = L22
Cs = selfcapacitance = C11 = C22
Lm = mutual inductance = L12 = L21
Cm = mutual capacitance = C12 =C21
Example
A Polar SI9000 field solver is used to compare a loosely coupled pair, with 4 mil traces, separated by 20 mil space, vs. a SE transmission line with the same dielectric thickness (see Figure 3). The LC matrix was extracted at 10GHz. As can be seen, the oddmode impedance of the loosely coupled pair equals the characteristic impedance of the SE trace, and thus differential impedance would be the same.
Figure 3. Comparison of a loosely coupled pair (left), with 4 mil traces, separated by 20 mil space, vs. a SE transmission line (right) with the same dielectric thickness. Oddmode impedance of the loosely coupled pair equals the characteristic impedance of the SE trace.
But if you route a pair of traces with close coupling, the oddmode impedance is less than the SE impedance for the same trace width (unless you adjust the line width). For example, on the left side of Figure 4, a 444 mil geometry has a differential impedance of 91 Ohms. In order to get 100 Ohms differential, the line width must be reduced to 3.35 mils and space adjusted to 4.65 mils to keep the same 12 mil centercenter pitch, shown on right.
Figure 4. Comparison of 444 mil geometry (left) vs. 3.354.653.35 geometry (right) to achieve 100 Ohm differential impedance for the same centercenter pitch.
But it doesn’t end there.
For some industry standards, there is usually a very short reach (VSR) spec which has a maximum channel loss defined. For example, the IEEE 802.3 CAUI4 chipmodule (C2M) spec budgets 7.5 dB at 12.89 GHz Nyquist frequency from the chip’s pins to a faceplate module’s pins, e.g. small formfactor pluggable (SFP) module. Because of modern topofrack routers and switches, it is not unusual to have 10 or more inches between the main switch chip and SFP module, the differential pair geometry design becomes important to satisfy both differential impedance and insertion loss (IL).
Reduced line width and tighter coupling results in higher loss over the length of the channel. Using the above examples, differential IL is plotted in Figure 5 for all three differential pairs. Loose coupling is shown in green; tight coupling without line width adjustment (Tight1) is shown in red, while tight coupling with line width adjustment (Tight2) is shown in blue.
As you can see, there is about a half dB difference at 12.89 GHz between loose coupling and both tight coupling examples over 10.6 inches. Tight coupling lowers IL, regardless if line width is adjusted to meet differential impedance. In this example, there is only 0.1 dB delta between Tight1 and Tight2, which suggests most of the higher loss is due to tighter coupling.
Figure 5. Differential IL comparison of loose coupling (green); Tight1 coupling without line width adjustments (red) and Tight2 coupling with line width adjustment (blue).
This can be explained by reviewing SE to differential mixedmode conversion. Given a 4port Sparameter, with SE port order as shown in Figure 6, the differential IL is determined by;
Equation 2
Where:
SDD21 = the differential IL defined by the ratio of the differential signaling coming out of port 2 to the differential signal going into port 1
S21 = the SE IL defined by the ratio of the SE signaling coming out of port 2 to the SE signal going into port 1
S43 = the SE IL defined by the ratio of the SE signaling coming out of port 4 to the SE signal going into port 3
S23 = farend crosstalk coupling from port 3 to port 2
S43 = farend crosstalk coupling from port 4 to port 3
As you can see from Equation 2, when the traces get closer together, and the coupling terms get larger, differential IL increases.
Figure 6. SE 4port Sparameter port labeling.
Figure 7 plots differential TDR of all three examples. The steeper monotonic rise of the blue trace is due to higher resistive loss of 3.35 mil traces, as compared to the 4 mil traces in the other two examples.
Figure 7. Differential TDR comparison of loose coupling (green); Tight1 coupling without line width adjustments (red) and Tight2 coupling with line width adjustment (blue).
To summarize then, it doesn’t matter if a differential pair is tightly coupled or loosely coupled. Properly engineered, both can be designed to properly match the output driver impedance. But as we have seen, each will have advantages and disadvantages.
Tighter coupling gives you better routing density at the expense of higher loss. Loose coupling allows for easier routing around obstacles and less loss. But in either case, they must be designed and measured for differential impedance.
So why is this important?
PCB fabrication shops use impedance as a metric to determine if the board has been fabricated to specification. Because the oddmode impedance of a tightly spaced pair of traces depends on driving both traces differentially, you will not be able to determine the differential impedance by just measuring SE impedance of a tightly coupled pair like you could with two uncoupled traces.
References:

E. Bogatin, “Signal Integrity Simplified”, 3rd edition, Prentice Hall PTR, 2018

Keysight Advanced Design System (ADS) [computer software], (Version 2020)

Polar Instruments Si9000e [computer software] Version 2017
How Authorship Advances Your Career and Become an Industry Influencer
So how can authorship advance your career and lead to becoming an industry influencer?
Well first of all, it offers a chance for deep learning of a subject matter. When you have to capture your thoughts on paper, you suddenly realize you may not know as much about the subject as you think you know. It forces you to do more research on the topic so that the information you are trying to covey is accurate.
It demonstrates thought leadership at your work and the industry. You become the subject matter expert on that topic. And over time, the path to your desk, is worn from all the traffic to your cubicle. If you are self employed as a consultant, it eventually leads to more business opportunities.
It inspires your coworkers and peers to become subject matter experts in their own right by leading by example. Being a subject matter expert offers opportunities to work with other subject matter experts in your company on leading edge projects.
It builds your personal brand. By writing papers and presenting at conferences you become known in the industry from the work you have accomplished and shared.
It gives you a chance to network, meet and collaborate with new people with like interests in the industry. It’s a snowball effect. I can’t even begin to count now many new people from around the world I have met since starting to publish and attend conferences.
It builds self confidence. Everyone at one time or another has had a fear of public speaking. By presenting your work in an audience of your peers, that fear of public speaking begins to dissipate.
Personal pride. Just like a “runner’s high”, you get a dopamine hit every time you see your work published or you present. There is no greater feeling, after spending an enormous amount of time writing your paper, making your slides perfect, continually practicing your presentation, to anyone who will listen, then finally delivering to an audience. It becomes addictive so you will want to continually publish and present your work.
It leaves a lasting legacy of part of your life’s work behind. Let’s face it, our time is limited on this earth. By publishing your work, it inspires future generations in their research, just like past generations of authors have inspired many of today’s authors, including myself.
You don’t have to start big. A personal blog, web site is a good place to begin. Trade journals, and online magazines in your industry are always looking for quality content that is relevant to their readers.
Formal societies, like IEEE, is a more recognized venue and is peer reviewed. Submitting a paper to industry conferences is another way and offers the opportunity to present your work. And finally, the ultimate, is publishing a book.
Once your work is published, then you need to self promote what you have done. Use social media like LinkedIn, Facebook, Twitter or any other platform. You eventually will build a following, who will react and share your posts and soon become an industry influencer.
Finally, I’d like to leave you with this final thought. Being Canadian, our national pastime is Hockey. We usually have a hockey analogy for almost anything. Everyone who follows hockey knows Wayne Gretzky, the greatest hockey player of all time. One of his famous quotes was, “You always miss 100% of the shots you don’t take.” And likewise, if you do not take the shot of writing a paper, book or an article, you cannot become a subject matter expert or industry influencer.
Go for it!
CannonballHuray Model Demystified
Recently on the SIList there was great debate on whether or not my Cannonball model can be used to determine surface ratio and radius of sphere parameters needed for Huray roughness model from data sheets alone.
The author of this paper, “Conductor surface roughness modeling: From “snowballs” to “cannonballs”, [1] argues it is impossible to accurately model transmission lines from data sheets alone and seems to imply that because I had measured data in advance that I had magically “adjusted” R_{z} parameter to get such good correlation to measurements in my EDICon 2016 paper, “Practical Model of Conductor Surface Roughness Using Cubic Closepacking of Equal Spheres” [5].
Unfortunately his paper has created more confusion than clarity. To be clear, there is only ONE “Cannonball” model, and it is based on the cubic close packing of equal spheres, also known as facecentered cubic (FCC) packing.
The author of [1] also advocates using a material model identification methodology, similar to what I like to call the Design Feedback Method, shown in Figure 1. The author believes it is the only “accurate” way of determining printed circuit board (PCB) material properties for modeling.
Figure 1 Design Feed Back Method flow chart
This involves designing, building and measuring a test coupon with the intended PCB trace geometry to be used in final design. After modeling and tuning various parameters to best fit measured data, material parameters are extracted and then used in channel modeling software to design the final product.
The problem with this approach for many small companies is: TIME, RESOURCES, and MONEY.

Time to define stackup and test structures.

Time to actually design a test coupon.

Time to procure raw material – can take weeks, depending on scarcity of core/prepreg material.

Time to fabricate the bare PCB.

Time to assemble and measure.

Time to crosssection and measure parameters.

Time to model and fit parameters to measurements.
Then there is the issue of resources, which include having the right test equipment and trained personnel to get trusted measurements.
In the end this process ultimately costs more money, and material properties are only accurate for the sample from which they were extracted for the software and roughness model used. There is no guarantee extracted parameters reflect the true material properties.
There will be variation from sample to sample built from the same fab shop and more so from different fab shops because they have a different etch line and oxide alternative process.
For example Figure 2 shows measurements from two boards of the same design. As you can see there are differences in both insertion loss and TDR plots. Which curve do we use to fit parameters for material extraction to use in simulations? How many do we have to build and test to get a statistical sample of reality? How much time will this take? And how much money will it cost, especially if several PCB stackup geometries are required?
Figure 2 Comparison of insertion loss and TDR measurements of two boards of the same design
But, as Eric Bogatin often likes to say, “Sometimes an OK answer NOW is better than a good answer late”. For many signal integrity engineers, and design consultants, like myself, have to come up with an answer sooner, rather than later for many reasons. And depending on the issue at hand, those answers may be good enough. This was the initial motivation for my research.
So where do we get these parameters? Often the only sources are from manufacturers’ data sheets alone. But in most cases, the numbers do not translate directly into parameters needed for the EDA tools.
This paper will revisit the Cannonball model as it applies to the CMP28 reference platform from Wildriver Technology [14], and as part of it I will show:

How to determine effective dielectric constant (D_{keff}) due to roughness from data sheets alone.

How to apply my simple Cannonball stack model to determine roughness parameters needed for Huray model from data sheets alone.

How to apply these parameters using Simbeor software [10].

How to pull it all together with a simple case study.
But before we get into it, it is important to give a bit of background on material properties and PCB fabrication process.
Electrodeposited Copper
Electrodeposited (ED) copper is widely used in the PCB industry due to its low cost. A finished sheet of ED foil has a matte side and drum side. The matte side is usually treated with tiny nodules and is the side bonded to the core laminate. The drum side is always smoother than the matte side. For high frequency boards, sometimes the drum side of the foil is treated instead and bonded to the core. In this case it is known as reversed treated foil (RTF).
IPCTM6502.2.17A defines the procedure for determining the roughness or profile of metallic foils used on PCBs. Profilometers are often used to quantify the roughness tooth profile of electrodeposited copper.
Nodule treated tooth profiles are typically reported in terms of 10point mean roughness (R_{z}). Some manufacturers may also report root mean square (RMS) roughness (R_{q}). For standard foil this is the matte side. For RTF it is the drum side. Most often the untreated, or prepreg side, reports average roughness (R_{a}) in manufacturers’ data sheets.
With the realization of roughness having a detrimental effect on insertion loss (IL), copper suppliers began providing very low profile (VLP) and ultralow profile (ULP) class of foils. VLP foils have treated roughness profiles less than 4 μm while ULP foils are less than 2 μm. Other names for ULP class are HVLP or eVLP, depending on the foil manufacturer.
It is important to obtain the actual vendor’s copper foil data sheet used by the respective laminate supplier for accurate modeling.
Oxide/Oxide Alternative Treatment
In order to promote good adhesion of copper to the prepreg material during the PCB lamination process, the copper surface is treated with chemicals to form a thin, nonconductive film of black or brown oxide. The controlled oxidation process increases the surface area, which provides a better bond between the prepreg and the copper surface. It also passivates the copper surface to protect it from contamination.
Although oxide treatment has been used for many years, eventually the industry learned that the lack of chemical resistance resulted in pink ring, which is indicative of poor adhesion between copper and prepreg. This weakness has led to oxide alternative (OA) treatments which rely on some sort of etching process, but no oxide layer is formed.
With the push for smoother copper to reduce conductor loss, newer chemical bond enhancement treatments, working at the molecular level, were developed to maintain copper smoothness, yet still provide good bonding to the prepreg.
Since OA treatment is applied to the drum side of the foil during the PCB Fabrication process, the OA roughness numbers should be used instead of R_{a} specified in foil manufacturer’s data sheets. RTF foil is modeled differently and discussed later in the case study.
Tale of Two Data Sheets
Everyone involved in the design and manufacture of PCBs knows the most important properties of the dielectric material are the dielectric constant (D_{k}) and dissipation factor (D_{f }).
Using D_{k} / D_{f }numbers for stackup design and channel modeling from “Marketing” data sheets, like the example shown in Figure 3, will give inaccurate results. These data sheets are easily obtained when searching laminate supplier’s web sites.
Figure 3 Example of a “Marketing” data sheet easily obtained from laminate supplier’s web site. Source Isola Group.
Instead, real or “Engineering” data sheets, which are used by PCB fabricators to design stackups, should be used for PCB interconnect modeling. These data sheets define the actual thickness, resin content and glass style for different cores and prepregs. They include D_{k }/ D_{f }over a wide frequency range; usually from 100 MHz10GHz.
Figure 4 Example of an “Engineering” data sheet showing D_{k}/D_{f} for different glass styles and resin content over frequency. Source Isola Group.
Effective D_{k} Due to Roughness
Many engineers assume D_{k }published is the intrinsic property of the material. But in actual fact, it is the effective dielectric constant (D_{keff}) generated by a specific test method. When simulations are compared against measurements, there is often a discrepancy in D_{keff}, due to increased phase delay caused by surface roughness.
D_{keff} is highly dependent on the test apparatus and conditions of how it is measured. One method commonly used by many laminate suppliers is the clamped stripline resonator test method, as described by IPCTM650, 2.5.5.5, Rev C, Test Methods Manual.
The measurements are done under stripline conditions using a carefully designed resonant element pattern card made with the same dielectric material to be tested. As shown in Figure 5, the card is sandwiched between two sheets of unclad dielectric material under test. Then the whole structure is clamped between two large plates; each lined with copper foil and are grounded. They act as reference planes for the stripline.
Figure 5 Illustration of clamped stripline resonator test method, as described by IPCTM650, 2.5.5.5, Rev C, Test Methods Manual
This method assures consistency of product when used in fabricated boards. It does not guarantee the values directly correspond to design applications.
This is a key point to keep in mind, and here is why.
Since the resonant element pattern card and material under test are not physically bonded together, there are small air gaps between the various layers that affect measured results. The small air gaps result in a lower D_{keff} than what is measured in real applications using foil with different roughness bonded to the same core laminate. This is the primary reason for phase delay discrepancy between simulation and measurements.
If D_{k} and R_{z} roughness parameters from the manufacturers’ data sheets are known, then the effective D_{k} due to roughness (D_{keff}_{_rough}) of the fabricated core laminate can be estimated by [2]:
Equation 1
where: H_{smooth} is the thickness of dielectric from data sheet; R_{z} is 10point mean roughness from data sheet; D_{k} is dielectric constant from data sheet
Most EDA tools include a wideband causal dielectric model. To use it, you must enter D_{k }and D_{f} at a particular frequency. I found it is usually best to use the values near the Nyquist frequency of the baud rate.
Modeling Copper Roughness
“All models are wrong but some are useful”– a famous quote by George E. P. Box, who was a British statistician in the mid20^{th} century. The same can be said when using various roughness models.
For example many roughness models require RMS roughness numbers, but often R_{z} is the only number available in data sheets, and vice versa. If R_{z} is defined as the sum of the average of the five highest peaks and the five lowest valleys of the roughness profile over a sample length, and R_{q} is the RMS value of that profile, then the roughness can be modeled as a triangular profile with a peak to valley height equal to R_{z}, as illustrated in Figure 6.
Figure 6 Triangular roughness profile model with peak to valley height equal to 10point mean roughness R_{z}.
If we define the RMS height of the triangular roughness profile is equal to ∆, then:
Equation 2
And likewise, if we assume ∆ ~ R_{q}, then:
Equation 3
Several modeling methods were developed over the years to determine a roughness correction factor (K_{SR}). When multiplicatively applied to the smooth conductor attenuation (α_{smooth}), the attenuation due to roughness (α_{rough}) can be determined by:
Equation 4
Huray Model
In recent years, the Huray model has found its way into popular EDA software due to the continually increasing need for better modeling accuracy. The model is based on a nonuniform distribution of spherical shapes resembling “snowballs” and stacked together forming a pyramidal geometry.
By applying electromagnetic wave analysis, the superposition of the sphere losses can be used to determine the total loss of the structure. Since the losses are proportional to the surface area of the roughness profile, an accurate estimation of a roughness correction factor (K_{SRH}) can be analytically solved by [4]:
Equation 5
Although it has been proven to be a pretty accurate model, it relied on analysis of scanning electron microscopy (SEM) pictures of the treated surface and tuning of parameters for best fit to measured data. This is not a practical solution if all you have is roughness parameters from manufacturers’ data sheets.
CannonballHuray Model
Building upon the work already done by Huray, and using the Cannonball stack principle, the sphere radius and flat base area parameters are easily estimated solely from roughness parameters published in manufacturers’ data sheets.
As illustrated in Figure 7 there are three rows of equal sized spheres stacked on a square tile base. Nine spheres are on the first row, four spheres in the middle row, and one sphere on top. This stacking arrangement is known as closepacking of equal spheres, but more commonly known as the “Cannonball” stack due to the method used by sailors to stack actual cannonballs aboard ships.
Figure 7 CannonballHuray physical model. The height of the stack is the RMS height of the peak to valley profile equal to R_{z} from data sheets.
If we could peer into the stack and imagine a pyramid lattice structure connecting to the center of all the spheres, then the total height is equal the height of two pyramids plus the diameter of one sphere.
Given the height of the Cannonball stack (∆) is equal to the RMS value of the peak to valley roughness profile; then from method described in my earlier papers, determining the sphere radius (r ), from R_{z} found in data sheets, can be further simplified and approximated as [13]:
and base area (A_{flat}) as:
Equation 7
Because the model assumes the ratio of A_{matte}/A_{flat} = 1, and there are only 14 spheres, the original CannonballHuray model can be further simplified to:
Equation 8
where: K_{CH} (f) = CannonballHuray roughness correction factor, as a function of frequency; δ (f) = skindepth, as a function of frequency in meters; r = the radius of spheres in meters (Equation 6)
CMP28 Case Study Revisited
To test the accuracy of the model, stackup details and measured data from a CMP28 test platform, design kit, courtesy of Wildriver Technology, shown in Figure 8, was used for model validation. The PCB stackup is shown in Figure 9
Two different sets of Sparameter (s2p) files from a 2 inch and 8 inch singleended (SE) stripline traces shown were used in this study. The original set of measurements, from my previous papers, and a second set provided as part of CMP28 design kit from another PCB were used for model correlation.
The 6 inch transmission line segment Sparameter data was deembedded using Ataitec ISD software [8] for both sets of data.
Figure 8 Photo of a portion of CMP28 test platform courtesy of Wildriver Technology used for model validation.
Figure 9 CMP28 PCB Stackup
The PCB was fabricated with Isola FR408HR 3313 core and prepreg, with 1 oz. RTF. D_{k} and D_{f} at 10GHz were obtained from the FR408HR data sheet found on their web site and shown in Figure 10 & Figure 11.
Figure 10 Isola FR408HR data sheet used for core dielectric properties.
Figure 11 Isola FR408HR data sheet used for prepreg dielectric properties.
The foil used on FR408HR core laminates is MLS, Grade 3, controlled elongation RTF from Oakmatsui. Roughness Rz parameters for drum and matte sides are 120μin (3.048 μm) and 225μin (5.715μm) respectively for 1 oz. copper foil.
Figure 12 MLS RTF foil data sheet used on FR408HR laminate.
An oxide or oxide alternative (OA) treatment is usually applied to the copper surfaces prior to final PCB lamination. When it is applied to the matte side of RTF, it tends to smoothen the macroroughness slightly. At the same time, it creates a surface full of microvoids which follows the underlying rough profile and allows the resin to fill in the cavities, providing a good anchor.
MultiBond MP from Macdermid Enthone is an example of an oxide alternative microetch treatment commonly used in the industry. Typically 50 μin (1.27μm) of copper is removed when the treatment is completed, depending on the board shop’s process control, as per Figure 13.
In a subsequent paper by J.A. Marshall, presented at IPC APEX 2015 titled, “Measuring Copper Surface Roughness for High Speed Applications” [11], there is data supporting the hypothesis that RTF roughness gets smoother after OA application.
Figure 13 Macdermid Enthone MultiBond MP data sheet reference from their web site.
Table 1 summarizes the PCB design parameters, dielectric material properties and copper roughness parameters obtained from respective manufactures’ data sheets.
Table 1 CMP28 Test Board and Data Sheet Parameters
Parameter  FR408HR/RTF 
Dk Core/Prepreg  3.65/3.59 @10GHz 
Df Core/Prepreg  0.0094/0.0095 @ 10GHz 
R_{z} Drum side  3.048 μm 
R_{z} Matte side before Microetch  5.715 μm 
R_{z }Matte side after Microetch  4.445 μm 
Trace Thickness, t  1.25 mil (31.7μm ) 
Trace Etch Factor  60 deg 
Trace Width, w  11 mils (279.20 μm) 
Core thickness, H1  12 mils (304.60 μm) 
Prepreg thickness, H2  10.6 mils (269.00 μm) 
GMS trace length  6 in (15.23 cm) 
From Table 1 and by applying Equation 1, D_{keff} of core and prepreg due to roughness were determined to be:
Next, the Cannonball model’s sphere radiuses, for matte and drum side of the foil, were determined to be:
Because most EDA tools only allow a single value for the radius parameter, the average radius (r_{avg}) was determined to be:
Equation 9
Simbeor electromagnetic software from Simberian Inc. [10] was used for modeling the transmission lines. It includes the latest and greatest dielectric and conductor roughness models, including the HurayBracken causal metal model.
Solution explorer pane and solution tree, as shown in Figure 14, allows you to edit and view solution data as a tree structure. All parameters from Table 1 were entered here.
Simbeor requires two parameters; roughness factor (RF1) and sphere radius (SR1). Because the Cannonball model always has N=14 spheres and base area (A_{flat}) is always 36r^{2}, r^{2} cancels out and RF1 can be simplified to:
Equation 10
Sphere radius (SR1) is r_{avg} = 0.225 as calculated from Equation 9.
Figure 14 Simbeor Solution Explorer Pane and Solution Tree
The wideband causal dielectric model option was used to model dielectric properties over frequency. Effective D_{k} due to roughness for core and prepreg, calculated above, were substituted instead of data sheet values. Standard copper resistivity of 1.724e8 ohmmeter was used.
After the transmission lines were modeled and simulated, the Sparameter results were saved in touchstone format. Keysight ADS [5] was used for further simulation analysis and comparison.
D_{keff} can be derived from phase delay. This is also known as time delay (TD) and is often used as a metric for simulation correlation accuracy for phase. TD, as a function of frequency, in seconds, is calculated from the unwrapped measured transmission phase angle, and is given by:
Equation 11
and:
D_{keff }, as a function of frequency, is then given by:
Equation 12
where:c = speed of light (m/s); Length = length of conductor (m)
Figure 15 compares the simulated results vs measurement of a 6inch, deembedded stripline trace. The red plots are measured from CMP28 design kit data. The data was bandwidth limited to 35 GHz. The blue plots are the original measured data used in my previous paper [5]. The green plots are modeled with data sheet values only with oxide alternative treatment applied. SE IL is shown on the left and D_{keff} is shown on the right. As can be seen, there is excellent correlation.
Figure 15 Measured vs simulated insertion loss (left) and D_{keff }(right) with OA etch treatment applied.
The author of [1] suggests is that because I had the measured data, R_{z} was “adjusted” to show excellent results. What he is implying is my “adjusting” the roughness, due to the oxide treatment, was the reason for such good results, in spite of the fact Macdermid’s OA data sheet reports typical 50 μin of copper removal after treatment and data from [11] showing RTF gets slightly smoother after OA treatment.
So ok, let’s see what happens if I didn’t adjust the roughness due to OA treatment. Instead of using R_{z }matte side after microetch (4.445 μm ) roughness, we will use 5.715 μm from data sheet.
This will affect D_{keff }of prepreg and average sphere radius r_{avg}_{ , }so we will recalculate them:
And average radius is:
Figure 16 compares the simulated results vs measurement. The red plots are measured from CMP28 design kit data. The blue plots are the original measured data used in my previous paper [5]. The green plots are modeled with data sheet values only without oxide alternative treatment applied. SE IL is shown on the left and D_{keff} is shown on the right.
As can be seen, there is still excellent correlation with insertion loss even though OA was not considered. As expected using the rougher number would increase effective Dk. But in the end the TDR plots in Figure 17shows impedance change is negligible.
Figure 16 Measured vs simulated insertion loss (left) and phase delay (right) without OA etch treatment applied.
Figure 17 Measured vs simulated TDR plots with OA etch treatment (left) and without (right).
Summary and Conclusions
By using CannonballHuray model, with copper foil roughness and dielectric material properties obtained solely from respective manufacturers’ data sheets, practical PCB interconnect modeling for highspeed design is now achievable using commercial fieldsolving software employing Huray model.
Measured results from two different boards confirmed there are variations due to manufacturing that would affect material model extraction method accuracy.
When oxide alternative treatment was not considered, even though the matte side roughness of RTF gets smoothened during the PCB fabrication process, the simulated results still show excellent correlation to the original measured data from previous paper [5].
References
[1] Y. Slepnev, “Conductor surface roughness modeling: From “snowballs” to “cannonballs”.
[2] B. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”. DesignCon 2017, Proceedings, Santa Clara, CA, 2017
[3] L. Simonovich, “Practical method for modeling conductor roughness using cubic closepacking of equal spheres,” 2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), Ottawa, ON, 2016, pp. 917920. doi: 10.1109/ISEMC.2016.7571773.
[4] Huray, P. G. (2009) “The Foundations of Signal Integrity”, John Wiley & Sons, Inc., Hoboken, NJ, USA., 2009
[5] L.Simonovich, “Practical Model of Conductor Surface Roughness Using Cubic Closepacking of Equal Spheres”, EDICon 2016, Boston, MA
[6] Keysight Advanced Design System (ADS) [computer software], (Version 2017). URL: http://www.keysight.com/en/pc1297113/advanceddesignsystemads?cc=US&lc=eng.
[7] Isola Group S.a.r.l., 3100 West Ray Road, Suite 301, Chandler, AZ 85226. URL: http://www.isolagroup.com/
[8] Ataitec, URL: http://ataitec.com/products/isd/
[9] V. DmitrievZdorov, B. Simonovich, I. Kochikov, “A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics”, DesignCon 2018 Proceedings, Santa Clara, CA, 2018
[10] Simberian Inc., 2629 Townsgate Rd., Suite 235, Westlake Village, CA 91361, USA, URL: http://www.simberian.com/
[11] John A. Marshall, “Measuring Copper Surface Roughness for High Speed Applications”, IPC APEX Expo 2015.
[12] Macdermid Enthone, Multibond MP, Inner Layer Oxide Alternative Bonding. URL: https://electronics.macdermidenthone.com/productsandapplications/printedcircuitboard/surfacetreatments/innerlayerbonding
[13] B. Simonovich, “PCB Interconnect Modeling Demystified”. DesignCon 2019, Proceedings, Santa Clara, CA, 2019.
[14] Wild River Technology LLC 8311 SW Charlotte Drive Beaverton, OR 97007. URL: https://wildrivertech.com/
Perils of Crossing Split Planes
I recently came across this YouTube video spoof of Chuck Norris doing the spits across two aircraft wings above the clouds and it occurred to me that it was a perfect metaphor for what happens when a digital signal, propagating along a microstrip trace, crosses a split plane on a printed circuit board (PCB). If Chuck Norris and his merry band of paratroopers standing on his head were the signal, then at the split of two reference planes, we would see an impedance mismatch which manifests itself as a positive peak in the time domain reflection (TDR) plot for the duration of the discontinuity.
When discussing signal integrity (SI) issues there is always a great debate when signals on one layer of PCB crossing over split or a slot in the reference planes. On the one hand, some argue that this should never be done because of the increased risk in crosstalk and possible failure to pass electromagnetic compatibility (EMC) compliance. On the other hand, others stressed that if the width of the gap and power/ground layers in the stackup were engineered carefully, this may not be as big of an issue. So who’s right?
Well, like all things involving signal integrity, the answer is, “it depends”. And the best way to answer “it depends” is to put in the numbers.
When I decided to investigate this, I thought to myself I would just set up a couple of simple simulations to explore the issues. Of course, once you get into it, you find other scenarios to check out, then another, and before long you have amassed a lot of data. So I decided to capture it all in a white paper.
Here is a brief summary of the results.
To see just how much of an issue this is I set up a topology using Keysight ADS as shown in Figure 1. Two transmission line segments before and after the gap section (TL17, TL18) were modeled with internal 2D field solver. The gap section (SNP139) was modeled and simulated with Momentum 3D planar field solver in order to properly capture the electromagnetic effects as the signals cross the gaps. The Sparameter results were saved as touchstone format and brought back into the ADS schematic.
A 50 mil gap was chosen for worst case and a 5 mil gap was chosen for best case. As expected, when the topology was driven differentially from Port 1, the 50 mil gap results, shown in red, had a higher impedance discontinuity compared to the 5 mil gap, shown in blue.
Figure1 Keysight ADS general schematic (top) used to model and simulate a microstrip crossing a split plane. Red and blue plots (bottom) are differential impedance comparison of 50 mil vs 5 mil gaps respectively.
Figure 2 shows simulated results of incident/transmitted signals; nearend/farend crosstalk (NEXT/FEXT) when the gap between the split planes was reduced from 50 mils (blue plots) down to 5 mils, and the thickness of dielectric from layer2 to layer 3 was reduced from 45 mils to 2 mils (red plots). Compared to the scenario with no gap (black plots) there was no appreciable increase in crosstalk.
Figure 2 Comparison of SE Incident/Transmitted voltage, NEXT/FEXT for 50 mil gap (blue) and thick dielectric under the gap vs 5 mil gap and thin dielectric under the gap (red). As expected the closer proximity of reference plane under the gap results in less incident reflection and NEXT while minimizing risetime degradation in transmitted signal and FEXT.
From a signal integrity perspective, one may conclude that crossing a split plane may be ok, with certain caveats. But in terms of passing EMC, there is still risk and doubt. For instance we see that there is still some current flow along each side of the split when we reduce the thickness between Layer 2 and 3. The combination of the split plane and diverted return current along the split creates an efficient slot antenna which will radiate noise.
Since a real design may have many interdependencies affecting the final performance, it is difficult to come up with a general rule that says if you do this, and minimize that you will be ok; and because of that, I’m still on the side of staying away from crossing split planes. When you can’t, then a more detailed analysis should be done based on the actual layout and stackup of the board; or look for other alternatives that can mitigate noise radiation; like adding extra external shielding for instance.
In the end it is what I always like to say about engineering, “it’s what you don’t know you don’t know that can ruin your day”. In today’s highspeed designs we can no longer restrict our thinking in terms of signal integrity, power integrity or EMC alone. We must consider all three and become educated or at least aware of the other disciplines. Had we only been concerned about signal integrity, without being aware of EMC we would have probably made the wrong conclusion, and in the end the final product might well have failed EMC compliance tests.
For more detail you can down load the white paper I wrote titled, “Split Planes and What Happens When Microstrip Signals Cross Them” from my web site here.
Practical Modeling of Highspeed Channels
As Dave Dunham from Molex Corp. likes to say, “When designing highspeed serial links beyond 10 GB/s, everything matters”. In order to ensure first time success at these speeds, accurate channel modeling is a prerequisite. This is especially true for long backplane channels.
Although many EDA tools include the latest and greatest models for conductor surface roughness and wideband dielectric properties, obtaining the right parameters to feed the models is always a challenge. Often the only sources are from data sheets alone. But in most cases, the numbers do not translate directly into parameters needed for the EDA tools. So how do we get these parameters?
One way is to follow the design feedback method which involves designing, building and measuring a test coupon, then extracting the parameters through tuning simulation to measurement. Although this method is pretty practical and accurate, a significant amount of expertise and equipment is required to design, build and measure the test coupon, which takes significant amount of time and money.
But, as Eric Bogatin often likes to say, “Sometimes an OK answer NOW! is better than a good answer late.” As a highspeed signal integrity practitioner and backplane architect, I often have to come up with an answer sooner, rather than later because of the impact to time and cost to my clients. And that’s why I have been motivated over the last few years to research and develop simple methodologies to accurately determine parameters to feed into modern EDA tools.
If you went to this year`s EDICon 2017 in Boston, and attended the Highspeed Digital Symposium session, you would have heard me speak on a “Practical Modeling of Highspeed Channels Based on Data Sheet Input”, which was the title of my presentation.
For those of you who could not attend, I have made available an annotated slide deck. You can download a copy from my web site.
What you will learn:

How to use my Cannonball model to determine Huray roughness parameters from data sheet alone

How to determine effective dielectric constant due to roughness from data sheets alone

How to apply these parameters in the latest version of Polar Si9000e Field Solver

How to pull it all together using Keysight ADS software
And this is an example of simulation results compared to measurements you can expect to see:
Via Stubs Demystified
We worry about via stubs in highspeed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot (IL) of the channel. But are all via stubs bad? Well, as with most answers relating to signal integrity, “It depends.”
If one of these frequency nulls happen to line up at or near the Nyquist frequency of the bit rate (i.e. 1/2 of the bitrate), the received eye will be devastated, resulting in a high biterrorratio (BER), or even link failure.
Figure 1 shows simulation results of two backplane channels. On the left are measured SDD21 insertion loss and eye diagram of a 10 GB/s, nonreturntozero (NRZ) signal, with short through vias and long stubs ~ 270 mils. On the right, shows measured SDD21 IL and eye diagram of a channel with long through vias and shorter stubs ~ 65 mils
Because the ¼ wave resonant null occurs at a frequency ~ 4. 4 GHz, this is near the Nyquist frequency for 10 GB/s. As can be seen, the eye is totally closed for the long stub case. But when the shorter stub case is simulated, the eye is open with plenty of margin.
So how does a via stub cause ¼ wave resonance? This question can be explained with the aid of Figure 2. Starting on the left, we see a via with two sections. The through (thru) part is the top portion connecting a device pin to an inner layer trace of a printed circuit board (PCB). The stub portion is the lower portion and is an open circuit.
On the right a sinusoidal signal is injected into the pin at the top of the via and travels along the thru portion until it reaches the junction of the internal trace and stub. At that point, the signal splits. Some of it travels along the trace, and the rest continues down the stub. Once it reaches the bottom, it reflects back up. When it reaches the trace junction, it splits again with a portion traveling along the trace and the rest back to the source.
If f_{ }is the frequency of a sine wave, and the time delay (TD) through the stub portion equals a ¼ wavelength, then when it reflects at the bottom and reaches the junction again, it will be delayed by ½ a cycle and cancels most of the original signal.
Figure 2 Illustration of a ¼ wave resonance of a stub. If f = frequency where TD = ¼ wavelength, then when 2TD = ½ cycle minimum signal received.
Resonance nulls occurs at the fundamental frequency ( f_{o}) and at every odd harmonic. If you know the length of the stub (in inches) and the effective dielectric constant (Dk_{eff}), surrounding the via hole structure, the resonant frequency can be predicted by:
Equation 1
Where: f_{o} is the ¼ wave resonant frequency (GHz); c is the speed of light (~11.8 in/ns); Stub_length is inches.
You will find that Dk_{eff} is not the same as the bulk Dk published in laminate manufacturers’ data sheets. It is typically higher. A higher Dk_{eff} increases phase delay through the via resulting in a lower resonant frequency.
One reason is excess capacitance from the via pads as well as the via barrel’s proximity to the clearance hole openings (also known as antipads) in plane layers. The other is because of the anisotropic nature of the laminate material.
For the example in Figure 1, the ¼ wave resonant frequency of the long via stub is ~ 4.4 GHz. With a stub length of ~ 270 mils, this gives a Dk_{eff} of 6.16, which is considerably higher than the published bulk Dk of 3.65. When you model a via in an electromagnetic (EM) 3D field solver, it automatically accounts for the excess capacitance, but you will still need to compensate for the anisotropic nature of the dielectric.
A material is anisotropic when there are different values for parallel (xy) vs perpendicular (z) measured values for dielectric constant. Dielectric constant and loss tangent, as published in manufacturers’ data sheets, report perpendicular measured values. For FR4 fiberglass reinforced laminates, anisotropy can range from 15% 25% higher. The bad news is these numbers are not readily available from data sheets.
For differentially driven vias with plane layers evenly distributed throughout the entire stackup, Dk_{eff} can be roughly estimated by:
Equation 2
Where: Dk_{xy} is the dielectric constant adjusted for anisotropy (15%25% higher); Dk_{z} is the bulk dielectric constant from data sheets; s is viavia spacing; drillØ is drill diameter; H and W are antipad shape dimensions as shown in Figure 3 .
Figure 3 Antipad parameters for Equation 2.
The effects of via stubs can be mitigated by: using blind or buried vias; backdrilling; or by using thru vias only (i.e. from top layer to bottom layer). Practically, the shortest stub that can be achieved by backdrilling is on the order of 5 to 10 mils.
As a rule of thumb, we usually strive to have an interconnect bandwidth (BW) to be five times the Nyquist frequency of the bitrate. Since a ¼wave resonant null behaves somewhat like a notch filter, depending on the highfrequency rolloff due to Qfactor, frequencies near resonance will be attenuated. For that reason a good rule of thumb to follow is making sure the first null should occur at the 7^{th} harmonic, or higher, of the Nyquist frequency to maintain the integrity of the 5^{th} harmonic frequency component that makes up the risetime of a signal.
With this in mind, for a given baudrate (Baud) in GBd, the maximum stub length (l_{max}), in inches can be estimated by:
Equation 3
For NRZ signaling, the baudrate is equal to the bit rate. But for pulseamplitude modulation (PAM4) signaling, which has 2 symbols per bit time, the baudrate is ½ of that. Thus a 56 GB/s PAM4 signal has a baudrate of 28 GBd, and the Nyquist frequency is 14 GHz, which happens to be the same as 28 GB/s NRZ signalling.
Figure 4 presents a chart of maximum stub length vs baudrate based on Equation 3, using a Dk_{eff} = 6.16 (blue) vs 3.65 (red). It shows us the higher the baudrate, the more the stub length becomes an issue, especially past 10 GBd. We also get a feel for the sensitivity of stub length to Dk_{eff }. Even though there is ~ 70% difference in Dk_{eff}, there is only ~ 30% delta in stub lengths for the same baudrate. This means that even if we use the bulk Dk published in data sheets, we are probably not dead in the water.
If the respective stub length is greater than this, it does not mean there is a show stopper. Depending on how much longer means the eye opening at the receiver will be degraded and we lose margin. We see this by the example in Figure 1. Even though the stub lengths in the channel were almost double the value at 10 GBd from the chart, there is still plenty of eye opening.
Figure 4 Chart showing estimated maximum stub length vs baudrate with Dk_{eff} of 6.16 (red) vs 3.65 (blue) based on Equation 3
To further explore design space and test out the rule of thumb, a generic circuit model was built using Keysight ADS with the ability to vary the via stub lengths
Referring to the chart, at 28 GBd, the maximum stub length should be 12 mils, assuming a Dk_{eff} of 6.16. Figure 5 shows simulation results for NRZ signalling. As can be seen, there was a difference of only 17 mV in eye height (1.5%), and no extra jitter for 12 mil stubs compared to 5 mil stubs.
Figure 5 Eye diagrams comparison with BER at 10E12 for stub lengths of 5 mils vs 12 mils. Modeled and simulated with Keysight ADS.
But if we use the exact same channel model, and use the generic PAM4 IBIS AMI model from Keysight Technologies, we can see the results plotted in Figure 6. On the left are the eye openings with 5 mil stubs and the right with 12 mil stubs. In this case, there was an average reduction of ~7 mV (6%) in eye heights, and 0.24 ps (2%) in eye widths at BER 10E12 across all three eyes.
Figure 6 PAM4, 28 GBd (56 GB/s) eye height and width comparison at BER of 10E12 for 5 mil vs 12 mil stub lengths. Modeled and simulated with Keysight ADS.
Because PAM4 signalling has three smaller eyes, that are onethird the size of an NRZ eye for the same amplitude, it is more sensitive to channel impairments. From the above examples, we can see NRZ had only 1.5% reduction in eye height compared to 6% for PAM4. Similarly there was no increase in jitter for NRZ compared to 2% increase for PAM4 when stub lengths changed from 5 mils to 12 mils.
What this says is maintaining a BW to 5 times Nyquist rule of thumb, when estimating via stub lengths, is quite conservative for NRZ signalling. There is almost the same BW as the channel with 5 mil stub, which was the original objective. But because PAM4 is more sensitive to impairments, it shows there is less margin.
In summary then, rules of thumb and related equations are a good way to reinforce your intuitions or to give you an answer sooner rather than later. They help you know what to expect before you take any measurements or perform any simulations. But they should never be used to sign off on any highspeed design.
Because every system will have different impairments affecting BER, the only way to know how much margin you have is by modeling the via with a 3D EM field solver, based on the actual stackup and simulating the entire channel complete with crosstalk, if margins are tight. This is even more critical for data rates above 10 GBd.
So to answer the original question, “are all via stubs bad”? Well, the answer is it still depends. For NRZ signalling, there is more leeway than for PAM4. But you now have a practical way to quickly quantify the answer if you know the stub length, baudrate and delay through the via.
Obsessions with Conductor Surface Roughness – What’s the Dk Because of it?
You know you have an obsession when you are flying 6 miles over Colorado; look out your window at the beautiful scenery; and all you can think about is how the rocky mountain topology reminds you of conductor surface roughness! Well call me obsessed because that’s exactly what I thought on my way to DesignCon 2017 in Santa Clara, CA.
For those of you who know me, you know that I have been researching practical methods to model conductor surface roughness, and its effect on insertion loss (IL). I have presented several papers on the subject over the last couple of years. It’s one of my pet projects. This year, at DesignCon, I presented a paper titled, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness” .
Everyone involved in the design and manufacture of printed circuit boards (PCBs) knows one of the most important properties of the dielectric material is the relative permittivity (ε_{r}), commonly referred to as dielectric constant (D_{k}). But in reality, D_{k} is not constant at all. It varies over frequency as you will see later.
We often assume the value reported in manufacturers’ data sheets is the intrinsic property of the material. But in actual fact, it is the effective dielectric constant (D_{keff}) generated by a specific test method. When you compare simulation against measurements, you will often see a discrepancy in Dkeff and IL, due to increased phase delay caused by surface roughness. This has always bothered me. For a long time I was always looking for ways to come up with Dkeff from data sheet numbers alone. Thus the obsession and motivation for my recent research work.
Since phase delay, also known as time delay (TD), is proportional to Dkeff of the material, my theory was that the surface roughness profile decreases the effective separation between parallel plates, thereby increasing the electric field (efield) strength, resulting in additional capacitance, which accounts for an increase in effective D_{k} and TD.
The main focus of my paper was to prove the theory and to show a practical method to model Dkeff and TD due to surface roughness. By referencing Gauss’s Law for charged parallel plates, I confirmed mathematically, and through simulation, how the dielectric thickness and permittivity are interrelated to efield and capacitance. I also revealed how the 10point mean (R_{z}) roughness parameter can be applied to finally estimate effective Dkeff due to roughness. Finally I tested the method via case studies.
In his book, “Transmission Line Design Handbook”, Wadell defines D_{keff} as the ratio of the actual structure’s capacitance to the capacitance when the dielectric is replaced by air.
D_{keff} is highly dependent on the test apparatus and conditions of how it is measured. There are several methods used in the industry. One method that is commonly used by many laminate suppliers is called the clamped stripline resonator test method. It is described by IPCTM650, section 2.5.5.5, Rev C.
In short, this method rapidly tests dielectric material for permittivity and loss tangent, over an Xband frequency range of 812.4 GHz, in a production environment. It does not guarantee the values are accurate for design applications.
Here’s why:
The measurements are made under stripline conditions, using a carefully designed resonant element pattern card, made out of the same dielectric material to be tested. The card is sandwiched between two sheets of unclad dielectric material under test. The whole structure is then clamped between two large plates, lined with copper foils that are grounded.
Since the resonant element pattern card and material under test are not physically bonded together, there are small air gaps between the various layers affecting measured results. These air gaps are caused in part by:
 Removing the copper from the material under test, leaving the bare substrate, complete with the micro void imprint of the copper roughness.
 The air gap between resonant element pattern card and material under test, due to the copper thickness of the etch pattern.
 The roughness profile of the copper, on the resonant element pattern card and fixture’s grounded foil reference planes, are different than would be in practice, unless the same foil type is used.
If D_{keff} and R_{z} roughness parameters from the manufacturers’ data sheets are known, then the effective D_{k} due to roughness (D_{keff}_{_rough}) of the fabricated core laminate can now be easily estimated by:
Where: H_{smooth} is the thickness of dielectric from data sheet; R_{z} is 10point mean roughness from data sheet; and D_{keff} is the D_{k} from data sheet.
With reference to Figure 1, using D_{keff} with rough copper model, as shown on the left, is equivalent to using D_{keff}_{_rough}, with smooth copper model, as shown on the right. Therefore all you need to do is use D_{keff}_{_rough} for impedance calculations, and any other numerical simulations based on surface roughness, instead of D_{k} published in data sheets.
It is as simple as that.
Figure 1 Effective D_{k }due to roughness model. Using D_{keff} with rough copper model (left) is equivalent to using D_{keff}_{_rough }with smooth copper model (right).
For example, one case study I presented used measurements from a CMP28 modeling platform from Wild River Technology. The PCB was fabricated with FR408HR material and reverse treated foil (RTF). Keysight EEsof EDA ADS software was used for modeling and simulation. The results are shown in Figure 2.
The left graph shows results when data sheet values for core and prepreg were used. D_{keff} measured (red) was 3.761, compared to simulated D_{keff} (blue) of 3.626, at 10 GHz. This gave a delta of ~ 4%. But when the D_{keff_rough} was used for core and prepreg the delta was within 1%.
Figure 2 Measured vs simulated D_{keff} using FR408HR data sheet values for core and prepreg (left) and using D_{keff_rough} (right). Modeled and simulated with Keysight EEsof EDA ADS software.
The paper shows in more detail how Equation 1 was derived, based on Gauss’ Law. In addition, I show how IL and phase delay is also improved when D_{keff_rough} is used instead of data sheet values. You can download the paper titled, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”, and other papers on modeling conductor loss due to roughness from my web site.