Posts Tagged ‘Crosstalk’
COUPLED TRANSMISSION LINES AND CROSSTALK
Originally published Signal Integrity Journal August 9, 2022
When two coplanar parallel traces running in close proximity over the coupled length, as shown in Figure 1, they are electromagnetically coupled together.
When two complementary signals are transmitted, there is mutual electromagnetic coupling defined by the amount of mutual inductance and capacitance. This is known as differential signaling. The differential impedance (Zdiff), is the instantaneous impedance of a pair of transmission lines.
The impedance of each trace, when driven differentially, is known as the oddmode impedance (Zodd). Conversely, when each trace is driven with the same polarity, the impedance of each trace is known as the evenmode impedance (Zev).
Differential impedance is simply twice the oddmode impedance:
Equation 1
When Zodd = Zev, the traces are deemed to be uncoupled and there will be no crosstalk (XTalk). The characteristic impedance (Zo) of a single trace, in isolation, is equal to the geometric average (Zavg) of Zodd and Zev. When Zodd and Zev are not equal, there will be some level of XTalk, depending on the space between traces. In this case, Zo is approximately equal to Zav and is given as;
Equation 2
Crosstalk
There are two types of XTalk generated; NearEnd (NEXT), or backwards XTalk, and FarEnd (FEXT), or forward XTalk.
Figure 1 Illustration of NEXT and FEXT. As the aggressor signal propagates from port 3 to port 4, NearEnd XTalk appears on port 1 and FarEnd XTalk appears on port 2 after one time delay (TD) of the interconnect.
NEXT
Refer to Figure 1. Through electromagnetic coupling, NEXT voltage (Vb) is related to the coupled current through a terminating resistor (not shown) at port 1; when driven by an aggressor voltage (Va) at port 3. When port 1 is terminated, the backward crosstalk coefficient (Kb) is defined by;
Equation 3
where;
Vb = the voltage at port 1
Va = the peak voltage of the aggressor at port 3
The general signature of the NEXT waveform, for a gaussian step aggressor, is shown in Figure 2. Va is the aggressor voltage at port 3 of Figure 1. Vb is the NEXT voltage at port 1. The NEXT voltage continues to increase in response to the rising edge of the aggressor until it saturates after the aggressor’s risetime. The green waveform (VaFE) is the aggressor voltage at port 4 after one time delay (TD). The duration of Vb waveform lasts for 2TD of the coupled length.
Figure 2 NEXT voltage signature, Vb in response to a gaussian step aggressor, Va. The duration of NEXT is equal to 2TD of the coupled length. VaFE is the aggressor voltage shown after one TD. simulated with Teledyne Lecroy WavePulser 40iX software.
When TD is equal to onehalf of the linear risetime, the NEXT voltage becomes saturated. The minimum length to reach saturation is known as the saturated length (Lsat), and is given by [1]:
Equation 4
where:
Lsat = the saturation length for nearend cross talk in inches
RT = Linear risetime to reach Va in ns
c = the speed of light = 11.8 in nsec
Dkeff = The effective dielectric constant surrounding the trace.
For example, a signal with a linear RT of 0.1nsec, to reach an aggressor voltage of 1V using FR4 material, with a Dkeff of 4, the saturation length in stripline is;
Important note: In PCB stripline construction, Dkeff is the Dk of the dielectric mixture of core and prepreg. But in microstrip, without solder mask, Dkeff is the mixture of Dk of air and Dk of the substrate. It is very difficult to predict the exact Dkeff in microstrip without a field solver, but a good approximation can be obtained by [3];
Equation 5
where;
Dkeff_{MS} = effective dielectric constant surrounding the trace in microstrip
Dk = Dielectric constant of the material
H = Height of dielectric
W = trace width
t = trace thickness
For example, a signal with a linear RT of 0.1ns, to reach an aggressor voltage of 1V and Dkeff_{MS} of 2.64, the saturation length in microstrip is;
If the coupled length (Lcoupled) is less than Lsat, the NEXT voltage will peak at a value less than the saturated NEXT voltage. The actual NEXT voltage, Vb is scaled by the ratio of coupled length to saturation length and is given by [1]:
Equation 6
For example, for a coupled of length of 100 mils and saturated length of 295 mils, NEXT voltage will be (100/295) or 33.9% of the saturated NEXT voltage.
NEXT vs Coupled Length in Stripline
Figure 3 plots NEXT voltage vs coupled lengths for 100mils, 295 mils and 590 mils representing less than, equal to and greater than Lsat respectively. For a coupled stripline geometry modeled with Polar SI9000 field solver (Figure 3B), Kb is 0.065.
Each length was then simulated in Polar Si9000 and touchstone files were imported into Keysight PathWave ADS software for further analysis. The results are plotted in Figure 3A.
Figure 3 Example of NEXT voltage vs couple lengths of 100 mils, 295 mils and 590 mils in stripline, with linear rise time of 0.1ns. Modeled with Polar Si9000 and simulated with Keysight PathWave ADS.
As can be seen, using a 1V aggressor with a linear risetime of 0.1ns and a saturated length of 295 mils, the NEXT voltage is 63.2 mV, compared to full saturated NEXT voltage of 64.8 mV. With a coupled length of 100 mils, NEXT voltage saturates at 22.2 mV, for the duration of the aggressor’s risetime, compared to 22.03mV predicted by Equation 6 [1].
NEXT vs Coupled Length in Microstrip
Similarly, Figure 4 plots NEXT voltage vs coupled lengths for 100mils, 363 mils and 590 mils for Lsat respectively. For a coupled microstrip geometry modeled with Polar SI9000 field solver (Figure 3B), Kb is 0.055.
Each length was then simulated in Polar Si9000 and touchstone files were imported into Keysight PathWave ADS software for further analysis. The results are plotted in Figure 4A.
Figure 4 Example of NEXT voltage vs couple lengths of 100 mils, 363 mils and 590 mils in microstrip with linear rise time of 0.1ns. Modeled with Polar Si9000 and simulated with Keysight PathWave ADS.
As can be seen, using a 1V aggressor with a linear risetime of 0.1ns and a saturated length of 363 mils, the NEXT voltage is 54.6 mV, compared to full saturated NEXT voltage of 54.9 mV. With a coupled length of 100 mils, NEXT voltage saturates at 15.8 mV for the duration of the aggressor’s risetime, compared to 15.1mV predicted by Equation 6.
The magnitude of the NEXT voltage is a function of the coupled spacing between the two traces. As the two traces are brought closer together, the mutual capacitance and inductance increases and thus the NEXT voltage, Vb, will increase as defined by [1];
Equation 7
where;
Vb = NEXT voltage on victim
Kb = Backward crosstalk (NEXT) coefficient
Va = Aggressor voltage
Cm = Mutual capacitance per unit length
Lm = Mutual inductance per unit length
Co = Trace capacitance per unit length
Lo = Trace inductance per unit length
Unfortunately, the only practical way to calculate Kb is to use a 2D field solver to get the inductive and capacitance matrix elements from a field solver.
Alternatively, if only the odd and even mode impedances are known, then Kb is given as [2];
Equation 8
where;
Zterm = Victim input termination impedance, normally the characteristic impedance (Zo) of a single trace.
When Zterm is open circuit, Kb’ is given as [2];
Equation 9
FEXT:
FEXT voltage is correlated to the coupled current through a terminating resistor (not shown) at port 2 of Figure 1. The forward crosstalk coefficient, Kf, is equal to the ratio of FEXT voltage to aggressor voltage at the far end, defined as;
Equation 10
where;
Vf = the far end crosstalk voltage
VaFE = the peak voltage of the aggressor at farend
The general signature of the FEXT waveform, for a gaussian step aggressor, is shown in Figure 5. V_{f} is the forward crosstalk voltage at port 2 of Figure 1. VaFE is the aggressor voltage appearing at the far end port 4. FEXT voltage differs from NEXT in that it only appears as a pulse at TD after the signal is launched. In this example, the negative going FEXT pulse is the derivative of the aggressor’s rising edge at TD. The opposite is true on the falling edge of an aggressor.
Figure 5 FEXT voltage signature, Vf, is forward crosstalk (FEXT) voltage in response to a gaussian step aggressor voltage, VaFE. Simulated with Teledyne Lecroy WavePulser 40iX software.
Unlike the NEXT voltage, the peak value of FEXT voltage scales with the coupled length. It peaks when its amplitude grows to a level comparable to the voltage at 50% of the aggressor’s risetime at TD as shown in Figure 6. In this example, the coupled lengths are: 2, 4, 6, 8 and 10 inches respectively.
As the wave propagates along the transmission line, the RT degrades due to the dielectric dispersive loss. In the same way the aggressor waveform couples FEXT voltage onto the victim, FEXT voltage also couples noise back onto the aggressor affecting the risetime as shown. Due to superposition, the aggressor waveform shown at each TD is the sum of the FEXT voltage and the original transmitted waveform that would have appeared at TD with no coupling.
Figure 6 Microstrip FEXT voltage increase vs TD for coupled lengths of 2, 4, 6, 8 and 10 inches respectively. Simulated with Teledyne Lecroy WavePulser 40iX software.
If the risetime at TD is known, the FEXT voltage, Vf can be predicted by [1];
Equation 11
where;
Vf = FEXT voltage on victim
VaFE = Farend aggressor voltage
Kf = FEXT coefficient
Cm = Mutual capacitance per unit length
Lm = Mutual inductance per unit length
Co = Trace capacitance per unit
Lo = Trace inductance per unit length
RT = Risetime of aggressor signal at TD in sec
c = Speed of light
Dkeff = Effective dielectric constant surrounding the trace
Len = Length of trace
Although the inductive and capacitive matrix elements can be obtained using a 2D field solver, the risetime is more difficult to predict because of risetime degradation, as well as impedance variations along the line causing reflections. But worst of all, as seen in Figure 6, is the forward crosstalk coupling affecting the aggressor’s risetime makes it next to impossible to predict.
The only practical way to calculate Kf is to model and simulate the topology using a circuit simulator that supports coupled transmission lines. The circuit simulator should have an integrated 2D field solver built in to allow automatic generation of a coupled transmission line model from the crosssectional information.
Since the dielectric surrounding the traces in stripline is more homogeneous, than it is in microstrip, the best way to significantly reduce, or eliminate FEXT, is to route the traces in stripline geometry. Depending on the difference in Dk between core and prepreg used in the stackup, there is always a probability there will be some small amount of FEXT generated. The best way to mitigate this is to choose cores and prepregs to have similar values of Dk when designing the stackup.
References:
[1] E. Bogatin, “Signal Integrity Simplified”, 2^{nd} edition, Prentice Hall PTR, 2010
[2] B. Young, “Digital Signal Integrity”, Upper Saddle River, NJ: Prentice Hall, 2001
[3] E. O. Hammerstad, “Equations for Microstrip Circuit Design,” 1975 5th European Microwave Conference, 1975, pp. 268272, doi: 10.1109/EUMA.1975.332206.
[4] E. Bogatin, B. Simonovich, “Dramatic Noise Reduction using Guard Traces with Optimized Shorting Vias”, DesignCon 2013, Santa Clara, CA, USA
Are Guard Traces Worth It?
Originally published in, The PCB Design Magazine, April 2013 issue.
By definition, a guard trace is a trace routed coplanar between an aggressor line and a victim line. There has always been an argument on whether to use guard traces in highspeed digital and mixed signal applications to reduce the noise coupled from an aggressor transmission line to a victim transmission line.
On one side of the debate, the argument is that the guard trace should be shorted to ground at regular intervals along its length using stitching vias spaced at 1/10th of a wavelength of the highest frequency component of the aggressor’s signal. By doing so, it is believed the guard trace will act as a shield between the aggressor and victim traces.
On the other side, merely separating the victim trace to at least three times the line width from the aggressor is good enough. The reasoning here is that crosstalk falls off rapidly with increased spacing anyways, and by adding a guard trace, you will already have at least three times the trace separation to fit it in.
In our DesignCon2013 paper titled, “Dramatic Noise Reduction using Guard Traces with Optimized Shorting Vias”, I coauthored along with Eric Bogatin, we showed that sometimes guard traces were effective, and sometime they were not; depending on how the guard trace was terminated. By correct management of the ends of the guard trace, we demonstrated it can reduce coupled noise on a victim line by an order of magnitude over not having the guard trace present. But if the guard trace was not optimized, the noise on the victim line can also be larger with the guard trace, than without.
Analysis Using Circuit Models
We started out the investigation by building circuit models for the topologies studied. Agilent’s EEsof EDS ADS software was used exclusively to model and simulate both stripline and microstrip configurations. The generic circuit model, with a guard trace, is shown in the top half of Figure 1. The circuit model, without a guard trace, is shown in the bottom half.
For the analysis, we used lossless transmission line models. The guard trace length was exactly matched to the coupled length. The ground stitching and the endtermination resistors, on the guard trace, could be deactivated, and/or shorted, as required. The linewidth space geometry was set at 555 mils, and the spacing for the nonguarded topologies was set to three times the line width.
Figure 1 ADS schematic for generic topologies with a guard trace (top) and without (bottom). The transmission line were segmented and parameterized to easily change the lengths as required. The ground stitching and the endtermination resistors, shown in top schematic, can be deactivated and/or shorted as required.
Figure 2 is a summary of results when a guard trace was terminated in the characteristic impedance, left open, or shorted to ground at each end. The red waveforms are the results for topologies without a guard trace, and the blue waveforms are with a guard trace.
Depending on the nature of the termination, the reinfected noise on the guard trace can add or subtract to the directly coupled noise on the victim line. This often makes the net noise on the victim line worse than without a guard trace.
Unlike a simple twoline coupled model, where the near end crosstalk (NEXT) and far end crosstalk (FEXT) can be easily predicted from the RLGC matrix elements, trying to predict the same for a threeline coupled model is more difficult. Manually keeping track of all the noise induced on the guard trace, and its reinfection onto the victim line, is extremely tedious. First you must identify the directly coupled reinfected backward and forward noise on the victim line from the voltage on the guard trace. Then the problem is keeping track of the multiple reflections of the noise on the guard trace. Because of this, the only real way to analyse the effect is through circuit modeling and simulation.
In microstrip topologies, as you can see, there is little to no benefit to adding a guard trace; regardless of how the ends are terminated. This is because microstrip topologies are inherently prone to far end crosstalk. Therefore any far end noise, coupled onto the guard trace, will subsequently reinfect the victim with additional far end noise; as seen by the additional ringing superimposed on the blue waveform.
In stripline topologies, without a guard trace, there is no farend cross talk generated. But when a guard trace is added, and depending on how the ends are terminated, any near end coupled noise on the guard trace can reinfect the victim. It is only when the ends are shorted to ground we see such a dramatic reduction of both near and far end noise.
Figure 2 Summary of simulation results when the ends of the guard trace was terminated, left open or shorted to ground for microstrip and stripline geometries.
Distributed Shorting Vias
When practically implementing a guard trace, to act as a shield, a rough rule of thumb suggests the spacing of shorting vias should be at least 1/10 the wavelength of the highest frequency content of the signal. For a risetime of 100 psec, the stitching via spacing, to meet l/10, is 0.18 inches; or 9 stitching vias over 1.5 inches.
Figure 3 summarizes the results when a guard trace was stitched to ground at multiple wavelengths; compared to the case of no guard. As you can see, in the case of microstrip, when the guard trace is shorted with fewer than 9 vias, there is still considerable ringing noise on the guard trace which can reinfect the victim line. But in the case of stripline, having two shorting vias at each end, or any number up to 9 shorting vias has the same result. This suggests there is no need for multiple shorting vias, other than at the end of the guard trace; as long as the guard trace is the same length as the coupled length. This dramatically simplifies the use of guard traces in stripline.
Figure 3 Summary of simulation results with guard trace stitched for microstrip and stripline geometries.
Practical Design Considerations
Up until now we have modeled and simulated ideal cases of shorting the guard traces to ground. But in reality, there are additional practical design considerations to consider. First is via size, and the impact it has on the line to line spacing. Next is the finite via inductance; since its impedance will prevent complete suppression of the noise on the guard trace. And finally, the extension of the guard trace compared to the coupled length.
Because through hole manufacturing design rules limit the smallest via and capture pads, the smallest mechanical drill size most PCB vendors will spec is 8 mils. By the time you factor in the minimum pad diameter and pad to copper spacing, the minimum space between the aggressor and victim lines would have to be at least 28 mils, as shown in Figure 4; just to fit a guard trace with grounding vias down its length.
At this point, you have to ask yourself if it is even worth it; especially for microstrip topologies. If the two signal lines were to be increased to 28 mils, the reduction in cross talk from just the added separation would likely be more significant than adding the shorted guard trace.
Figure 4 Minimum track to track spacing to fit an 8 mil drilled via and pad in throughhole technology.
Fortunately, the circuit analysis has shown there is little benefit to adding a guard trace to microstrip topologies, even if it was ground stitched appropriately. But to gain a dramatic reduction in cross talk in stripline all that is required is to short the guard trace at each end, and ensure the guard trace is exactly the same length as the coupled length. This means the minimum space to fit a via and guard trace can remain at three times the line width; as long as the guard trace is extended slightly, as shown in Figure 5(a). Alternatively, the guard trace can be made equal to the coupled length, as illustrated in Figure 5(b).
Agilent’s ADS Momentum planar 3D field solver was used to explore and quantify the implications vias and guard trace lengths have on noise reinfection. Figure 5 details a portion of the 3D model on the left end of the respective topologies. The right hand sides are identical. The reference planes are not shown for clarity.
Figure 5 Two examples of adding a grounded guard trace with minimum spacing of 3 x line width. Figure (a): guard trace is extended past the coupled length (A) by dimension B on both sides in order to satisfy minimum 5 mil padtrack spacing requirements. Figure (b): guard trace is equal to coupled length by separating the traces at each ends. Modeled in Agilent Momentum 3D field solver. Reference planes are not shown for clarity.
After simulation, the Sparameter data was saved in Touchstone format and brought into ADS for transient simulation analysis and comparison. Figure 6 shows the results. The plot on the left used 100 psec risetime for the step edge, while the plot on the right used 50 psec. Both plots are consistent with the dramatic noise reduction observed in Figure 2, except here we see some added noise ripple after about 0.8 nsec.
At 100 psec risetime, there is effectively no difference in near end noise signature for either (a) or (b) topology. But when the risetime was reduced to 50 psec, the noise ripple is more pronounced. The blue waveform shows that even when dimension B is 0 mils, there is still a small amount of noise due to the inductive length of the vias to the reference plane. The red waveform shows that adding just 12 mils to the guard trace length, at each end, the ripple magnitude is almost doubled.
It is a wellknown fact that technology advancements over time results in faster and faster rise times. If you have engineered your design on the technology of the day, any future substitution of parts, with faster rise time, may cause your product to fail, or worse be intermittent.
Figure 6 Momentum transient simulation results comparing near end crosstalk at Port 1 when aggressor voltage was applied to Port 3. The red and blue waveforms are with a guard trace. The green waveform is with no guard and 15 mils separation. Aggressor voltage = 1V, 100 psec risetime (left) and 50 psec risetime(right)..
To explore this phenomenon, the guard trace was varied by 50 and 100 mils at each end, as illustrated in Figure 7. Here we can see that as the guard trace gets longer at each end, the noise ripple grows in magnitude quite rapidly. It is remarkable to note that when the guard trace is just 100 mils longer, at each end, the peakpeak amplitude of the noise just about equals the peak magnitude of the no guard case.
Figure 7 Momentum transient simulation results with guard trace extended. B = 12 mils (red), B = 50 mils (blue) and B = 100 mils (magenta) compared to no guard (green). Aggressor voltage = 1V, 100 psec risetime. Dimensions in mils.
When the guard trace was removed, and the space was increased to five times the line width, the near end crosstalk was reduced in magnitude and was approximately equal to the guard trace scenario, as seen in Figure 8. Furthermore, because there is no guard trace, there is no additional noise ripple.
Figure 8 Momentum transient simulation results comparing near end crosstalk at Port 1 when aggressor voltage was applied to Port 3. Aggressor voltage = 1V, 100 psec risetime.
So getting back to the original question, “Are guard traces worth it?” You be the judge. Using a guard trace, shorted at each end, can be effective, if you need the isolation. But it does have caveats. If you decide to go down this path, it is imperative for you to model and simulate your topology, preferably with a 3D field solver, before signing off on the design.
Reference

Eric Bogatin, Bert Simonovich,“Dramatic Noise Reduction using Guard Traces with Optimized Shorting Vias”, DesignCon2013, Santa Clara, CA, USA, Jan 2831, 2013.
Noncontact Interconnect: When Crosstalk Is Your Friend
Originally published in, The PCB Design Magazine, November 2012 issue.
In normal PCB designs, crosstalk is usually an unwanted effect, due to electromagnetic coupling, of two or more traces routed in close proximity to one another. We usually consider it to be our enemy, in any highspeed design, and go to great lengths to avoid it. So how, you may ask, can crosstalk ever be your friend?
To answer that question, I would like to start out by taking you back to the fall of 1994. This was the era of wide parallel busses running up to 33 MHz across backplanes. Highspeed serial, pointpoint interfaces, and serdes technology, as we know and love today, was just a twinkle in some bright young engineer’s eye.
Nortel, a.k.a. Northern Telecom at the time, was looking to replace the computing module shelf of the DMS Supernode platform because it was projected to run out of steam a few years later. In order to address the issue, the system architects decided that a scalable, multiprocessing, shared memory, computing architecture was needed to replace it.
My job was to develop a concept to package all these cards in a shelf, and then design a backplane to interconnect everything. It quickly became evident that a single shared bus could not support the bandwidth required for multiprocessing. Nor could multiple parallel buses solve the problem, because of the lack of highdensity backplane connector technology needed for all the I/O. Even if we had a suitable connector, and it could magically fit within the confines of the card slot, then the layer count of the backplane would have grown exponentially.
No, something else was needed. Fortunately, Bell Northern Research (BNR), the R&D lab of Nortel where I was working at the time, had an advanced technology group, that liked to play in the sand. I remember going to a meeting one day to see some presentations on some of the neat technology they were playing with.
One presentation they gave, was of a unique noncontact interconnect technology. I immediately saw the practical application that technology offered for our architecture, and it instantly became my friend. It allowed us to eventually invent a patented, proprietary point to multipoint interconnect solution, running at 1GB/s per pair [1].
The noncontact technology actually relied on controlled electromagnetic coupling, or simply crosstalk. See Figure 1. In this simple highlevel block diagram, each card on the shelf would transmit their data differentially across the backplane. As the differential pairs traversed through the connector fields of the card slots, the transmit signal was edgecoupled to an adjacent small trace, about three quarters of an inch long, connected to the respective receiver pin. After the last card slot, the transmit differential pairs switched layers where they returned back to the originating card and were terminated.
The beauty of this architecture was that each card only needed one set of transmitters to broadcast its data to all the other cards. Since each card had enough receivers to listen to the other cards, the point to multipoint interconnect achieved the equivalent of a multipoint to multipoint architecture; but without the overhead of additional pins and PCB layers. Furthermore, an effective line rate of 1GB/s was achieved using simple, inexpensive 2mm connectors; the same ones chosen for compact PCI standard.
Figure 2 is a photograph of an inner layer, doublesided core of the backplane, prior to lamination and drilling. It shows the couplers in more detail. The round pads are for the connector vias, and are used to attach the coupler traces to the connector pins. The rows of pads on the left are for one card slot, while the rows of pads on the right are for another card slot.
If we look at the two traces entering the picture from the bottom left side, we can see how they are routed through the connector field. These two traces are part of a differential pair where each are routed as singleended traces, i.e. with no coupling to one another. As these traces approach the first row of pads, they jog down to minimum spacing to ensure close coupling to the coupler traces attached to the pads. The close spacing continues to ensure maximum coupling to the next set of pads, where the pattern stars all over again at the bottom right. This pattern repeats all the way up the photo for each differential pair.
You may be astute to notice that the bottom coupler trace connects to a pad at each end, while the mate coupler, above it does not. When two, coplanar parallel traces are in close proximity to one another, there are two types of crosstalk generated; backward or NearEnd crosstalk (NEXT); and forward or FarEnd crosstalk (FEXT).
As the transmit signal propagates, from left to right in the photo, the rising edge of the signal initiates NEXT at the beginning of the coupled length. The NEXT voltage saturates after a critical length equal to the risetime divided by twice the propagation delay; where the risetime is in seconds, and propagation delay is in seconds per unit length. It stays saturated for twice the time delay of the coupled length. Because of differential signalling, the NEXT voltages are of opposite phase on the respective couplers.
At the coupler pin, there is a reflection caused by the via. Since the couplers, at the farend, are not terminated, in the characteristic impedance, and left open, any secondary reflections due to coupler via reflects back towards the receiver, again with opposite phase. When both reflections arrive back at the receiver, they will add together and add additional noise to the eye, causing intersymbol interference, as shown by the shoulder in Figure 3(A). By leaving one end open, and shorting the other one to ground, means that any secondary noise will have the same phase, and when they arrive at the receiver, they will cancel, thereby eliminating the intersymbol interference and increasing the eye amplitude as shown in Figure 3(B).
You will notice that the eye waveforms do not resemble the traditional eye diagram we are used to seeing. Instead we observe a typical NEXT eye, when the coupled length is short, compared to the bit time. There is also a line right in the middle.
Figure 4 can help to explain the reason. The blue waveform is the NEXT voltage, seen at the nearend of the coupler, in response to the red transmitted waveform. Notice that there are only pulses at an edge transition of the transmitted waveform. A rising edge creates a positive pulse, and a falling edge generates a negative pulse. The duration of each pulse is twice the time delay of the coupler length.
The receiver uses simple peakdetectors and latch to regenerate the signal back to the original waveform. A positive going pulse is detected by the positive peakdetector. When it crosses the positive voltage threshold (+V_{th}), it sets the latch output to logic high. The output remains high until a negative pulse crosses the negative threshold (V_{th}), of the negative peakdetector, and resets the latch to logic low.
And that is how crosstalk can be your friend! Of course the small coupled crosstalk signal means we have to guard against CROSSTALK from other digital signals on board. But that’s nothing that mixed signal layout design rules can’t solve. ……Wait a minute! ……We both share the same enemy? …….. Who would have thought an old Proverb, “The enemy of my enemy is my friend” [sic], would apply here too?
Reference:
[1] L. Simonovich et al, U.S. Patent 6,091,739, “HIGH SPEED DATA BUS UTILIZING POINT TO MULTIPOINT INTERCONNECT NONCONTACT COUPLER TECHNOLOGY ACHIEVING A MULTIPOINT TO MULTIPOINT INTERCONNECT.”
[2] J. Williamson et al, U.S. Patent 6,016,086, “NOISE CANCELLATION MODIFICATION TO NONCONTACT BUS.”
[3] Alexandre Guterman, Robert J.Zani, “PointtoMultipoint Gigabit Backplane Design”, IEEE International Symposium on EMC, May 1116, 2003.