## Archive for **February 2017**

## Obsessions with Conductor Surface Roughness – What’s the Dk Because of it?

You know you have an obsession when you are flying 6 miles over Colorado; look out your window at the beautiful scenery; and all you can think about is how the rocky mountain topology reminds you of conductor surface roughness! Well call me obsessed because that’s exactly what I thought on my way to DesignCon 2017 in Santa Clara, CA.

For those of you who know me, you know that I have been researching practical methods to model conductor surface roughness, and its effect on insertion loss (IL). I have presented several papers on the subject over the last couple of years. It’s one of my pet projects. This year, at DesignCon, I presented a paper titled, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”* ***.**

Everyone involved in the design and manufacture of printed circuit boards (PCBs) knows one of the most important properties of the dielectric material is the relative permittivity (*ε _{r}*), commonly referred to as dielectric constant (

*D*). But in reality,

_{k}*D*is not constant at all. It varies over frequency as you will see later.

_{k}We often assume the value reported in manufacturers’ data sheets is the intrinsic property of the material. But in actual fact, it is the effective dielectric constant (*D _{keff}*) generated by a specific test method. When you compare simulation against measurements, you will often see a discrepancy in

*D*

*keff*and IL, due to increased phase delay caused by surface roughness. This has always bothered me. For a long time I was always looking for ways to come up with

*D*

*keff*from data sheet numbers alone. Thus the obsession and motivation for my recent research work.

Since phase delay, also known as time delay (*TD*), is proportional to *D**keff *of the material, my theory was that the surface roughness profile decreases the effective separation between parallel plates, thereby increasing the electric field (e-field) strength, resulting in additional capacitance, which accounts for an increase in effective *D _{k}* and

*TD*.

The main focus of my paper was to prove the theory and to show a practical method to model *D**keff *and *TD* due to surface roughness. By referencing Gauss’s Law for charged parallel plates, I confirmed mathematically, and through simulation, how the dielectric thickness and permittivity are interrelated to e-field and capacitance. I also revealed how the 10-point mean (*R _{z}*) roughness parameter can be applied to finally estimate effective

*D*

*keff*due to roughness. Finally I tested the method via case studies.

In his book, “Transmission Line Design Handbook”, Wadell defines *D _{keff}* as the ratio of the actual structure’s capacitance to the capacitance when the dielectric is replaced by air.

*D _{keff}* is highly dependent on the test apparatus and conditions of how it is measured. There are several methods used in the industry. One method that is commonly used by many laminate suppliers is called the clamped stripline resonator test method. It is described by IPC-TM-650, section 2.5.5.5, Rev C.

In short, this method rapidly tests dielectric material for permittivity and loss tangent, over an X-band frequency range of 8-12.4 GHz, in a production environment. It does not guarantee the values are accurate for design applications.

Here’s why:

The measurements are made under stripline conditions, using a carefully designed resonant element pattern card, made out of the same dielectric material to be tested. The card is sandwiched between two sheets of unclad dielectric material under test. The whole structure is then clamped between two large plates, lined with copper foils that are grounded.

Since the resonant element pattern card and material under test are not physically bonded together, there are small air gaps between the various layers affecting measured results. These air gaps are caused in part by:

- Removing the copper from the material under test, leaving the bare substrate, complete with the micro void imprint of the copper roughness.
- The air gap between resonant element pattern card and material under test, due to the copper thickness of the etch pattern.
- The roughness profile of the copper, on the resonant element pattern card and fixture’s grounded foil reference planes, are different than would be in practice, unless the same foil type is used.

If *D _{keff}* and

*R*roughness parameters from the manufacturers’ data sheets are known, then the effective

_{z}*D*due to roughness (

_{k}*D*

_{keff}_{_rough}) of the fabricated core laminate can now be easily estimated by:

Where: *H _{smooth}* is the thickness of dielectric from data sheet;

*R*is 10-point mean roughness from data sheet; and

_{z}*D*is the

_{keff}*D*from data sheet.

_{k}With reference to Figure 1, using *D _{keff}* with rough copper model, as shown on the left, is equivalent to using

*D*

_{keff}_{_rough}, with smooth copper model, as shown on the right. Therefore all you need to do is use

*D*

_{keff}_{_rough}for impedance calculations, and any other numerical simulations based on surface roughness, instead of

*D*published in data sheets.

_{k}It is as simple as that.

Figure 1 Effective *D _{k }*due to roughness model. Using

*D*with rough copper model (left) is equivalent to using

_{keff}*D*

_{keff}_{_rough }with smooth copper model (right).

For example, one case study I presented used measurements from a CMP28 modeling platform from Wild River Technology. The PCB was fabricated with FR408HR material and reverse treated foil (RTF). Keysight EEsof EDA ADS software was used for modeling and simulation. The results are shown in Figure 2.

The left graph shows results when data sheet values for core and prepreg were used. *D _{keff}* measured (red) was 3.761, compared to simulated

*D*(blue) of 3.626, at 10 GHz. This gave a delta of ~ 4%. But when the

_{keff}*D*was used for core and prepreg the delta was within 1%.

_{keff_rough}Figure 2 Measured vs simulated *D _{keff}* using FR408HR data sheet values for core and prepreg (left) and using

*D*(right). Modeled and simulated with Keysight EEsof EDA ADS software.

_{keff_rough}The paper shows in more detail how Equation 1 was derived, based on Gauss’ Law. In addition, I show how IL and phase delay is also improved when *D _{keff_rough}* is used instead of data sheet values. You can download the paper titled,

*“A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”*, and other papers on modeling conductor loss due to roughness from my web site.