Bert Simonovich's Design Notes

Innovative Signal Integrity & Backplane Solutions

Field Solver Nuances: How to avoid GIGO

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To avoid “garbage in, garbage out” (GIGO) with any field solver, first you need to understand the little nuances of PCB fabrication process and how to interpret manufacturers’ data sheets. But most importantly you need to understand the tool’s user interface and what it is asking for.

All 2D or 3D field solvers will give accurate impedance predictions. The differences are the type of solvers used under the hood and complexity of the user interface. Simple 2D field solvers, used in many of today’s stackup planners, simply give predicted characteristic impedance based on material properties and trace geometries. More complex, 2.5D or 3D field solvers, allow for additional material parameters and can predict insertion loss, phase delay and impedance over frequency. Some will even export RLGC and touchstone files for further signal integrity analysis.

Standard PCBs are fabricated using cores and prepreg material. Prepreg sheets are a mixture of fiberglass (glass) cloth and resin which is partially cured. Cores are simply cured prepreg sheets with copper bonded to one or both sides of the laminate. Copper is etched away on each side of the foil to leave the circuit pattern.

In a multi-layer PCB, cores and prepreg sheets are alternately stacked symmetrically above and below the middle of the layup then pressed under heat and pressure. The prepreg layers gets thinner when pressed allowing the resin to fill the voids between the copper features that were etched away on the cores.

One important parameter for accurate impedance modeling is dielectric constant (Dk). The best source is from laminate suppliers’ data sheets. But all data sheets from laminate suppliers are not the same.

“Marketing” data sheets are data sheets easily found on laminate suppliers’ websites. They are meant for quick comparison of dielectric properties to narrow your search for the right laminate for your application. They include mostly thermal and mechanical properties, which are important for the physical structure of the material and how it will perform with other material properties in the stackup during processing [3].

Marketing data sheets usually only report a typical Dk value at fifty percent resin content at two or three frequency points. Depending on glass style, resin content and thickness, Dk and dissipation factor (Df), will be different for different cores and prepreg thicknesses for the same laminate chemistry. In the end, they are not representative of what is needed to design an actual stackup, or to do impedance and loss modeling. Using these numbers will almost always lead to inaccurate impedance and signal integrity (SI) results.

Instead, you need to use the same Dk/Df construction table data sheets PCB fabricators use for the stackup. Dk/Df construction tables provide the actual core and prepreg thicknesses, resin content, and Dk/Df for the different glass styles, over different frequencies. Depending on the stackup, a combination of thicknesses is often needed to meet impedance requirements and have different Dk values.

Many engineers assume Dk published is the intrinsic property of the material. But in fact, it is the effective Dk (Dkeff) measured by a specific industry standard test method. It does not guarantee the values directly correspond to design applications. When compared against measurements from a design application, there is often a discrepancy in Dkeff due to increased phase delay caused by surface roughness [1].

Dkeff is highly dependent on the test apparatus and conditions of how it is measured. One popular test method, IPC-TM-650 clamped stripline resonator test method, assures consistency of product during fabrication. Due to the nature of this test method, the materials under test are not physically bonded together, air is entrapped between the various layers. These small air gaps are caused by: roughness of the copper foil plates in the fixture; roughness profile imprint left on the surface from the foil that was removed from the test samples; copper removed on the resonant element pattern card. Air entrapment results in a lower Dkeff than what is measured because in a real PCB everything is bonded together, with no air entrapment [3].

All glass weave reinforced laminates are anisotropic, which means E-field orientation, relative to the glass weave, is different depending on test method. E-fields produced from tests like IPC-TM-650 are transverse to the glass weave and Dkeff measured is out-of-plane.

E-fields produced by TM-650- split post cavity resonators, are parallel to the fiberglass weave Dkeff measured this way is in-plane. Dkeff is typically higher for in-plane measurements, compared to out-of-plane, depending on the glass resin mixtures used in the stackup.

Another source of discrepancy is not accounting for increased Dkeff due to the pressed thickness of prepreg. Since prepreg sheets have a certain percentage of resin content for the thickness, after pressing the resin content is reduced and since Dk is a function of resin and glass mixture, there will be a higher percentage of glass after pressing and thus slightly higher Dkeff.

The most common PCB trace geometries are micro-strip and stripline. A simple microstriip geometry is bare copper traces over a reference plane, separated by a dielectric height H, as shown in Figure 1. Depending on the stackup, there may be a core and prepreg layer between the outer layer and reference plane with the same or different Dk values for Dk1 and Dk2.

Simple stripline geometry has copper traces between two reference planes. For single-ended (SE) signals, there is only one trace used in the field solver to calculate the SE impedance. For differential pairs, there are two traces separated by a space. Because resin fills the voids between copper features the Dkresin will be lower than Dk1 or Dk2, shown in Figure 1.

The last thing to note is the wider side of the trace always faces the core material. This is a very important point to remember when using any field solver. If you get it reversed, it will lead to inaccurate results.


Figure 1 Generic microstrip and stripline geometries.

Thickness of copper traces is an important parameter for accurate impedance prediction. Copper thickness is usually specified in ounces per square foot. Most common thicknesses for inner layer traces are ½ oz. and 1 oz. foil. But field solvers expect an actual thickness dimension.

Most designers assume 0.7 mils (18um) thickness and 1.4 mils (36um) for ½ oz. and 1 oz. respectively. But because of the price of copper, the copper you get from foil manufacturers will likely be the minimum thickness allowed under IPC-4562A. When you factor in the typical thickness after fabrication, the typical thickness can be 0.6 mils (15um) and 1.2 mils (30um). But the minimum thickness allowed under IPC-A-600G-3.2.4 is 0.45 mils (11.4um) and 0.98 mils (24.9 um) for ½ oz. and 1 oz. respectively.

Due to the nature of the etching process, the traces will usually be trapezoidal in shape. This is known as the etch factor (EF), as defined by IPC-A-600G. It is the ratio of the thickness (t) to half the difference between W1 and W2.



Some field solvers will define EF differently so it is important to understand how to specify it properly.

Once you’ve come up with a proposed stackup, the next step is to do some impedance modeling. Normally your fab shop comes up with this, but it is a good idea to validate their proposal, to ensure you are in sync with them.

The first thing to do, is identify the layers from which to model. Next, is to use your field solver, to model characteristic impedance. Since all field solvers are different, and user interfaces can be confusing, make sure you understand the little nuances of your tool.

The next thing is to identify the core layers in the stackup and input H1 and Dk1 for the dielectric. Then, input the pressed thickness for prepreg H2 and Dk2, not the thickness found in Dk/Df construction tables. You can usually trust the pressed thickness from your fab shop. But be careful how the field solver defines H2. Most field solvers define it as shown in Figure 1, but some solvers, like Polar Si9000e, define it as (H2+t), shown in Figure 2. Usually, you can trust the pressed thickness from your board shop stackup drawing.

Finally, if your field solver allows for it, fill in Dkresin between two traces if you know it. It will be lower than Dk2. Since this number is generally hard to obtain, a rough estimate to use is the lowest Dk value from the highest resin content prepreg found in Dk/Df construction tables.

Once everything is set up, optimize the line width and space, until the desired characteristic impedance is reached. One last point to remember, is that all 2D field solvers only calculate lossless characteristic impedance. But when we measure an impedance test coupon with a time domain reflectometer (TDR), we are measuring the instantaneous impedance along the PCB trace.

More often than not, impedance is different than what was predicted. This is because a 2D field solver only calculates the lossless characteristic impedance of the cross-sectional geometry; while a TDR measures the instantaneous impedance of a lossy transmission line at every point along its length.

A 2D field solver has no input for conductor resistivity, dielectric loss, or how long the conductor is. Resistive loss often results in a slow monotonic rise in the impedance profile. IPC-TM-650 specifies the measurement zone between 30-70 % and most PCB fab shops, will measure an average impedance

In this example, shown in Figure 2, for a low loss dielectric, there is a 4-5 ohm difference depending on where the measurement is taken. When all input parameters are included correctly for a lossy transmission line model, you can see there is excellent correlation.


Figure 2 Lossless characteristic impedance from Polar SI9000 field solver (left) vs measured TDR plot from an impedance coupon and lossy transmission line model from Polar Si9000.

Although minor differences in individual parameters may have second order affects, collectively they could add up to give poor correlation to measurements. But if you consider all the nuances discussed in this article, you can get pretty good accuracy as shown in Figure 2.

[1] Bert Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”, DesignCon 2017, Santa Clara, CA

[2] Bert Simonovich, “PCB Fabrication: What SI/PI Engineers Need to Know for First Time Modeling Success”, DesignCon 2021 Spring Break Webinar, April 12, 2021

[3] Bert Simonovich, A Tale of Two Data Sheets and How Foil Roughness Affects Dk, White paper

Written by Bert Simonovich

July 23, 2022 at 12:04 pm

2 Responses

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  1. Hi Bert, regarding Figure 2, you mentioned there is a 4-5 ohms difference between average TDR impedance and simulated lossless characteristic impedance, and I believe the gap is due to resistance with the trace length. May I know how long your trace length is on this case? Thanks.

    Nick Huang

    August 10, 2022 at 4:27 am

    • Hi Nick, Thank you for your comment. You are correct the rising slope of TDR plot is due to trace resistance length. I believe the test coupon was 8 inches long.

      Bert Simonovich

      August 10, 2022 at 8:51 am

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