Bert Simonovich's Design Notes

Innovative Signal Integrity & Backplane Solutions

The Poor Man’s PCB Via Modeling Methodology

with 17 comments

You are a backplane designer and have been assigned to engineer a  new high-speed, multi-gigabit serial link architecture from several line cards to multiple fabric switch cards across a backplane. These links must operate at 6GB/s day one and be 10GB/s (IEEE 802.3KR) ready for product evolution. The schedule is tight, and you need to come up with a backplane architecture to allow the rest of the program to progress on schedule.

imageYou come up with a concept you think will work, but the backplane is thick with over 30 layers. There are some long traces over 30 inches and some short traces of less than 2 inches between card slots. There is strong pressure to reuse the same connector you used in your last design, but your gut tells you its design may not be good enough for this higher speed application.

Finally, you are worried about the size and design of the differential via footprint used for the backplane connectors because you know they can be devastating to the quality of the received signal.  You want to maximize the routing channel through the connector field, which requires you to shrink the anti-pad dimensions, so the tracks will be covered by the reference planes, but you can’t easily quantify the consequences on the via of doing so.

You have done all you can think of, based on experience, to make the vias as transparent as possible without simulating. Removal of non-functional pads on the inner layers, and planning to back-drill the connector via stubs will help,  but is it enough? You know in the back of your mind the best way to answer these questions, and to help you sleep at night,  is to put in the numbers.

So you decide to model and simulate the channel. But to do so, you need accurate models of the vias to plug into your favorite circuit simulator. But how do you get these? You have heard it all before; “for high-speed, the best way to model a via is with a 3D electro-magnetic field solver”.  Although this might be true, what if you don’t have access to such a tool, because the cost is more than your company wants to spend, or because you don’t have the expertise nor the time to learn how to build a model you can trust to make a timely decision?

On top of that, 3D field solvers typically produce S-parameter behavioral models. Since they represent only one sample of a given construction, it is impossible to perform what-if, worst case, min/max analysis with a single behavioral model. Because of this,  many iterations of the model are required; causing further delay in getting your answer.

A circuit model on the other hand, is a schematic representation of the actual device. For any physical structure, there can be more than one circuit model to describe it. All can give the same performance, up to some bandwidth. When run in a circuit simulator, it predicts a measurable performance of the structure. These models can be parameterized so that worst case analysis can be explored quickly.

The problem with a circuit model is that you often need a behavioral model to calibrate it, or need to use analytical equations to estimate the parameters. But, as my friend Eric Bogatin often says, “an OK answer NOW! is better than a great answer late”.

In the past, it was next to impossible to develop a circuit model of a differential via structure without a behavioral model to calibrate it. These behavioral models were developed through empirical formulas, measured data, or through the use of 3D EM field solvers.

Now, there is another way. I have nicknamed it, “The Poor Man’s PCB Via Modeling Methodology”. Here’s how it works.

Anatomy of a Differential Via Structure:

imageAn example of a differential via structure, shown in Figure 1, is representative of vias used to connect surface mounted components or backplane connectors to internal layer traces.

The via barrel is a plated through hole extending the entire length of a PCB stack-up. The outside diameter equals the drill diameter. The inside diameter is the finished hole size (FHS) after plating. Pads are used on layers to ensure there is sufficient copper for track attachment after drilling operation. When used in this fashion, they are referred to as functional pads. Anti-pads are the clearance holes in the plane layers allowing the via barrel to pass through them without shorting.

The via portion is the length of the barrel connecting one signal layer to another. It is often referred to as the through via since it is part of the signal net. The stub portion is the rest of the barrel extending to the outer layer of the PCB. In high-speed designs, a good rule of thumb to remember is that a via stub should be less than 300mils/BR in length; where BR is the bit rate in Gb/s.

Building a Simple Scalable Circuit Model:

imageOn close examination of Figure 2, a differential via structure can be represented by a twin-rod transmission line geometry with excess capacitance (shown in red) distributed over its entire length. The smaller the anti-pad diameter, the greater the excess capacitance. This ultimately results in lower via impedance, causing higher reflections.

In all high-speed serial link designs, it is common practice to remove all non-functional pads and to maximize the anti-pad clearance as much as practically possible. Oval anti-pads are often used in this regard to further mitigate excess via capacitance.

Figure 3 illustrates the equivalent circuit for a differential via that could be used in a channel topology simulation. Here it is modeled with Keysight ADS software using a coupled line transmission line model for each section. This equivalent circuit model can be scaled for any combination of layer transitions and integrated in any channel simulation scenario.

imageSince the cross-section of the via is constant throughout its length, the differential impedance of all sections of the via are the same. We only need to know the physical length of each segment and the effective dielectric constant (Dkeff) to get the time delay of each segment.

When driven differentially, the odd-mode parameters of each via are of major importance. Since the even-mode parameters have no impact on differential performance, both odd and even-mode parameters are set to the same values in the model.

The challenge then is to calculate the odd mode impedance (Zodd), representing the individual via impedance (Zvia), of a differential via structure and the effective dielectric constant (Dkeff) based on its geometry. Simple equations are used to determine these parameters.

Developing the Equations:

Anti-pads can vary in size and shape. They can be anything from round, to oval around each via, or even a large oval surrounding both vias as illustrated in Figure 4. Square, or rectangular variations (not shown) are similar. image

Referring back to Figure 2, we see the structure of each via looks a lot like two coaxial transmission lines with the inner layer reference planes acting like a shield. Electrostatically this is a good approximation, but because the shield is not continuous, the magnetic fields are not contained like they are in a coaxial structure. Instead they behave more like magnetic fields around a twin-rod structure.

So here lies the secret in modeling a differential via. We take the best of both geometries to calculate the odd-mode impedance representing Zvia.

For inductance, we will use the odd-mode inductance formula from the twin-rod transmission line geometry to calculate Lvia :


Referring to Figure 4, we then calculate the odd-mode capacitance for Cvia derived from an approximate formula for an elliptic coaxial structure developed by M.A.R. Gunston in his book, “Microwave Transmission Line Impedance Data” . In the original formula, both shield (W’+b) and inner conductor (w+t) are elliptical in shape and are dimensioned as shown. When the anti-pads are circular, then ln[(W’+b) /(w+t)] reduces to just ln[b/t)]; which is the denominator in the Coax equation. If we use Gunston’s approximation to calculate Cvia, then the equation becomes:










Since conventional FR4 type laminates are fabricated with a weave of glass fiber yarns and resin, they are anisotropic in nature. Because of this, the dielectric constant value depends on the direction of the electric fields. In a multi-layer PCB, there are effectively two directions of electric fields.

The oneimage we are most familiar with has the electric fields perpendicular to the surface of the PCB; as is the case of stripline shown here in Figure 5. The dielectric constant, designated as Dkz in this case, is normally the bulk value of the dielectric specified by the laminate manufacturer’s data sheet.

The other case has the electric fields running parallel to the surface of the PCB, as is the case when a signal propagates through a differential via structure. In this situation, the dielectric constant, designated as Dkxy, can be15-20% higher than Dkz .

Therefore, assuming a nominal 18% anisotropic factor, Dkxy = 1.18(Dkz)

Now that we have defined Lvia, Cvia and Dkavg, Zvia can be estimated using the following equation:


But we are not finished yet. We still need to determine the effective dielectric constant (Dkeff) in order to accurately model the delay through the via and stub portion. Without the correct value, the quarter-wave resonant nulls in the insertion loss plot, due to the stub length, cannot be accurately predicted. The value for Dkeff is determined based on how much the via’s odd-mode impedance is decreased due to the distributed capacitive loading of the anti-pads.

To help us with this task, we start with the twin-rod formula. The odd-mode impedance (Zodd) is half the differential impedance (Ztwin), and is expressed as:


By substituting Equation 1 for Zodd into the equation above, and solving for Dkeff we eventually come up with the following equation:


Validating the Model:image

A simple 26 layer test vehicle was fabricated to compare the accuracy of the differential via circuit model to real vias. It consisted of two differential via pairs separated by 6 inches of 100 Ohm stripline differential pairs. Three sample via structures representing long, medium and short via stubs, as summarized in Figure 6, were measured using an Agilent N5230A VNA.

The differential vias had the following common parameters:

imageVia drill diameter; D = 28 mils
Center to center pitch; s = 59 mils
Oval anti-pads= 53 mils x 73 mils
Dk of the laminate = 3.65
Anisotropy in Dkxy = 18%
Zvia = Zstub = 31.7 Ohms (per Equation 1)
Dkeff = 6.8 (per Equation 2)

Agilent ADS software was used to model and facilitate simulation correlation of the measured data as captured in Figure 7. This simple model accounts for the discontinuity of the long through section and the long stub section. The top half is the measured channel using an S-parameter file. The bottom half is a circuit model of the channel. Since the probes were not calibrated out, they are part of the device under test. The balun transformers are used to facilitate the display of the S-parameter and TDR results.image

The comparison between the measured and simulated results of the insertion loss and TDR response for the three via stub cases using this simple approximation methodology is summarized in Figure 8.  The insertion loss plots, in the frequency domain, are shown on the left, while the TDR plots are shown on the right.

The resonant nulls in the SDD21 plots are due to the stub lengths. As you can see, the longer the stub, the lower the resonant frequency null. If this null happens at the Nyquist frequency of the bit rate, the eye will be totally closed. This is why we back-drill them out after the board has been fabricated.

The simulation correlation is excellent up to about 12 GHz. The TDR plots show excellent impedance matching and delay for all three cases, while the simulated stub resonant frequencies match the measured frequencies very well. As you can see, these simple approximations for Dkeff and Zvia are perfectly adequate in providing a quick and accurate circuit model for differential through hole vias typically used in backplane applications.image


As illustrated, a simple twin-rod model (Figure 2) is used as the basis for a practical differential via circuit modeling methodology. By using Equation 1 and Equation 2, you can quickly determine the odd-mode impedance and effective dielectric constant needed for the circuit model.

Of course, you should use this methodology first as a rough starting point to quickly estimate the performance of your differential via design. If your worst case topology simulations show the performance is marginal, then it is worth while to invest the time and money to develop a 3D full wave model to perform a more accurate analysis.

On the other hand, if you find this approximation shows the vias have little impact on the channel performance, it may be of greater value for you to invest your time and money in resolving other critical issues with your design.

Try it the next time you are losing sleep over your design challenges.

For more Information:


If you liked this design note and want to learn more, or get more details on this innovative via modeling methodology, you can visit my web site, LAMSIM , and download a copy of the white paper I wrote along with Eric Bogatin and Yazi Cao titled, “Method of Modeling Differential Vias” .

While you are there, feel free to investigate my other white papers and publications.

If you would like more information on our signal integrity and backplane services, or how we can help you achieve your next high-speed design challenge, email us at:



UPDATE: In collaboration with Saturn PCB, I am pleased to announce my differential via equations above have been incorporated in a new impedance calculator available now in Saturn PCB Tool Kit software suite.


Written by Bert Simonovich

March 14, 2011 at 11:23 am

17 Responses

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  1. Bert,

    As a young EE in a small group with very little ability to buy high end tools, you nailed my problem on the head with this article. For me, the most helpful thing that you provide is your validation results for the models. Eric did the same thing in his book with regard to rule-of-thumb approximations and simulations. Both of you are truly assets to the field and have been an invaluable resource for me as a young EE.


    Cory Keitz

    May 17, 2011 at 3:07 pm

    • Cory, thank you so much for the kind words. I’m glad you found the topics useful. It is comments like yours that makes sharing these design notes so satisfying. Best of luck with your career.

      Bert Simonovich

      May 17, 2011 at 8:35 pm

    • Side note: This feels like an out of body experience. My name is also Cory Keitz and I am a design engineer who does PCB design. I don’t usually work at the level you are describing but the odds of two people with the same (not so common) name doing the same work is staggering.

      Mind Blown! Thanks.

      Cory Keitz

      June 28, 2011 at 3:59 pm

  2. It’s hard to read the values in figure 7. Are the impedances of the vias shown in figure 8 31.7 ohm with 6.8 dielectric constant for both the signal paths and the stubs?

    Dennis Han

    April 9, 2013 at 11:45 am

    • Yes, the same values of 31.7 Ohms and Dkeff=6.8 were used for Via signal path and stub in all three cases in fig 8.

      Bert Simonovich

      April 9, 2013 at 12:11 pm

  3. Thank you Bert. Highy informative and concise. Would love to see the addition of formulas for back-drilled via structures. Thanks. Oscar

    Oscar Fallah

    March 29, 2014 at 9:09 pm

    • Oscar, Thank you for your comment. There are no additional formulas for back-drilled vias. They are just vias without a stub.

      Bert Simonovich

      March 30, 2014 at 4:43 am

  4. Nice article & white papers on your site. What’s your take on the value of ground vias near differential via pairs? Many of the articles on controlled impedance vias (single ended) seem to think they are essential? Is this like the conventional wisdom for guard traces Vs. the reality pointed out in your white papers on the subject on your web site?

    Alex Henderson

    March 27, 2016 at 3:05 pm

    • Alex, Ground vias near differential via pairs provide common signal return path due to skew caused by difference in length between the positive and negative path of a differential pair. Skew is most often caused by trace length mismatch, or connector pin length deltas. Skew causes mode conversion which exacerbates EMI.

      If there is space, I like to add two GND vias, one each side of the diff via pair, and they should be symmetrical spacing to each signal via. If you can’t put two vias each side then a single via placed so that it is symmetrically spaced away from both signal vias is the next choice.

      Bert Simonovich

      March 27, 2016 at 3:28 pm

      • Bert:
        Thank you for the concise reply. For my application I am dealing with closely coupled traces and vias w/ a single oval antipad similar to one of the options discussed in your white paper. Can you suggest a “poor man’s” version of the calculations necessary to take the impact of the ground vias on the impedance of the diff pair vias in to account? I have room for the ground vias (I could actually fit four symmetrically spaced around the diff pair) but I want to maintain the same impedance. BTW I will be building some boards using including one w/ flex to rigid transitions and a backplane based on Isola i-Speed materials. On the backplane I have room to include some test traces. I don’t have access to a TDR or I would volunteer measured data for validation of your models.

        Alex Henderson

        March 27, 2016 at 3:42 pm

      • Alex,

        Like all answers to signal integrity questions is, “It depends”. Most transmission line equations only gives an approximate answer. There are only 3 transmission line equations that will give an exact answer. They are coax, twin-rod and rod-over-plane geometries. Only a 3D field solver can give a more accurate answer for vias. The caveat is that all parameters are input correctly and the solver takes into account the anisotropic effect of the dielectric.

        That being said, the impedance of a differential via is primarily determined by the two vias proximity to one another. If there were no antipads, then the calculation for differential impedance is the simple twin-rod equation. -See the blog article on twin-rod following this post or refer to the actual referenced white paper on my web site.

        Where it gets complicated is the excess distributed capacitance due to nearby ground structures. Since the closest ground structures are usually the antipads through the plane layers distributed through the cross-section, (defined by dimensions in fig 4 for example), they will affect the excess capacitance more so than a nearby GND via, unless the near by ground via(s) are closer than the distance between the vias and closest anti-pad edge.

        Also the “Poor Man’s Equations” works best when the layers are closely spaced pretty evenly throughout the stack-up. If you have a stackup with closely spaced layers near the top and bottom and a thick dielectric core in the center, then the transmission line via model becomes a little more complicated. For the sections where the copper layers are closely spaced, you would use the “Poor Man’s Equations”. In the center section, you would use the simple twin-rod equations because in that area there is no copper and thus no anti-pads. Remember to use Dk_xy instead of bulk Dk from data sheets.

        It is difficult to provide any more detailed answers without knowing the exact details of your design. From past experience though, I have found that adding a pair of GND vias each side of the diff vias at the same spacing as the diff vias were enough. Usually these vias are on the outer most edge of the oval, and the outer edge of the via hole is tangent to oval antipad’s edge. With this geometry, the capacitive effect of GND via would already be taken into account by dimension ‘b’ in fig 4 right. Of course of you are going through a connector, or component BGA package, the pin footprint will dictate dimensions and you would adjust anti-pads accordingly to get best impedance match vs routability of traces.

        Bert Simonovich

        March 28, 2016 at 11:00 am

  5. Hello Bert,

    This is a very interesting article, as is the white paper you co-authored with Bogatin and Cao. The one thing I can’t seem to grasp in this is that when modeling a via for single ended capacitance, the anti-pad diameter, via pad diameter, and drill diameters are used in the calculation. However in the paper, it seems the via pad diameter is not included. Why is that? Should it be included like it is with calculating for a single ended via?

    Thank you

    C. Sullivan

    September 8, 2016 at 10:21 pm

    • Craig,

      Thank you for your interest. Technically you are correct with your question on inclusion of pads. The answer is pain for gain. The transmission line model of the via becomes a bit more complex in that you now have to add a small section of transmission line for the respective pads. In most cases a via will have 3 pads, one on top layer, one on internal signal layer and one on the bottom layer. There may or may not be an anti-pad on the same layer. If there is, then the impedance would be coaxial, or twin-axial to determine the impedance of that section. The top and bottom layers will likely only have air as dielectric or solder mask. You need to use the right Dk accordingly. I had experimented adding the pads or not and found no appreciable difference in correlation results.

      Remember, this method is meant to give you “an answer now rather than a better answer late”, as my friend Eric Bogatin likes to say. Feedback from others found this method helps them with the what-if analysis to narrow down the via/antipad geometry before building a 3D model. I have consistently achieved good correlation with 3D models up to 10-12GHz.

      Also read my last comment to Alex below for improving model when layers are not closely spaced. Feel free to contact me off line if you have more questions.

      Bert Simonovich

      September 9, 2016 at 10:01 am

  6. I just started to work on this topic because if you want to do 3D simulation and you don’t have any numbers to begin with then good luck! Thanks for sharing your excellent paper however I have some questions

    -What value you used for FHS in your calculations? typically plating is of 1mils so it should be 27mils.

    -What is the difference between Zvia and Zodd? I am little bit confused because the value shown above for the Zvia is typically for the Zodd.

    -Have you done any additional work on this topic as this was published back in 2011?


    March 3, 2020 at 5:24 pm

    • Khan,
      Thank you for your comments. To answer your questions:
      – The via impedance calculations depend on outer diameter of the via barrel which is the drill size, not FHS.
      – There is no difference between Zvia and Zodd. The equations are bases on odd mode impedance of twin-rods.
      – I have not done any additional work except to test the equations from time to time with 3D simulated results. As you have experienced sometimes you need a starting point. It is equivalent mindset to using transmission line equations rather than 2D field solvers.

      Bert Simonovich

      March 4, 2020 at 8:09 am

      • Thanks for your reply.
        I was trying to calculate the Zvia and DKeff but I am not getting exactly same numbers as you calculated(31.7ohms and 6.8) so I am wondering where I am making a mistake.
        Also the Agilent ADS link is not working and the snaps are not very clear.


        March 12, 2020 at 11:25 am

  7. Khan,

    I don’t know numbers you used.

    You need to refer to fig 4 left antipads shown above
    These are the parameters:
    -Drill diam = 28 mils
    -s = 59 mils
    -dim b = 53 mils
    -dim W’ = 73 mils
    -Dkz1 = 3.69
    -Dkz2 =3.58
    -Dkz = (3.69+3.58)/2 = 3.64
    -Anistropy = 18%
    -Dkxy = 0.18 * Dkz = 4.3
    -Dkavg = (4.3+3.64)/2 =3.96

    Then use eq. 1 for Zvia = 31.8 ohms
    Then use eq. 2 for Dkeff = 6.73
    Then Zdiff = 2*Zvia = 63.7 ohms

    More detail can be found in the white paper link at the end of the blog.

    Bert Simonovich

    March 12, 2020 at 12:36 pm

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