I don’t know numbers you used.

You need to refer to fig 4 left antipads shown above

These are the parameters:

-Drill diam = 28 mils

-s = 59 mils

-dim b = 53 mils

-dim W’ = 73 mils

-Dkz1 = 3.69

-Dkz2 =3.58

-Dkz = (3.69+3.58)/2 = 3.64

-Anistropy = 18%

-Dkxy = 0.18 * Dkz = 4.3

-Dkavg = (4.3+3.64)/2 =3.96

Then use eq. 1 for Zvia = 31.8 ohms

Then use eq. 2 for Dkeff = 6.73

Then Zdiff = 2*Zvia = 63.7 ohms

More detail can be found in the white paper link at the end of the blog.

]]>Thanks for your reply.

I was trying to calculate the Zvia and DKeff but I am not getting exactly same numbers as you calculated(31.7ohms and 6.8) so I am wondering where I am making a mistake.

Also the Agilent ADS link is not working and the snaps are not very clear.

Khan,

Thank you for your comments. To answer your questions:

– The via impedance calculations depend on outer diameter of the via barrel which is the drill size, not FHS.

– There is no difference between Zvia and Zodd. The equations are bases on odd mode impedance of twin-rods.

– I have not done any additional work except to test the equations from time to time with 3D simulated results. As you have experienced sometimes you need a starting point. It is equivalent mindset to using transmission line equations rather than 2D field solvers.

-What value you used for FHS in your calculations? typically plating is of 1mils so it should be 27mils.

-What is the difference between Zvia and Zodd? I am little bit confused because the value shown above for the Zvia is typically for the Zodd.

-Have you done any additional work on this topic as this was published back in 2011?

]]>Craig,

Thank you for your interest. Technically you are correct with your question on inclusion of pads. The answer is pain for gain. The transmission line model of the via becomes a bit more complex in that you now have to add a small section of transmission line for the respective pads. In most cases a via will have 3 pads, one on top layer, one on internal signal layer and one on the bottom layer. There may or may not be an anti-pad on the same layer. If there is, then the impedance would be coaxial, or twin-axial to determine the impedance of that section. The top and bottom layers will likely only have air as dielectric or solder mask. You need to use the right Dk accordingly. I had experimented adding the pads or not and found no appreciable difference in correlation results.

Remember, this method is meant to give you “an answer now rather than a better answer late”, as my friend Eric Bogatin likes to say. Feedback from others found this method helps them with the what-if analysis to narrow down the via/antipad geometry before building a 3D model. I have consistently achieved good correlation with 3D models up to 10-12GHz.

Also read my last comment to Alex below for improving model when layers are not closely spaced. Feel free to contact me off line if you have more questions.

]]>This is a very interesting article, as is the white paper you co-authored with Bogatin and Cao. The one thing I can’t seem to grasp in this is that when modeling a via for single ended capacitance, the anti-pad diameter, via pad diameter, and drill diameters are used in the calculation. However in the paper, it seems the via pad diameter is not included. Why is that? Should it be included like it is with calculating for a single ended via?

Thank you

]]>Alex,

Like all answers to signal integrity questions is, “It depends”. Most transmission line equations only gives an approximate answer. There are only 3 transmission line equations that will give an exact answer. They are coax, twin-rod and rod-over-plane geometries. Only a 3D field solver can give a more accurate answer for vias. The caveat is that all parameters are input correctly and the solver takes into account the anisotropic effect of the dielectric.

That being said, the impedance of a differential via is primarily determined by the two vias proximity to one another. If there were no antipads, then the calculation for differential impedance is the simple twin-rod equation. -See the blog article on twin-rod following this post or refer to the actual referenced white paper on my web site.

Where it gets complicated is the excess distributed capacitance due to nearby ground structures. Since the closest ground structures are usually the antipads through the plane layers distributed through the cross-section, (defined by dimensions in fig 4 for example), they will affect the excess capacitance more so than a nearby GND via, unless the near by ground via(s) are closer than the distance between the vias and closest anti-pad edge.

Also the “Poor Man’s Equations” works best when the layers are closely spaced pretty evenly throughout the stack-up. If you have a stackup with closely spaced layers near the top and bottom and a thick dielectric core in the center, then the transmission line via model becomes a little more complicated. For the sections where the copper layers are closely spaced, you would use the “Poor Man’s Equations”. In the center section, you would use the simple twin-rod equations because in that area there is no copper and thus no anti-pads. Remember to use Dk_xy instead of bulk Dk from data sheets.

It is difficult to provide any more detailed answers without knowing the exact details of your design. From past experience though, I have found that adding a pair of GND vias each side of the diff vias at the same spacing as the diff vias were enough. Usually these vias are on the outer most edge of the oval, and the outer edge of the via hole is tangent to oval antipad’s edge. With this geometry, the capacitive effect of GND via would already be taken into account by dimension ‘b’ in fig 4 right. Of course of you are going through a connector, or component BGA package, the pin footprint will dictate dimensions and you would adjust anti-pads accordingly to get best impedance match vs routability of traces.

]]>Bert:

Thank you for the concise reply. For my application I am dealing with closely coupled traces and vias w/ a single oval antipad similar to one of the options discussed in your white paper. Can you suggest a “poor man’s” version of the calculations necessary to take the impact of the ground vias on the impedance of the diff pair vias in to account? I have room for the ground vias (I could actually fit four symmetrically spaced around the diff pair) but I want to maintain the same impedance. BTW I will be building some boards using including one w/ flex to rigid transitions and a backplane based on Isola i-Speed materials. On the backplane I have room to include some test traces. I don’t have access to a TDR or I would volunteer measured data for validation of your models.

Alec

Alex, Ground vias near differential via pairs provide common signal return path due to skew caused by difference in length between the positive and negative path of a differential pair. Skew is most often caused by trace length mismatch, or connector pin length deltas. Skew causes mode conversion which exacerbates EMI.

If there is space, I like to add two GND vias, one each side of the diff via pair, and they should be symmetrical spacing to each signal via. If you can’t put two vias each side then a single via placed so that it is symmetrically spaced away from both signal vias is the next choice.

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