Archive for the ‘Useful Equations’ Category
PCB Vias – An Overview
Vias make electrical connections between layers on a printed circuit board. They can carry signals or power between layers. For backplane designs, the most common form of vias use plated through hole (PTH) technology. They connect the pins of connectors to inner signal layers. A PTH via is formed by drilling a hole through the layers to be connected and then copper plating it.
High Density Interconnects (HDI) is another via technology used to form very small vias where drilling holes, using a conventional drill bit, is impractical. Also known as microvias, this technology creates the hole with a laser before plating.
Via Aspect Ratio
Via aspect ratio is defined as the ratio of the circuit board thickness to the smallest unplated drilled hole diameter. It is an important metric you need to be aware of when specifying the minimum via hole size for your design, and designing your stackup. For example, an unplated via with a drill diameter of 0.020 inches and a board thickness of 0.200, would have an aspect ratio of 10:1. The smaller the aspect ratio, the more consistent the plating is throughout the length of the via. It is desirable to have 2 mil plating thickness for the via walls. Large aspect ratio vias tend to have more plating at each end compared to the middle. This increases the chance of cracked via barrels due to zaxis expansion while soldering.
An aspect ratio of 6:1 pretty much ensures your board can be fabricated anywhere. Most highend board shops have the capability of fabricating boards with 10:1 aspect ratio; for drill diameters of less than 0.020 inches. Practically, the smallest drill diameter used for a through holed via is 0.013 inches. At 10:1, the maximum board thickness would be 0.130 inches.
For drill diameters larger than 0.020 inches, the max aspect ratio can be anywhere from 15:1 to over 20:1; depending on the board shop. Since backplane via hole size is driven by the compliant pins of the connector, it is best to work with your board shop to determine the maximum board thickness they can fabricate with the minimum finished hole size (FHS) specified in the design.
Via Configurations
The following lists the various via configurations you might expect to find on any multilayer PCB design:

Stub Via

Through Via
 Blind or Microvia

Buried Via

Backdrilled Via
Stub Via
The Stub Via is the most common via configuration found in PCBs today. As illustrated, there are two variations; Stub Via A and Stub Via B.
For the Stub Via A example, it shows the through portion starting from the top layer and ending at some inner layer. The stub portion is the remaining portion continuing from the inner layer junction to the bottom layer.
The Stub Via B example shows the through portion originating from one internal signal layer and terminating on another internal signal layer. In this scenario, there are two stubs. The first stub is from the first internal layer junction to the top layer; the second stub is from the second internal layer junction to the bottom layer.
Through Via
Through vias are the oldest and simplest via configurations originally used in 24 layer PCB designs. Since the signals originate and terminate from the outer layers of the PCB, there are no stubs. In multilayer PCB applications, they are an inexpensive way to eliminate the resonance effects caused by stubs where other mitigation techniques are not practical or are too expensive.
Blind/Buried Via
Blind and buried vias are just like any other via, except they do not go all the way through the PCB. A Blind Via connects one or more internal layers to only one external layer. Controlleddepth drilling is used to form the holes prior to plating.
A buried via, on the other hand, is a plated hole which is completely buried within the board. It connects one or more internal layers and does not connect to an external layer. Using buried via technology is costly because the inner layers being interconnected need to be fully fabricated and plated before final lamination of the entire PCB.
A microvia is a form of blind via. Because the holes are so small (0.006 inches or less), they are formed using lasers, and cannot penetrate more than one or two layers at a time. They are most commonly used in highdensity PCB designs like cell phones, or in FPGA and custom ASIC chip packaging.
Backdrilled Via
High speed pointpoint serial link based backplanes are often thick structures; due to the system architecture and cardcard interconnect requirements. Backdrilling the via stub is common practice on thick PCBs to minimize stub length for bitrates greater than 3Gb/s.
Backdrilling is a process to remove the stub portion of a PTH via. It is a postfabrication drilling process where the backdrilled hole is of larger diameter than the original PTH. This technology is often used instead of blindvia technology to remove the stubs of connector vias in very thick highspeed backplane designs. State of the art board fabrication shops are able to backdrill to within 8 mils of the signal layer to keep, so there will always be a small stub portion attached to the via.
Backdrilling is not without limitations. Smaller vias and tighter pitch driven by large pin count BGA packages makes backdrilling impractical in these applications; due to drill bit size and tolerance issues. Fortunately, smaller via diameters limit the maximum PCB thickness due to aspect ratio; thereby limiting the length of the stub to the board thickness. Careful planning the highspeed layers within the stackup is one way to control stub length.
We worry about stubs in highspeed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot of the channel. If one of these frequency nulls happen to line up at or near the Nyquist frequency of the bit rate, the received eye will be devastated resulting in a high biterrorrate; even link failure. A shorter stub length means these resonances will be pushed out further in frequency; ideally past the 5th harmonic of the Nyquist frequency as a rule of thumb.
Rules of thumb, in general, are no substitute for actual modeling and simulation. You should never depend on them to signoff the final design; but you can use them to gain some intuition before hand. With that in mind, you can estimate the maximum stub length in inches using the following equation:
Where:
L _{Stub_max }= maximum stub length in inches.
Dkeff = effective dielectric constant of the material surrounding the via hole structure.
BR = Bit rate in GB/s.
For example, the maximum stub length at 5GB/s should be less than 0.120 inches in FR4 material with a Dkeff of 4.0 to ensure the first resonant frequency null is greater than 5 times the Nyquist frequency of the bit rate. If the stub length is greater than this, it does not mean the design will not work at 5GB/s. Depending on just how much longer it is means there will be less than optimum eye opening at the receiver.
If you know the length of the stub, you can predict the fundamental resonant frequency, using the following equation:
Where:
Stub_len = stub length in inches.
f_{o} = fundamental resonant frequency in GHz
So, using the same Dkeff of 4.0, and stub length of 0.120 inches, we calculated in the above example, the first resonant frequency null would occur at approximately 12.3 GHz. If we assume this is the 5th harmonic, then the Nyquist frequency is approximately 2.5GHz and the bit rate is 5Gb/s; which is where we started.
PCB Crosssectional Geometries
PCB crosssectional geometries describe the details of the dielectric substrates, traces and reference planes within a PCB stackup. Their physical relationship with one another can then be used to predict the characteristic impedance of the respective traces. There are only three generic crosssectional geometries with variations within each. They are:

Coplanar

Microstripline

Stripline
Coplanar:
Coplanar geometry, or sometimes called coplanar waveguide (CPW), is a signal conductor sandwiched between two coplanar reference conductors or planes. These reference planes are usually ground. The characteristic impedance is controlled by the signal trace width and the gap between it and reference planes. This is a common transmission line structure for RF and microwave designs using singlesided printed circuit board technology. As a rule of thumb, the width of the reference plane on each side of the signal trace should be at least five times the distance between the left and right plane.
Microstrip line:
The microstrip line is the most popular transmission line geometry used in two or four layer printed circuit boards. The characteristic impedance is controlled by the signal trace width, on one side of the substrate, and the thickness of the substrate to the reference plane below it. The embedded microstrip line has the signal trace covered with prepreg or other dielectric material.
Cross section views below showing Microstrip line (left) and embedded microstrip line (right).
Stripline:
Cross section views below shows an example of single stripline (left) and dual stripline (right) geometries. These are geometries are typically found in multilayer PCBs of 6 layers or more. The characteristic impedance is controlled by the trace width, thickness and its proximity to the reference planes above and below.
Single stripline has one signal layer sandwiched between two reference planes. If the signal layer is exactly spaced between the two reference planes, the geometry is called a symmetrical stripline; as opposed to an asymmetrical stripline, where the signal trace is offset from the center of the crosssection.
Dual stripline geometries have two signal layers sandwiched between reference planes, and are mainly used to save layers; caveat is a trace on one layer is routed orthogonal to the trace on the other to mitigate crosstalk.
Differential Pair Geometry:
Differential signaling is when a signal and its complement are transmitted on two separate conductors. These conductors are called a differential pair. In a PCB, both traces are routed together with a constant space between them as edgecoupled or broadsidecoupled.
Edgecoupled routes the traces sidebyside on the same layer as microstrip or stripline. The advantage is that any noise on the reference plane(s) is common to both traces and thus cancelled at the receiver. Most differential pairs are routed this way.
Broadsidecoupled routes one trace exactly over the other on 2 separate layers as dual stripline. Since each trace is more tightly coupled to its adjacent reference plane than the opposite reference plane, any noise on the planes will not be common to both traces and thus, will not be cancelled at the receiver. Because of this, and the fact that it usually results in a thicker PCB, this geometry is rarely used.
OddMode Impedance:
Consider a pair of equal width microstrip line traces, labeled 1 and 2, with a constant spacing between them. Each individual trace, when driven in isolation, will have a characteristic impedance Zo, defined by the selfloop inductance and selfcapacitance of the trace with respect to the reference plane.
When a pair of traces are driven differentially, the mode of propagation is odd. If the spacing between the transmission lines is close, there will be electromagnetic coupling between the two traces. This coupling is defined by the mutual inductance and capacitance.
The proximity of the traces to a reference plane(s) influences the amount of electromagnetic coupling between traces. The closer the traces are to the reference plane(s), the lower the selfloop inductance, and the stronger selfcapacitance to the plane(s); resulting in a lower mutual inductance, and weaker mutual capacitance between traces. The result is a lower differential impedance.
A 2D field solver is usually used to extract the parameters for a given geometry. Once the RLGC parameters are extracted, an L C matrix can be set up as follows:
The selfloop inductance and selfcapacitance for trace 1 and 2 are L11, C11, L22, C22 respectively. The off diagonal terms in each matrix, L12, L21, C12, C21, are the mutual inductance and mutual capacitance. We use the LC matrix to determine the oddmode impedance.
The oddmode impedance is the impedance of one trace, of a differential pair, when driven differentially. It can be calculated by the following equation:
Where:
Zodd = odd mode impedance
Lo = selfloop inductance = L_{11} = L_{22}
Co = selfcapacitance = C_{11}_{ }= C_{22 }
Lm = mutual inductance = L_{12} = L_{21}
Cm = mutual capacitance = C_{12}_{ }=C_{21}
Even Mode Impedance:
When current flows down both traces, of the same polarity, the mode of propagation is even and the coupling is positive. The even mode impedance can be calculated using the following equation:
Differential Impedance:
The differential impedance is twice the oddmode impedance:
Average Impedance:
When current flows down two traces randomly, as if they were singleended, the mode of propagation is a combination of odd and even. The average impedance of each trace is affected by its proximity to the adjacent trace(s); calculated by the following equation:
Coupling Coefficient:
The coupling coefficient, Kcc, is a number that conveys the amount of electromagnetic coupling between two traces. Knowing the odd and even mode impedances, Kcc can be calculated by the following equation:
Backward Crosstalk Coefficient:
Two traces near one another will couple a portion of its own signal to the other. If we consider one trace as the aggressor, and the other as the victim, the amount of coupled noise travelling backwards on the victim’s trace, opposite to the aggressor’s direction, is called NearEnd crosstalk (NEXT) or backwards crosstalk. The amount of coupled noise, travelling in the same direction as the aggressor’s direction, is called FarEnd crosstalk (FEXT).
In stripline, there is little to no FEXT, but backwards crosstalk will saturate to a fraction of the amplitude of the aggressor’s voltage for the length of time the traces are coupled. This fraction of the aggressor’s voltage is called the backward crosstalk coupling coefficient Kb. It is equal to one half of the coupling coefficient Kcc :
Example:
A 898 mil differential pair; with 12mil core; 12 mil prepreg; Dk=4; stripline geometry; 1/2 oz copper; has the following R L G C matrix extracted from a 2D field solver:
If the two traces are driven differentially, then the differential impedance is 100 Ohms and there is 14% coupling of the two traces. On the other hand, if the traces are driven singleended then the characteristic impedance of each trace is 57 Ohms. With 9 mils of space between them, the backward crosstalk is 7%.
If you increase the spacing between traces until Zodd equals approximately Zeven, the coupling will reduce to near zero, and there will be little backward crosstalk. For this particular geometry, increasing the space to 50 mils gives Zodd = 61.5 Ohms and Zeven = 61.7 Ohms for Kb = 0.07 %. Depending on your design and your noise budget, you may be able to live with a certain amount of backwards crosstalk. The only way to know the spacing between traces to achieve the budget is to plug in the numbers.
Acknowledgment:
I would like to thank my old Nortel colleague, Dick Goulette for sharing these equations many years ago. They have served me well over the years.