Bert Simonovich's Design Notes

Innovative Signal Integrity & Backplane Solutions

Backplane High Level Design –the Secret to Success

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In a previous design note on Backplane Architecture and Design, I touched briefly on the concept of a Backplane High Level Design (HLD). In this design note, I will touch on key aspects that go into this process, using a simple fictitious system architecture as a straw-man, to demonstrate the principle.

For any new backplane design, I always recommend starting with a HLD. It helps you capture your thoughts, in an organized manner, and later provides the road map to follow for detailed design of the backplane. It also facilitates concurrent design of the rest of the system by the rest of the design team.

I like to use PowerPoint to capture the HLD information, but any other graphical based tool could be used. Later on in the design process, the drawings in the HLD document are reused in a more formal design specification document.

One of the first things I do, when coming on board a project, is capture the system architecture in a series of functional block diagrams starting from the high-level system block diagram, as shown in Figure 1. This is an example of what you might receive from the system architect at the beginning of a project.

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Each block diagram details how the respective circuit packs, or other components of the system, interconnect to one another; complete with the number of signal I/Os for that function. For example, Figure 2 below shows the system data path and system control plane block diagrams. It illustrates one possible way of how you would arrange the circuit pack blocks, as they would appear in a shelf, when viewed from the front. Whenever possible, I like to arrange the blocks this way, because it presents a consistent look and feel throughout the documentation; from mechanical views, to connector placement, and route planning.

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Preliminary Route Planning:

After all the functional block diagrams are completed, I usually go through a preliminary route planning exercise. The idea here is to gain some intuition for the final routing strategy, and to uncover any hidden issues that may surface down the road.

This is the most crucial step in any backplane design. Usually at this stage of the project, the system packaging architect is busy developing the shelf packaging concept, and is looking for feedback on connectors and card locations, so he (or she) can complete the common features drawing. The common features drawing defines all the x-y coordinates for all connectors and other mechanical parts on the backplane.

An example of a preliminary routing plan strategy diagram is shown in Figure 3. Each color represents two routing layers; for a total of 6 layers. The heavy black lines represent the high-speed serial link bundles of the data path; routed completely from SW1 and SW4 to LC1-10. The partially routed heavy red and blue lines, follow the exact same route plan as the heavy black lines, except they terminate to the respective color-coded SW cards. The beauty of this comes later, when the actual routing of the backplane takes place. Because the routing is identical, except for the source and destinations, it is a simple copy and paste exercise to replicate the routing on 5 of the 6 layers. The only editing required is at each end of the links. As you can appreciate, this is a huge time saver in completing the final layout!

imageimageWhen the preliminary route plane is complete, a pin-list summary for each circuit pack is compiled using an Excel spreadsheet. The pin-list summarizes the minimum number of pins needed per circuit pack for the function. Later on, it helps to drive the selection and number of connectors.

After completing the preliminary route planning exercise, and pin-list summary, you will gain a sense for:

  • the number of routing layers you will need
  • circuit pack connector signal grouping and partitioning
  • connector selection criteria for density
  • minimum vertical routing channel space needed between connectors
  • worst case topologies for signal integrity analysis

Backplane Connector Selection:

Large companies invest a lot of money and time to qualify a connector family. There is always strong pressure to reuse connectors from one system design to another because of cost. Qualifying a new connector is no trivial task. It takes a significant development effort to model, characterize and test the connectors. If you try to qualify a new connector, at the same time as designing a new system, you run the risk of delaying the overall program if serious issues develop along the way. Sometimes though, reusing the same connector just won’t cut it. For whatever the reason, one day you will be forced to look at other connectors.

Choosing the right connector for any new system is the most important aspect for any backplane design; regardless if it is reuse of a previous connector, or looking at new ones. The connector is the lifeblood of the backplane because it ultimately drives minimum slot pitch and circuit board height. It must be capable of supporting current and next generation high-speed signaling standards, and be robust enough to withstand multiple insertions. Factors such as pin density, pin pitch, pairs per row, overall size, skew, and crosstalk are examples to consider in this process.

Preliminary Stack-up:

In any high-speed serial link architecture, the data plane links are the most critical signals. They are the ones that usually define the total number of routing layers for the final PCB stack-up. When we include 4 layers, for redundant power distribution, to the 6 routing layers, the minimum number of layers for the backplane will be 18 layers as shown in Figure 4.

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The right half of the figure gives counter-bore details. Another name often used is back-drilling. It is a common procedure done on backplanes to minimize via stubs, which is a killer for multi-gigabit serial links.

Detailed Route Plan:

Usually, around this time in the project schedule, the mechanical architect has put together a preliminary common features drawing, showing the preliminary connector placement. We use this drawing as a template to do a more detailed routing plan analysis.

By studying the preliminary route plan and pin-list, we can come up with a strategy to organize and partition the signals within the connector, and perform a more detailed routing analysis. This process can take a few iterations before it is optimum, but eventually, we end up with a more detailed routing plan as summarized in Figure 5. Each illustration here represents two routing layers per drawing. One layer is for Tx and the other is for Rx.

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Vertical Routing Channel Analysis:

imageBefore we sign-off on connector placement and route plan though, we need to verify there is enough space between connectors for the vertical routing channels. Otherwise, this may be a deal breaker for the chosen connector; slot pitch; total number of layers; or even the whole system packaging concept. If you do not have enough space here, there will be compromises needed somewhere else to accommodate it. The worst case scenario is having to double the number of layers, or having to choose a higher cost connector.

Signal Integrity Analysis:

Finally preliminary channel simulations must be done before we can sign-off on the backplane physical architecture concept. Now that all the detailed routing analysis is complete, we can easily establish several topologies to analyze.

imageOne example of a worst case reference topology is highlighted in Figure 6. During this stage, we use Manhattan distance to estimate trace lengths.

After procuring the connector models, and developing circuit models to represent the via structures, I like to use Agilent ADS to capture and simulate the topologies. An example of the circuit topology, and simulation results are summarized in Figure 7.

Here, the topology was simulated at 10GB/s. The S-parameters are compared against the IEEE 802.3 10BaseKR spec. You would normally do this for every topology of interest. Later on, during the detailed design phase of the program, I would get 3D models of the vias built and use actual routed lengths from the backplane and circuit pack cards to confirm the design.

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Summary:

Hopefully by now, you can appreciate the backplane architecture and design can be a complex beast to tame, and get right the first time. There are many complex interrelated steps that require the due diligence and meticulous planning to be successful. We have only scratched the surface here. You can download the full white paper titled, “ Backplane Architecture High-Level Design” , from which this design note is based upon, and an example of the PowerPoint HLD document from our website at: www.lamsimenterprises.com.

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If you would like more information on our signal integrity and backplane services, or how we can help you achieve your next high-speed design challenge, email us at: info@lamsimenterprises.com.

Written by Bert Simonovich

January 31, 2011 at 8:56 pm

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