## Via Stub Termination -Brought to You by “The Stubinator”

Thick backplanes with long via stubs will cause unwanted resonances in the channel insertion loss compared to vias with little or no stub length as shown by the red and green traces in the plot of Figure 1. If these resonances occur at or near the Nyquist frequency of the bit rate, there will be little or no eye-opening left at the receiver.

Figure 1 Topology circuit model of 2 differential vias with 30 inches of PCB etch. Insertion loss plot of Long via-no stub (green); short via-long stub (red); stub terminated (blue). Received eye diagrams after optimized FFE receive equalization at 10GB/s. Modeled and simulated using Agilent ADS.

In a typical backplane application, the signal entering the via structure from the top will travel along the through portion until it reaches the junction of the internal track and stub. At that point, the signal splits with some of the signal continuing along the trace, and the rest continuing along the stub. If the signal was Arnold Schwarzenegger, he would say, *“I’ll be back!”*. Having done this gig before, he knows that when he reaches the end of the stub it’s like hitting a brick wall; there’s no where to go but back up the stub. Like Arnold, when the signal reaches the end of the stub, it reflects back up the stub. When it arrives at the same junction, a portion combines with the original signal and the rest continues back toward the source. If the round trip delay is half a cycle, the two waves are completely 180 degrees out of phase and there is cancellation of the original signal. The frequency where maximum cancellation occurs is called the ¼ wave resonant frequency, *fo*. Resonance nulls due to stubs in an insertion loss plot, like the one shown in Figure 1, occurs at the fundamental frequency *fo* and at every odd harmonic.

If you know the length of the stub (in inches) and the effective dielectric constant *Dkeff*, the resonant frequency can be predicted with the following formula:

(1)

It is common practice to reduce stub lengths in high-speed backplane designs by back-drilling the stubs as close as possible to the active internal signal layer. This is a complex and costly process involving setting individual drill depths on a per board basis. Special design features must be designed into the artwork to set correct back-drill depth. Furthermore, it is difficult to verify **ALL** back-drilled holes were drilled correctly. I know of a case where a backplane came back and one via (that they knew of) had a significantly longer stub than was specified. The problem showed up by accident when they were characterizing the channel using a VNA and saw an unexpected resonant null in the SDD21 insertion loss plot. When all was said and done, it turned out there was a glitch in the fabricator’s software controlling the back-drilling process. There is no practical way to find these faults; short of doing VNA measurements on 100% of the back-drilled holes. With hundreds of them in a typical high-speed backplane, the cost would be prohibitive. Thus we have to trust the fabrication process of the vendor(s).

If only there was a way to terminate the stub and get rid of all this back-drilling. Well there just might be a solution. After returning from last year’s DesignCon2010, I was intrigued by a paper presented by Dr. Nicholas Biunno on a new matched terminated stub technology developed by Sanmina-SCI Corporation. They call this technology MTSvia^{TM}^{ }and it allows the embedding of metal thin-film or polymer thick film resistors within a PCB stack-up during its fabrication. I like to call it *“The Stubinator”.* They developed this technology as an alternative to back-drilling. The beauty of this is you can terminate all the high-speed via stubs on just one resistive layer at the bottom of the PCB.

Of course, for this to work, we need to terminate the vias with a resistance equal to the differential via impedance to be most effective. But how do we determine the via differential impedance without going through a bunch of trial and error builds? In a DesignCon2009 paper titled, **“Practical Analysis of Backplane Vias” **I coauthored with Eric Bogatin from Bogatin Enterprises L.L.C., Sanjeev Gupta and Mike Resso from Agilent Technologies, we showed how you can model and simulate differential vias as simple twin-rod transmission line structures using simple transmission line circuit models as shown in Figure 1. You can download a copy of this award-winning paper from my web site at: **Lamsimenterprises.com** .

After determining *fo* (either by measurement of a real structure or through 3D modeling) and solving for *Dkeff* by rearranging equation (1), the differential via impedance calculated using the following equation:

(2)

Where:

*s* = the center to center spacing of the vias

*D* = Drill diameter.

Example:

The differential vias used in the model of Figure 1 has the following parameters:

*s* = 0.059 in.

*D* = 0.028 in.

*stub_length* = 0.269 in.

*Dkeff *= 6.14 by Equation (1) and *fo*=4.4GHz ;

*Zdiff *= 66 Ohms by Equation (2).

By adding a 66 Ohm resistor across the bottom of each via stub in the model, the blue trace in the plot shows the stub resonance has completely disappeared at the expense of an additional flat loss of about -10dB. The eye has opened up nicely.

This *“Stubinator”* technology looks like it could be a promising alternative to back-drilling. It resolves many of the issues and limitations highlighted above. Combined with silicon that can accommodate the additional signal loading, it may extend the life of traditional copper interconnections for next generation of Ethernet standards beyond 10GB/s.

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