Bert Simonovich's Design Notes

Innovative Signal Integrity & Backplane Solutions

Perils of Crossing Split Planes

with 2 comments

imageI recently came across this YouTube video spoof of Chuck Norris doing the spits across two aircraft wings above the clouds and it occurred to me that it was a perfect metaphor for what happens when a digital signal, propagating along a microstrip trace, crosses a split plane on a printed circuit board (PCB). If Chuck Norris and his merry band of paratroopers standing on his head were the signal, then at the split of two reference planes, we would see an impedance mismatch which manifests itself as a positive peak in the time domain reflection (TDR) plot for the duration of the discontinuity.

When discussing signal integrity (SI) issues there is always a great debate when signals on one layer of PCB crossing over split or a slot in the reference planes. On the one hand, some argue that this should never be done because of the increased risk in crosstalk and possible failure to pass electromagnetic compatibility (EMC) compliance. On the other hand, others stressed that if the width of the gap and power/ground layers in the stackup were engineered carefully, this may not be as big of an issue. So who’s right?

Well, like all things involving signal integrity, the answer is, “it depends”. And the best way to answer “it depends” is to put in the numbers.

When I decided to investigate this, I thought to myself I would just set up a couple of simple simulations to explore the issues. Of course, once you get into it, you find other scenarios to check out, then another, and before long you have amassed a lot of data. So I decided to capture it all in a white paper.

Here is a brief summary of the results.

To see just how much of an issue this is I set up a topology using Keysight ADS as shown in Figure 1. Two transmission line segments before and after the gap section (TL17, TL18) were modeled with internal 2D field solver. The gap section (SNP139) was modeled and simulated with Momentum 3D planar field solver in order to properly capture the electromagnetic effects as the signals cross the gaps. The S-parameter results were saved as touchstone format and brought back into the ADS schematic.

A 50 mil gap was chosen for worst case and a 5 mil gap was chosen for best case. As expected, when the topology was driven differentially from Port 1, the 50 mil gap results, shown in red, had a higher impedance discontinuity compared to the 5 mil gap, shown in blue.


Figure1 Keysight ADS general schematic (top) used to model and simulate a microstrip crossing a split plane. Red and blue plots (bottom) are differential impedance comparison of 50 mil vs 5 mil gaps respectively.

Figure 2 shows simulated results of incident/transmitted signals; near-end/far-end crosstalk (NEXT/FEXT) when the gap between the split planes was reduced from 50 mils (blue plots) down to 5 mils, and the thickness of dielectric from layer2 to layer 3 was reduced from 45 mils to 2 mils (red plots). Compared to the scenario with no gap (black plots) there was no appreciable increase in crosstalk.


Figure 2 Comparison of SE Incident/Transmitted voltage, NEXT/FEXT for 50 mil gap (blue) and thick dielectric under the gap vs 5 mil gap and thin dielectric under the gap (red). As expected the closer proximity of reference plane under the gap results in less incident reflection and NEXT while minimizing risetime degradation in transmitted signal and FEXT.

From a signal integrity perspective, one may conclude that crossing a split plane may be ok, with certain caveats. But in terms of passing EMC, there is still risk and doubt. For instance we see that there is still some current flow along each side of the split when we reduce the thickness between Layer 2 and 3. The combination of the split plane and diverted return current along the split creates an efficient slot antenna which will radiate noise.

Since a real design may have many interdependencies affecting the final performance, it is difficult to come up with a general rule that says if you do this, and minimize that you will be ok; and because of that, I’m still on the side of staying away from crossing split planes. When you can’t, then a more detailed analysis should be done based on the actual layout and stackup of the board; or look for other alternatives that can mitigate noise radiation; like adding extra external shielding for instance.

In the end it is what I always like to say about engineering, “it’s what you don’t know you don’t know that can ruin your day”. In today’s high-speed designs we can no longer restrict our thinking in terms of signal integrity, power integrity or EMC alone. We must consider all three and become educated or at least aware of the other disciplines. Had we only been concerned about signal integrity, without being aware of EMC we would have probably made the wrong conclusion, and in the end the final product might well have failed EMC compliance tests.

For more detail you can down load the white paper I wrote titled, “Split Planes and What Happens When Microstrip Signals Cross Them” from my web site here.


Written by Bert Simonovich

December 11, 2017 at 10:52 am

2 Responses

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  1. Interesting to see the simulation results, Bert. Sometimes you can get away if a differential pair crosses a narrow gap, but generally, any single-ended clock (or other HF, fast-edged, signal) crosses a gap in the return plane, it’s only going to increase EMI and cross-coupling of signals. To better understand the EMI ramifications, I produced this short video demo showing the measured results using near field and current probes.

    Cheers, Ken

    Kenneth Wyatt

    December 11, 2017 at 11:02 am

    • Thank you for your comment Ken. The white paper on my web site shows better the current density along the split as well as current on reference plane under the split. True it is reduced when crossing with differential signals, but there is still some current. Also when there is intra-pair skew there will be mode conversion, and the common signal return will behave like single-ended return current and radiate. Depending on how much skew will determine how much common current will go around the gap. In most PCB designs there will be skew because of: routing length mismatch; fiber weave effect; connector pin length differences; or asymmetrical placement of return vias when differential traces change layers, to name a few.

      Bert Simonovich

      December 11, 2017 at 11:25 am

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