Bert Simonovich's Design Notes

During DesignCon 2025, I had several side discussions about the findings presented in my DesignCon 2024 paper on dielectric anisotropy. A key concern raised was the discrepancy between measured results and simulations when converting the out-of-plane dielectric constant (Dkz) to in-plane Dkxy using my heuristic method. While Isola’s Tachyon 100G showed an average material anisotropy of approximately 4–6% across different glass styles, other researchers claimed that an anisotropy of 10–12% was necessary for accurate via simulation correlation.

What’s going on?

Glass-reinforced laminates dielectric properties vary depending on the orientation of the electric field within the structure. The in-plane dielectric constant (Dkxy) applies when the electric field is parallel to the fiberglass cloth, whereas the out-of-plane dielectric constant (Dkz) is when the field is perpendicular to it. Determining material anisotropy is strongly influenced by the specific test method used to extract dielectric properties and knowing the glass to resin volume ratios.

In my DesignCon 2024 paper, I defined percent anisotropy (Λ) using the following equation:

Equation 1

Efforts have been made to determine dielectric anisotropy using a quarter-wave resonant via structure. This approach relies on a via acting as a stub, which in theory, sounds like a sound method. Any quarter-wave resonant structure generates frequency nulls in the S21 insertion loss (IL) plots, as illustrated in Figure 1. The first resonant null at 13 GHz, corresponds to the fundamental frequency (f₀), with additional nulls appearing at each odd-harmonic.

Figure 1 S21 Insertion loss plot showing resonant nulls due to quarter-wave stub resonances.

Given the speed of light (c₀), the length of the stub, and the effective dielectric constant (Dkeff) surrounding the via hole structure, the resonant frequency is predicted using:

Equation 2

Adjusting Dk values within a 3-D field solver to fit measured results based on as-fabricated PCB cross-section (x-section) dimensions provides an effective anisotropy (Λeff) specific to a similar via structure utilizing the same dielectric material. However, this does not represent the true anisotropy of the bulk dielectric.

While material anisotropy contributes to Dkeff surrounding a via hole structure, several other factors must also be considered.

One key factor is resin content. During the lamination process, the prepreg layers are pressed, leading to a decrease in resin volume. Since the glass volume remains unchanged, the overall Dk of the pressed laminate increases. This should be accounted for before applying my heuristic method to calculate Dkxy.

Another important consideration is drilled hole size. The actual dimensions of the via hole structure often differ from the specifications in the CAD database, which can impact simulation accuracy.

Lastly, via barrel roughness plays a significant role. Just as foil roughness influences Dkeff and time delay (TD) in transmission lines, via barrel roughness affects the surrounding dielectric properties. Increased via barrel roughness leads to higher TD and lowers the resonant frequency. Since quarter-wave stub resonance is used to determine Λeff, an increase in Dkeff and TD results in higher Λeff values.

To illustrate the impact of manufacturing tolerances on dielectric anisotropy, we can compare an ideal via structure with an actual fabricated version. An ideal via structure is depicted in Figure 2 (A). The via barrels are perfectly smooth and antipads align symmetrically across all layers. The dielectric surrounding the via is homogeneous. Many signal integrity (SI) engineers rely solely on the bulk Dk values provided in laminate suppliers’ Dk/Df construction tables without accounting for material anisotropy. Additionally, they often assume that the final pressed dielectric thickness matches the stackup design specifications and that the specified drill size aligns with the actual drill bit dimensions.

However, in reality, an as-fabricated x-section reveals deviations from ideal conditions, as shown in Figure 2 (B). Manufacturing tolerances result in misalignment of antipads across layers, and via barrels often exhibit rough surfaces with protruding whiskers which will affect dielectric properties. Moreover, since vias pass through a mixture of resin and fiberglass cloth, using bulk Dk values may not accurately represent material anisotropy. The true dielectric constant surrounding the via depends on the glass resin volume ratios of the pressed dielectric thickness and actual drill size used.

Figure 2 Cross-section illustration example of an ideal as designed via structure (fig A) and as fabricated (fig B).

Dielectric anisotropy plays a critical role in accurate PCB design and simulation. While quarter-wave resonant structures provide a useful method for extracting Λeff values, additional factors such as resin content, via barrel roughness, and manufacturing tolerances significantly influence the effective dielectric constant (Dkeff). By accounting for these real-world effects, simulation accuracy can be improved to better correlate with measured results.

To learn more, details can be found in this white paper.