Archive for the ‘Technology’ Category
Originally published in, The PCB Design Magazine, November 2012 issue.
In normal PCB designs, crosstalk is usually an unwanted effect, due to electro-magnetic coupling, of two or more traces routed in close proximity to one another. We usually consider it to be our enemy, in any high-speed design, and go to great lengths to avoid it. So how, you may ask, can crosstalk ever be your friend?
To answer that question, I would like to start out by taking you back to the fall of 1994. This was the era of wide parallel busses running up to 33 MHz across backplanes. High-speed serial, point-point interfaces, and serdes technology, as we know and love today, was just a twinkle in some bright young engineer’s eye.
Nortel, a.k.a. Northern Telecom at the time, was looking to replace the computing module shelf of the DMS Supernode platform because it was projected to run out of steam a few years later. In order to address the issue, the system architects decided that a scalable, multi-processing, shared memory, computing architecture was needed to replace it.
My job was to develop a concept to package all these cards in a shelf, and then design a backplane to interconnect everything. It quickly became evident that a single shared bus could not support the bandwidth required for multi-processing. Nor could multiple parallel buses solve the problem, because of the lack of high-density backplane connector technology needed for all the I/O. Even if we had a suitable connector, and it could magically fit within the confines of the card slot, then the layer count of the backplane would have grown exponentially.
No, something else was needed. Fortunately, Bell Northern Research (BNR), the R&D lab of Nortel where I was working at the time, had an advanced technology group, that liked to play in the sand. I remember going to a meeting one day to see some presentations on some of the neat technology they were playing with.
One presentation they gave, was of a unique non-contact interconnect technology. I immediately saw the practical application that technology offered for our architecture, and it instantly became my friend. It allowed us to eventually invent a patented, proprietary point to multi-point interconnect solution, running at 1GB/s per pair .
The non-contact technology actually relied on controlled electro-magnetic coupling, or simply crosstalk. See Figure 1. In this simple high-level block diagram, each card on the shelf would transmit their data differentially across the backplane. As the differential pairs traversed through the connector fields of the card slots, the transmit signal was edge-coupled to an adjacent small trace, about three quarters of an inch long, connected to the respective receiver pin. After the last card slot, the transmit differential pairs switched layers where they returned back to the originating card and were terminated.
The beauty of this architecture was that each card only needed one set of transmitters to broadcast its data to all the other cards. Since each card had enough receivers to listen to the other cards, the point to multi-point interconnect achieved the equivalent of a multipoint to multipoint architecture; but without the overhead of additional pins and PCB layers. Furthermore, an effective line rate of 1GB/s was achieved using simple, inexpensive 2mm connectors; the same ones chosen for compact PCI standard.
Figure 2 is a photograph of an inner layer, double-sided core of the backplane, prior to lamination and drilling. It shows the couplers in more detail. The round pads are for the connector vias, and are used to attach the coupler traces to the connector pins. The rows of pads on the left are for one card slot, while the rows of pads on the right are for another card slot.
If we look at the two traces entering the picture from the bottom left side, we can see how they are routed through the connector field. These two traces are part of a differential pair where each are routed as single-ended traces, i.e. with no coupling to one another. As these traces approach the first row of pads, they jog down to minimum spacing to ensure close coupling to the coupler traces attached to the pads. The close spacing continues to ensure maximum coupling to the next set of pads, where the pattern stars all over again at the bottom right. This pattern repeats all the way up the photo for each differential pair.
You may be astute to notice that the bottom coupler trace connects to a pad at each end, while the mate coupler, above it does not. When two, coplanar parallel traces are in close proximity to one another, there are two types of crosstalk generated; backward or Near-End crosstalk (NEXT); and forward or Far-End crosstalk (FEXT).
As the transmit signal propagates, from left to right in the photo, the rising edge of the signal initiates NEXT at the beginning of the coupled length. The NEXT voltage saturates after a critical length equal to the risetime divided by twice the propagation delay; where the risetime is in seconds, and propagation delay is in seconds per unit length. It stays saturated for twice the time delay of the coupled length. Because of differential signalling, the NEXT voltages are of opposite phase on the respective couplers.
At the coupler pin, there is a reflection caused by the via. Since the couplers, at the far-end, are not terminated, in the characteristic impedance, and left open, any secondary reflections due to coupler via reflects back towards the receiver, again with opposite phase. When both reflections arrive back at the receiver, they will add together and add additional noise to the eye, causing inter-symbol interference, as shown by the shoulder in Figure 3(A). By leaving one end open, and shorting the other one to ground, means that any secondary noise will have the same phase, and when they arrive at the receiver, they will cancel, thereby eliminating the inter-symbol interference and increasing the eye amplitude as shown in Figure 3(B).
You will notice that the eye waveforms do not resemble the traditional eye diagram we are used to seeing. Instead we observe a typical NEXT eye, when the coupled length is short, compared to the bit time. There is also a line right in the middle.
Figure 4 can help to explain the reason. The blue waveform is the NEXT voltage, seen at the near-end of the coupler, in response to the red transmitted waveform. Notice that there are only pulses at an edge transition of the transmitted waveform. A rising edge creates a positive pulse, and a falling edge generates a negative pulse. The duration of each pulse is twice the time delay of the coupler length.
The receiver uses simple peak-detectors and latch to regenerate the signal back to the original waveform. A positive going pulse is detected by the positive peak-detector. When it crosses the positive voltage threshold (+Vth), it sets the latch output to logic high. The output remains high until a negative pulse crosses the negative threshold (-Vth), of the negative peak-detector, and resets the latch to logic low.
And that is how crosstalk can be your friend! Of course the small coupled crosstalk signal means we have to guard against CROSSTALK from other digital signals on board. But that’s nothing that mixed signal layout design rules can’t solve. ……Wait a minute! ……We both share the same enemy? …….. Who would have thought an old Proverb, “The enemy of my enemy is my friend” [sic], would apply here too?
 L. Simonovich et al, U.S. Patent 6,091,739, “HIGH SPEED DATA BUS UTILIZING POINT TO MULTI-POINT INTERCONNECT NON-CONTACT COUPLER TECHNOLOGY ACHIEVING A MULTI-POINT TO MULTI-POINT INTERCONNECT.”
 J. Williamson et al, U.S. Patent 6,016,086, “NOISE CANCELLATION MODIFICATION TO NON-CONTACT BUS.”
 Alexandre Guterman, Robert J.Zani, “Point-to-Multipoint Gigabit Backplane Design”, IEEE International Symposium on EMC, May 11-16, 2003.
Recently I came across a blog post titled, “Can Oscilloscopes Really Calculate BERs?”, written by Ransom Stephens.
I liked this article. I liked it because, as usual, Ransom likes to challenge your way of thinking and makes you go back to basics in order to understand. For example, when he debates whether BER is “bit error ratio” or “bit error rate”, it stopped me in my tracks to question if I was using the correct terminology, and why. For the record, when I started my career working on T1 line repeaters, I was taught it was “rate”. But, technically, Ransom’s assertion that it really is “ratio” is also correct.
Before you discount this and say, “In mathematics, there can be only one answer”, stay with me here, and let me try to explain where I’m coming from. According to Merriam-Webster dictionary, the definition of ratio is, “the indicated quotient of two mathematical expressions”, or “the relationship in quantity, amount, or size between two or more things: proportion”. If you take the number of bit errors and divide them by the total number of bits, then you have, by definition, a ratio, as Ransom claims. For example, if you have 1 error in 1 TBits of data, then you have a “bit error ratio” of 1E-12.
When you look up the word rate, in the same dictionary, the definition is, “reckoned value: valuation” or “a fixed ratio between two things”. In terms of BER, when it is defined as rate, the fixed ratio between two things is the number of errors over some period of time. Since a bit has a time component associated with it, you can convert the total number of bits into time by multiplying it by the bit time. For example, at 10 GB/s, the bit time is 100 ps. So 1TB of data takes 100 seconds to transmit all of the bits. If there was 1 bit error during that time, you would have a “bit error rate” of 1 error per 100 seconds.
In mission critical applications, we usually aspire to have error-free performance for the life of the product. As bit rates continue to climb, that’s an awful lot of bits. Theoretically, if you want your product to have a bit error rate of 1 error in 25 yrs, then, at 10GB/s, you would need to transmit 7.884E+18 bits;[25yrs*(60*60*24*365)sec/yr*10GB/s] to have a bit error ratio of 1.268E-19!
Bit error ratio, or bit error rate? It kind of reminds me of part of the song, “Let’s Call the Whole Thing Off”, by George and Ira Gershwin; “You like to-may-toes, and I like to-mah-toes”. At the end of the day, it’s still tomatoes. In the right context, I think both terms are equally valid. You need to be ambidextrous, so to speak, in your analysis and how you quote the number.
I recently came across some souvenir pictures and artwork of work I had done early in my career at Bell Northern Research. For those of you who are old enough to remember, it will bring back some fond memories of the technology back in the day; and for you young designers, this is how we did things back in the late ‘70s, early ‘80s.
Figure1 Northern Telecom T1C line repeater circa 1980.
Figure 1 is a T1C line repeater I helped to design early in my career circa 1980. Line repeaters were used to regenerate digital signals along a span between two central offices. There were two regenerators per line repeater, and one repeater for every 4-pairs (2Tx, 2Rx) in the cable. They were housed in apparatus cases mounted on telephone poles or pedestals every mile or so. In the city they were usually installed in manhole vaults buried underground.
T1 digital transmission was introduced in 1961 as a way to replace older analog voice frequency technology, and is still in use today. T1 data rate is 1.544 Mb/s and carries 24 channels of DS0 at 64Kb/s. As digital technology exploded through the 1970’s, it became more affordable, allowing T1 to become more popular. By the early 1980’s, the installed base was reaching capacity especially in large cities, and the industry was looking for ways to increase its bandwidth. Sound familiar? To address this issue, a new T1C standard was developed to double the bandwidth. T1C stands for T1-concatenated, and doubles the data rate to 3.152 Mb/s allowing it to carry 48 DS0 channels.
As part of the T1C project team, my primary responsibility was to package the design and lay out the printed circuit board. Because of the limited real estate available and because through-hole component technology was the only choice for PCBs, we needed to use thick-film technology for the receiver equalization circuitry.
Thick-film technology was quite popular at the time, and was the predecessor to today’s surface-mount technology on PCB’s. It allowed for the miniaturization of circuitry by screen printing conductive traces and resistive ink onto a ceramic substrate, then firing it to a high temperature. Surface mount components were limited to capacitors, SOT transistors and diodes.
At the time, Northern Telecom (NT) had their own in-house thick-film design and manufacturing facility located in Aylmer, Quebec. All of the thick-film designs used in NT’s products prior to the T1C project were single in-line packages (SIPs). Because of the height restriction, and the amount of circuitry needed to be integrated onto the substrate, SIPs were impractical, so we had to develop dual in-line manufacturing capability at the same time we were developing the product.
The final dual in-line thick-film packages are shown near the faceplate. Since the packaging of the repeater was so dense, I needed to place components under the thick-film substrates. This was all well and good until I was testing a bunch of repeaters for a field trial in California coming up in December of that year. I accidentally dropped one and it happened to land flat with component side up. After I picked it up, I had noticed both thick-film substrates were cracked. How could this be? There was enough clearance from the highest component underneath, and enough pins to support the ceramic substrate, so why did it break?
Fortunately, we had a state of the art photography lab in the building with high-speed camera equipment. So we set up a controlled experiment to capture what went wrong. We built up some test samples and dropped them while capturing it all at high-speed. Well it wasn’t a fluke. Every one that we dropped and filmed showed the same result. It turns out there was enough flex in the long right angle pins, that the momentum of the substrate caused it to hit the radial capacitor underneath, then spring back as if nothing had ever happened. Under other circumstances, this would have been cool to see, but not when the project was in jeopardy.
To make a long story shorter, I eventually came up with an elegant solution for a plastic carrier that would support the substrate and keep it at a fixed height above the board. Not only did it solve the reliability problem, but it also solved the shipping and handling protective packaging issue for the thick-film assembly at the same time.
Figure 2 shows the actual artwork for the repeater’s PCB. Back then, all our boards were double-sided and all layouts were done by hand; first in colored pencil, then using red/blue tape and pads on mylar film for final artwork. Red usually represented the solder (bottom) side of the board and blue was the component (top) side. The artwork was usually done at 2:1 scale and later photo reduced to produce the 1:1 photo-masks. Red and blue filters were used during the photo reduction process to separate individual layer masks. A red filter generated the component side and blue filter produced the solder side photo-masks respectively. All drilled holes were manually specified on a separate drawing with various symbols for the drill sizes. Line widths and space were typically 25 mils and components were on 100 mil pitch. All components were through-hole mounted on one side only and passed through a solder wave.
Figure 2 Example of double-sided artwork for the T1C line repeater. Red is solder side, blue is component side.
The T1C line repeater project from its inception, to designing, testing, building 50 prototypes by hand and completing a successful field trial in California, took about 6 months; all with a team of three plus our manager, and mechanical design support staff. Finding these pictures truly was a blast from the past. Looking back, I sometimes wonder if we could have done it any faster with today’s modern technology, CAD tools and outsourcing business model. What do you think?
Born in Hamilton, Ontario, Canada, Bert graduated in 1976 from Mohawk College of Applied Arts and Technology in Hamilton, Ontario, Canada as an Electronic Engineering Technologist. Over a 32 year career at Bell Northern Research and Nortel, he helped pioneer several advanced technology solutions into products and has held a variety of R&D positions, eventually specializing in high-speed signal integrity and backplane design. He is the founder of Lamsim Enterprises Inc. providing innovative signal integrity and backplane solutions. He is currently engaged in signal integrity, characterization and modeling of high-speed serial links associated with backplane interconnects. With three patent applications and two patent grants to his name, he has also (co)authored several publications, including an award-winning DesignCon2009 paper related to PCB via modeling. His current research interests include signal integrity, high-speed characterization, and modeling of high-speed serial links associated with backplane interconnects. To contact Bert, email him at: email@example.com