Archive for the ‘Signal Integrity’ Category
Fiber Weave Effect Timing Skew
Fiber weave effect timing skew is becoming more of an issue as bit rates continue to soar upwards. For signaling rates of 5GB/s and beyond, it can actually ruin your day. For example, the figure on the left shows a 5GB/s received eye is totally closed due to 12.7 inches of fiber weave effect. It was modeled and simulated using Agilent ADS software.
So what is fiber weave effect anyways and why should we be concerned about it? Well, it’s the term commonly used when we want to describe the situation where a fiberglass reinforced dielectric substrate causes timing skew between two or more transmission lines of the same length. Since the dielectric material used in the PCB fabrication process is made up of fiberglass yarns woven into cloth and impregnated with epoxy resin, it becomes non-homogeneous.
The speed at which a signal propagates along a transmission line depends on the surrounding material’s relative permittivity (er), or dielectric constant (Dk). The higher the Dk, the slower the signal propagates along the transmission line. When one trace happens to line up over a bundle of glass yarns for a portion of its length, as illustrated by the top trace in the figure on the left, the propagation delay is different compared to another trace of the same length which lines up over mostly resin. This is known as timing or phase skew and is due to the delta Dk surrounding the respective traces.
Fiber weave effect is a statistical problem. It is not uncommon for PCB designs to have long parallel lengths of track routing without any bends or jogs. This is particularly true in large passive backplane designs. Because the fiber weave pattern tends to run parallel to the x-y axis, any traces running the same way will eventually encounter a situation of worst case timing skew if you build enough boards. This was demonstrated by Intel after compiling more than 58,000 TDR and TDT measurements over two years. In 2007, Jeff Loyer et al presented a DesignCon paper “Fiber Weave Effect: Practical Impact Analysis and Mitigation Strategies” where they published the data and proposed techniques to mitigate the effect of fiber weave skew. They showed statistically it is possible to have a worst case timing skew of approximately 16ps per inch representing a delta Dk of approximately 0.8.
In high speed differential signalling this is an issue because any timing skew between the positive (D+) and negative (D-) data converts some of the differential signal into a common signal component. Ultimately this results in eye closure at the receiver and contributes to EMI radiation.
You can calculate the timing skew using the following equation:
Where:
tskew = total timing skew due to fiber weave effect length (sec)
Dkmax= dielectric constant of material predominated by fiberglass.
Dkmin= dielectric constant of material predominated by resin.
c = speed of light = 2.998E+8 m/s (1.18E+10 in/s)
A practical methodology you can use to estimate the minimum and maximum values of Dk is by studying the material properties available from PCB laminate suppliers. Consider two extreme styles of fiberglass cloths used in modern PCB laminate construction as illustrated by the figure on the left. The loose weave pattern of 106 has the highest resin content of all the most popular weaves, while the tight weave pattern of 7628 has the lowest. Therefore, you could use the specified values of Dk for cloth styles 106 and 7628 to get Dkmin and Dkmax respectively. Once you have these and apply a tolerance, you can estimate the tskew .
Example:
Assume Fr4 material; one inch of fiber weave effect; Dk106= 3.34(+/-0.05) and Dk7628= 3.97(+/-0.05), then timing skew is calculated as follows:
Modern serial link interfaces use differential signalling on a pair of transmission lines of equal length for interconnect between two points. In a DesignCon 2007 paper, “Losses Induced by Asymmetry in Differential Transmission Lines” by Gustavo Blando et al, they showed how intra-pair timing skew between the positive (D+) and negative (D-) data caused an increase in the differential insertion loss profile due to timing induced resonances. These resonances appear as dips in the differential insertion loss profiles of the channel as shown in the following figure:
This figure presents the results from an ADS simulation I did recently of a PCIe Gen2 channel running at 5GT/s. The eye diagrams are at the receiver after approximately 30” of track length chip to chip. The channel model was parameterized to allow for adjusting the fiber weave effect length as required.
As you can see, when the length of the fiber weave effect induced skew increases from 0 to 12.7 inches, the fundamental frequency nulls in the differential insertion loss plots decrease. These nulls occur at the fundamental frequency (fo) and every odd harmonic.
Also, the eye shows some degradation at 5.6 inches of fiber weave effect and starts to distort significantly after 7.8 inches. At 12.7 inches, fo equals the Nyquist frequency of the data rate (in this case 2.5GHz) and the eye is totally closed.
You can predict the resonant frequency ahead of time and use it to gain some intuition before you simulate and validate the results. If you know the total intra-pair timing skew, fo is calculated using the following equation:
Where:
fo = resonant frequency
tskew = total intra-pair timing skew
Example:
Using tskew = 16 ps/in we calculated above and using 12.7 inches from the last simulation results in the figure above, the fundamental resonant frequency null is:
You can find more details of this phenomena plus a novel way to model and simulate it from a recent White Paper I published titled, “Practical Fiber Weave Effect Modeling”. It, along with other papers, is found on my website at LamsimEnterprises.com.
Characteristic Impedance and Propagation Delay of a Transmission Line
A transmission line is any two conductors with some length separated by a dielectric material. One conductor is the signal path and the other is its return path. As the leading edge of a signal propagates down a transmission line, the electric field strength between two oppositely charged conductors creates a voltage between them. Likewise, the current passing through them produces a corresponding magnetic field. A uniform transmission line terminated in its characteristic impedance will have a constant ratio of voltage to current at a given frequency at every point on the line.
To ensure good signal integrity, it is important to maintain a constant impedance at every point along the way. Any change in the characteristic impedance results in reflections which manifests itself into noise on the signal. In any printed circuit board design, it is almost impossible to maintain a constant impedance of the transmission path from transmitter to receiver. Things like vias, non-homogeneous dielectric, thickness variation and other component paracitics all contribute to impedance mismatch. In high-speed designs, uncontrolled impedance can significantly reduce voltage and timing margins to the point where the circuit may be marginal or worst inoperable. The best you can do is to try to minimize each impedance discontinuity when they occur.
Lossy Transmission Line Circuit Model:
The circuit model for a lossy transmission line assumes an infinite series of two-port components as illustrated. The series resistor represents the distributed resistance with the units as ohms (Ω) per unit length. The series inductor represents the distributed loop inductance with the units as henries (H) per unit length. Separating the two conductors is the dielectric material represented by conductance G in siemens (S) per unit length. Finally, the shunt capacitor represents the distributed capacitance between the two conductors with units of farads (F) per unit length.
A 2D field solver is the best tool to extract these parameters from a given transmission line geometry. It assumes, however, that the same geometry is maintained through its entire length. Many spice like simulators need these RLGC parameters for their lossy transmission line models.
Given the RLGC parameters, the characteristic impedance can be calculated by the following equation:
Where:
Zo is the intrinsic characteristic impedance of the transmission line.
Ro is the intrinsic series resistance per unit length of the transmission line.
Lo is the intrinsic loop inductance per unit length of the transmission line.
Go is the intrinsic conductance per unit length of the transmission line.
Co is the intrinsic capacitance per unit length of the transmission line.
Lossless Transmission Line:
For the lossless transmission line model, Ro and Go are assumed to be zero. As a result, the equation reduces to simply:
Propagation Delay:
Propagation delay, as it relates to transmission lines, is the length of time it takes for the signal to propagate through the conductor from on point to another. Given the inductance and capacitance per unit length, the propagation delay of the signal can be determined by the following equation:
Where:
tpd is the propagation delay in seconds/unit length.
Lo is the intrinsic loop inductance per unit length of the transmission line.
Co is the intrinsic capacitance per unit length of the transmission line.
Relative permittivity is also known as relative dielectric constant . The number is a measure of an insulator material’s ability to transmit an electric field compared to a vacuum, which is 1. For simplicity, it is usually referred to it as just the dielectric constant, Dk.
Electromagnetic signals propagate at the speed of light through free space. When these signals are surrounded by insulating material other than air or a vacuum, the propagation delay increases proportionally. You can determine the propagation delay with a known Dk by the following equation:
Where:
Dk is the dielectric constant of the material.
c is the speed of light in free space = 2.998E8 m/s or 1.180E10 in/s.
Driver’s Output Impedance From IBIS
In a recent post from the SI-list I subscribe to asks a question; “How do you find the driver impedance information from the IBIS file?” Most of the time we want this information so that we can explore mitigation techniques to control reflections caused by impedance discontinuities of the transmission path.
IBIS stands for Input/Output Buffer Information Specification and is controlled by the IBIS Open Forum organization. It is a device modeling technique used in simulation to provide a simple table based; non-proprietary buffer model derived from a real semi-conductor device. IBIS models can be used to characterize I/V output curves, rising/falling waveforms and pin parasitics of the device packaging.
When a driver’s output impedance is not matched to the transmission line characteristic impedance (Zo), there are reflections which causes ringing at the receiver as shown by the red waveform in the figure on the left. Terminating the transmission line at the receiver using a pull-up or pull-down resistor to match Zo is one way to cure this. Although this approach works fine, it is not the preferred method because the resistor value would be in the 45-70 Ohm range to match the typical single-ended transmission line impedances found in modern PCB designs. Such a low resistance causes additional loading on the driver resulting in higher power dissipation.
A better method is to add a series resistor at the end of the driver to make up the difference in impedance. For example if the buffer’s output impedance is 20 Ohms driving a 50 Ohm transmission line, you would add a 30 Ohm resistor in series with the output.
Because the buffer is a semi-conductor, it’s output impedance could vary based on rising/falling edge transitions, manufacturing process (slow, typical, fast), and the load it is driving. Since IBIS models are ASCII based, you can simply use your favourite text editor to view and quickly estimate the output impedance when driving 50 Ohms using two of the four V-T waveform tables.
Here’s how:
The output impedance is often different for the rising edge compared to the falling edge. To determine the output impedance of a low to high transition you would use the pull-down [Rising Waveform]; R_fixture = 50; V_fixture = 0.000 table. A sample of what this table looks like is shown below:
[Rising Waveform]
R_fixture = 50.0000
V_fixture = 0.000
| time V(typ) V(min) V(max)
|
0.000S 0.000V 0.000V 0.000V
0.2000nS 0.000V 0.000V -1.7835uV
0.4000nS -1.1143mV -8.0018uV -7.8340mV
0.6000nS 0.1336V -5.4161mV 0.9354V
0.8000nS 1.1220V -12.5300mV 2.3940V
* * * *
* * * *
9.6000nS 2.5680V 2.1880V 2.7880V
9.8000nS 2.5680V 2.1880V 2.7880V
10.0000nS 2.5680V 2.1880V 2.7880V
The first three lines of the table tells us that the rising waveform has a 50 Ohm resistor connected to the buffer output and pulled-down to 0V as shown by the equivalent circuit on the right.
The combination of the output impedance (Zs) and the 50 Ohm load forms a simple voltage divider network described by the following equation:
Where:
VO = Voltage at the output pin of the buffer
VDC = Supply voltage
Zs = Buffer impedance
Solving for Zs, we end up with the following equation:
![clip_image002[5]](http://bertsimonovich.files.wordpress.com/2010/12/clip_image0025.gif "clip_image002[5]"){kind=small}
If VDC is 3.3V, and VO is 2.568V using the typical voltage at 10 nS from the V-T table above, the output impedance for the rising edge into 50 Ohms is equal to 14.25 Ohms.
To determine the output impedance of a high to low transition you would use the pull-up [Falling Waveform]; table similar to the following example:
[Falling Waveform]
R_fixture = 50.0000
V_fixture = 3.3000
V_fixture_min = 3.0000
V_fixture_max = 3.4500
| time V(typ) V(min) V(max)
|
0.000S 3.3000V 3.0000V 3.4500V
0.2000nS 3.3000V 3.0000V 3.4500V
0.4000nS 3.2995V 3.0000V 3.4500V
* * * *
* * * *
9.4000nS 0.5598V 0.6824V 0.4812V
9.6000nS 0.5598V 0.6824V 0.4812V
9.8000nS 0.5598V 0.6824V 0.4812V
10.0000nS 0.5598V 0.6824V 0.4812V
This time, the table tells us the falling waveform has a 50 Ohm resistor connected to the buffer output and pulled-up to V_fixture as shown by the equivalent circuit on the right.
The output impedance is calculated by the following equation:
![clip_image002[11]](http://bertsimonovich.files.wordpress.com/2010/12/clip_image00211.gif "clip_image002[11]"){kind=small}
Where:
VO = Output voltage when the driver is sinking current
V_Fix = Voltage of the test fixture
Using typical values for V_Fix = 3.3V and VO = 0.5598V at 10nS, Zs = 10.21 Ohms.
As you can see for this particular IBIS model, the output impedance varies depending on the edge transition. For a rising edge, the output impedance is 14.25 ohms and 10.21 Ohms for a falling edge when using the typical values. The impedances will also vary under min/max conditions.
If your load is something other than 50 Ohms, you should NOT rely on this simple method for signoff. Instead you should simulate it if the design is critical. Sometimes though we need a quick ball park number to gain some insight of a particular design or to give us some intuition of what to expect from simulation.
You can validate this methodology using any Spice-like simulator which supports IBIS models. There are many to choose from like HSPICE, Hyperlynx, Cadence Spectraquest, Ansoft Designer from ANSYS and Agilent ADS to name a few. Chances are if you work for a large company, you already have access to some of these tools. If you are a student or someone just starting to learn about signal integrity, there is an alternative available. Fortunately, Spectrum Software offers Micro-cap 10; a free trial of its SPICE software you can use. Although it is limited to the number of components, nodes and performance, it is more than adequate for this and other signal integrity studies. Personally, I found it quite easy to pick up and get productive fairly quickly.
For the purpose of the analysis, the output buffer and it’s impedance (Zs) can be simplified as shown by the schematic on the left. When the buffer drives a 50 Ohm transmission line, you typically see the waveforms at the driver’s output (blue) and receiver’s input (red) as shown in the following plot:
The initial step in the rising and falling edges of the blue waveform (Vs) is due to the voltage divider action between Zs and Zo. Let us call these steps as a “porch” and designate the voltages as Vp_rise/Vp_fall for the rising and falling porches respectively.
Vp_rise is equivalent to the maximum voltage of Rising Waveform table found in the IBIS model. Vp_fall is equivalent to the minimum voltage of Falling Waveform table.
The analysis is best summarized by the following Figure:
A common circuit topology was built using the schematic editor. The respective greyed-out devices are disabled during simulation making it a convenient way of switching them in and out for the different topologies. R1 is reserved for the series termination resistor and is set to 0 Ohms initially. Once the output impedance is determined, R1 is set to the difference between Zo and the output impedance Zs.
The top topology simulates the Pull-up test fixture and used to verify the Falling Waveform table in the IBIS model. Similarly, the center topology simulates the Pull-down test fixture for the Rising Waveform table. The bottom topology has the output buffer driving a real world 50 Ohm transmission line.
The results of the simulations are shown adjacent to their respective topologies. Referring to the last case, Vp_rise=2.555V and Vp_fall=3.3V-2.726V=0.574V . As you can see there is excellent correlation when you compare them against the IBIS model’s voltages of 2.568V and 0.5598V respectively. Using the simulated voltages and solving for Zs, we get 14.58 Ohms and 10.53 Ohms respectively.
Because Zs is different for the rise time and fall time, you can never perfectly compensate for the impedance mismatch. The best approach is sometimes to take the average value between the two. In this case Zs_avg=12.56 Ohms.
Once Zs is known, the series resistor can be calculated as follows:
![clip_image002[1]](http://bertsimonovich.files.wordpress.com/2010/12/clip_image0021.gif "clip_image002[1]"){kind=small}
When 38 ohms is substituted in the transmission line topology, the waveform is clean with minimum reflections as shown by the following results:
In conclusion, the methodology presented here is a simple and effective way to predict the driver’s output impedance from an IBIS model. Try it next time someone asks you the question, “How do you find the driver impedance information from the IBIS file?”
