Archive for January 2011
In a previous design note on Backplane Architecture and Design, I touched briefly on the concept of a Backplane High Level Design (HLD). In this design note, I will touch on key aspects that go into this process, using a simple fictitious system architecture as a straw-man, to demonstrate the principle.
For any new backplane design, I always recommend starting with a HLD. It helps you capture your thoughts, in an organized manner, and later provides the road map to follow for detailed design of the backplane. It also facilitates concurrent design of the rest of the system by the rest of the design team.
I like to use PowerPoint to capture the HLD information, but any other graphical based tool could be used. Later on in the design process, the drawings in the HLD document are reused in a more formal design specification document.
One of the first things I do, when coming on board a project, is capture the system architecture in a series of functional block diagrams starting from the high-level system block diagram, as shown in Figure 1. This is an example of what you might receive from the system architect at the beginning of a project.
Each block diagram details how the respective circuit packs, or other components of the system, interconnect to one another; complete with the number of signal I/Os for that function. For example, Figure 2 below shows the system data path and system control plane block diagrams. It illustrates one possible way of how you would arrange the circuit pack blocks, as they would appear in a shelf, when viewed from the front. Whenever possible, I like to arrange the blocks this way, because it presents a consistent look and feel throughout the documentation; from mechanical views, to connector placement, and route planning.
Preliminary Route Planning:
After all the functional block diagrams are completed, I usually go through a preliminary route planning exercise. The idea here is to gain some intuition for the final routing strategy, and to uncover any hidden issues that may surface down the road.
This is the most crucial step in any backplane design. Usually at this stage of the project, the system packaging architect is busy developing the shelf packaging concept, and is looking for feedback on connectors and card locations, so he (or she) can complete the common features drawing. The common features drawing defines all the x-y coordinates for all connectors and other mechanical parts on the backplane.
An example of a preliminary routing plan strategy diagram is shown in Figure 3. Each color represents two routing layers; for a total of 6 layers. The heavy black lines represent the high-speed serial link bundles of the data path; routed completely from SW1 and SW4 to LC1-10. The partially routed heavy red and blue lines, follow the exact same route plan as the heavy black lines, except they terminate to the respective color-coded SW cards. The beauty of this comes later, when the actual routing of the backplane takes place. Because the routing is identical, except for the source and destinations, it is a simple copy and paste exercise to replicate the routing on 5 of the 6 layers. The only editing required is at each end of the links. As you can appreciate, this is a huge time saver in completing the final layout!
When the preliminary route plane is complete, a pin-list summary for each circuit pack is compiled using an Excel spreadsheet. The pin-list summarizes the minimum number of pins needed per circuit pack for the function. Later on, it helps to drive the selection and number of connectors.
After completing the preliminary route planning exercise, and pin-list summary, you will gain a sense for:
the number of routing layers you will need
circuit pack connector signal grouping and partitioning
connector selection criteria for density
minimum vertical routing channel space needed between connectors
worst case topologies for signal integrity analysis
Backplane Connector Selection:
Large companies invest a lot of money and time to qualify a connector family. There is always strong pressure to reuse connectors from one system design to another because of cost. Qualifying a new connector is no trivial task. It takes a significant development effort to model, characterize and test the connectors. If you try to qualify a new connector, at the same time as designing a new system, you run the risk of delaying the overall program if serious issues develop along the way. Sometimes though, reusing the same connector just won’t cut it. For whatever the reason, one day you will be forced to look at other connectors.
Choosing the right connector for any new system is the most important aspect for any backplane design; regardless if it is reuse of a previous connector, or looking at new ones. The connector is the lifeblood of the backplane because it ultimately drives minimum slot pitch and circuit board height. It must be capable of supporting current and next generation high-speed signaling standards, and be robust enough to withstand multiple insertions. Factors such as pin density, pin pitch, pairs per row, overall size, skew, and crosstalk are examples to consider in this process.
In any high-speed serial link architecture, the data plane links are the most critical signals. They are the ones that usually define the total number of routing layers for the final PCB stack-up. When we include 4 layers, for redundant power distribution, to the 6 routing layers, the minimum number of layers for the backplane will be 18 layers as shown in Figure 4.
The right half of the figure gives counter-bore details. Another name often used is back-drilling. It is a common procedure done on backplanes to minimize via stubs, which is a killer for multi-gigabit serial links.
Detailed Route Plan:
Usually, around this time in the project schedule, the mechanical architect has put together a preliminary common features drawing, showing the preliminary connector placement. We use this drawing as a template to do a more detailed routing plan analysis.
By studying the preliminary route plan and pin-list, we can come up with a strategy to organize and partition the signals within the connector, and perform a more detailed routing analysis. This process can take a few iterations before it is optimum, but eventually, we end up with a more detailed routing plan as summarized in Figure 5. Each illustration here represents two routing layers per drawing. One layer is for Tx and the other is for Rx.
Vertical Routing Channel Analysis:
Before we sign-off on connector placement and route plan though, we need to verify there is enough space between connectors for the vertical routing channels. Otherwise, this may be a deal breaker for the chosen connector; slot pitch; total number of layers; or even the whole system packaging concept. If you do not have enough space here, there will be compromises needed somewhere else to accommodate it. The worst case scenario is having to double the number of layers, or having to choose a higher cost connector.
Signal Integrity Analysis:
Finally preliminary channel simulations must be done before we can sign-off on the backplane physical architecture concept. Now that all the detailed routing analysis is complete, we can easily establish several topologies to analyze.
After procuring the connector models, and developing circuit models to represent the via structures, I like to use Agilent ADS to capture and simulate the topologies. An example of the circuit topology, and simulation results are summarized in Figure 7.
Here, the topology was simulated at 10GB/s. The S-parameters are compared against the IEEE 802.3 10BaseKR spec. You would normally do this for every topology of interest. Later on, during the detailed design phase of the program, I would get 3D models of the vias built and use actual routed lengths from the backplane and circuit pack cards to confirm the design.
Hopefully by now, you can appreciate the backplane architecture and design can be a complex beast to tame, and get right the first time. There are many complex interrelated steps that require the due diligence and meticulous planning to be successful. We have only scratched the surface here. You can download the full white paper titled, “ Backplane Architecture High-Level Design” , from which this design note is based upon, and an example of the PowerPoint HLD document from our website at: www.lamsimenterprises.com.
If you would like more information on our signal integrity and backplane services, or how we can help you achieve your next high-speed design challenge, email us at: firstname.lastname@example.org.
Thick backplanes with long via stubs will cause unwanted resonances in the channel insertion loss compared to vias with little or no stub length as shown by the red and green traces in the plot of Figure 1. If these resonances occur at or near the Nyquist frequency of the bit rate, there will be little or no eye-opening left at the receiver.
Figure 1 Topology circuit model of 2 differential vias with 30 inches of PCB etch. Insertion loss plot of Long via-no stub (green); short via-long stub (red); stub terminated (blue). Received eye diagrams after optimized FFE receive equalization at 10GB/s. Modeled and simulated using Agilent ADS.
In a typical backplane application, the signal entering the via structure from the top will travel along the through portion until it reaches the junction of the internal track and stub. At that point, the signal splits with some of the signal continuing along the trace, and the rest continuing along the stub. If the signal was Arnold Schwarzenegger, he would say, “I’ll be back!”. Having done this gig before, he knows that when he reaches the end of the stub it’s like hitting a brick wall; there’s no where to go but back up the stub. Like Arnold, when the signal reaches the end of the stub, it reflects back up the stub. When it arrives at the same junction, a portion combines with the original signal and the rest continues back toward the source. If the round trip delay is half a cycle, the two waves are completely 180 degrees out of phase and there is cancellation of the original signal. The frequency where maximum cancellation occurs is called the ¼ wave resonant frequency, fo. Resonance nulls due to stubs in an insertion loss plot, like the one shown in Figure 1, occurs at the fundamental frequency fo and at every odd harmonic.
If you know the length of the stub (in inches) and the effective dielectric constant Dkeff, the resonant frequency can be predicted with the following formula:
It is common practice to reduce stub lengths in high-speed backplane designs by back-drilling the stubs as close as possible to the active internal signal layer. This is a complex and costly process involving setting individual drill depths on a per board basis. Special design features must be designed into the artwork to set correct back-drill depth. Furthermore, it is difficult to verify ALL back-drilled holes were drilled correctly. I know of a case where a backplane came back and one via (that they knew of) had a significantly longer stub than was specified. The problem showed up by accident when they were characterizing the channel using a VNA and saw an unexpected resonant null in the SDD21 insertion loss plot. When all was said and done, it turned out there was a glitch in the fabricator’s software controlling the back-drilling process. There is no practical way to find these faults; short of doing VNA measurements on 100% of the back-drilled holes. With hundreds of them in a typical high-speed backplane, the cost would be prohibitive. Thus we have to trust the fabrication process of the vendor(s).
If only there was a way to terminate the stub and get rid of all this back-drilling. Well there just might be a solution. After returning from last year’s DesignCon2010, I was intrigued by a paper presented by Dr. Nicholas Biunno on a new matched terminated stub technology developed by Sanmina-SCI Corporation. They call this technology MTSviaTM and it allows the embedding of metal thin-film or polymer thick film resistors within a PCB stack-up during its fabrication. I like to call it “The Stubinator”. They developed this technology as an alternative to back-drilling. The beauty of this is you can terminate all the high-speed via stubs on just one resistive layer at the bottom of the PCB.
Of course, for this to work, we need to terminate the vias with a resistance equal to the differential via impedance to be most effective. But how do we determine the via differential impedance without going through a bunch of trial and error builds? In a DesignCon2009 paper titled, “Practical Analysis of Backplane Vias” I coauthored with Eric Bogatin from Bogatin Enterprises L.L.C., Sanjeev Gupta and Mike Resso from Agilent Technologies, we showed how you can model and simulate differential vias as simple twin-rod transmission line structures using simple transmission line circuit models as shown in Figure 1. You can download a copy of this award-winning paper from my web site at: Lamsimenterprises.com .
After determining fo (either by measurement of a real structure or through 3D modeling) and solving for Dkeff by rearranging equation (1), the differential via impedance calculated using the following equation:
s = the center to center spacing of the vias
D = Drill diameter.
The differential vias used in the model of Figure 1 has the following parameters:
s = 0.059 in.
D = 0.028 in.
stub_length = 0.269 in.
Dkeff = 6.14 by Equation (1) and fo=4.4GHz ;
Zdiff = 66 Ohms by Equation (2).
By adding a 66 Ohm resistor across the bottom of each via stub in the model, the blue trace in the plot shows the stub resonance has completely disappeared at the expense of an additional flat loss of about -10dB. The eye has opened up nicely.
This “Stubinator” technology looks like it could be a promising alternative to back-drilling. It resolves many of the issues and limitations highlighted above. Combined with silicon that can accommodate the additional signal loading, it may extend the life of traditional copper interconnections for next generation of Ethernet standards beyond 10GB/s.
According to Wiktionary, an Architect is: “A person who plans, devises or contrives the achievement of a desired result.” Because the backplane is the key component in any system architecture, the sooner you consider the backplane’s physical architecture near the beginning of a project, the more successful the project will be. If you think about it in the same way as designing a building, you would never consider building it without first engaging a building architect to plan and oversee the detailed design. Likewise, the backplane architect plans and oversees the physical backplane design before any layout is ever started. He or she works closely with a system-packaging engineer to satisfy the system requirements before any concept becomes final. Sometimes the original system architecture needs revisions due to physical limitations the backplane imposes. This can only be established with due diligence and planning during the high-level design stage.
Unlike other circuit pack designs used in the system, the backplane is much like the keel of a ship of which the rest of the ship’s construction depends on for support and structural integrity throughout its lifetime. Backplanes need to be right the first time so that circuit packs can interoperate together day one and be capable of supporting future system upgrades as technology advances. Once the system has been deployed into the field, it is next to impossible to change the backplane to correct any deficiencies or to upgrade for performance like you can by redesigning the plug-in circuit packs.
The seasoned backplane architect is a unique individual usually tasked to turn the system architect’s ideas and dreams, like the system block diagram example shown to the left, into reality. An often-misunderstood profession, backplane architects wear many hats to accomplish their goals. Often they must juggle the design requirements from many disciplines and decide on the best trade-offs for the final design. They must converse fluently with system architects, mechanical designers, circuit pack designers, connector suppliers, PCB layout designers, ASIC/FPGA and software engineers. They must be organized and meticulous in their documentation and design. But, most importantly, they must have a sound knowledge of mechanical, PCB layout/fabrication, signal integrity, power and EMC issues.
The greatest danger in leaving the backplane design as an afterthought is the connector selection and pin-out definition. If left to system packaging engineers and board designers to define, they may not be optimum for either performance or system cost. Many times system architects and packaging engineers will merely take the total number of signals and choose a connector with the highest pin density per inch without considering PCB routing or signal integrity implications. Inefficient routing of the traces leads to an increase in layer count and results in a thicker board. Thicker boards leads to higher hole aspect ratios and longer vias affecting high speed performance. Additional layer count impacts common equipment cost.
The high-level design stage is where the physical backplane architecture starts to take shape. It uncovers potential layout routing issues and gives you the confidence the design will work the first time. The importance of this stage cannot be overstated. It primarily drives these key activities:
Sanitizes the system architecture.
Defines the final selection of appropriate connectors.
Defines the connector signal partitioning and circuit pack pin-outs.
Provides the routing plan and design rules for layout.
Defines the net topologies for signal integrity analysis and link budgeting.
Facilitates the mechanical design of shelf and system packaging.
Defines the minimum slot pitch for optimum routing channels.
Facilitates early circuit pack floor planning and final card size.
Facilitates ASIC and FPGA pin selection for optimum routing to backplane connectors.
Estimates PCB layer count and board thickness.
Establishes an estimate for system cost of goods to support the business case.
Proper route planning and connector pin-out definition is vital for optimum performance. When done correctly, the final schematic capture and actual PCB layout will flow smoothly with no surprises. As an example, the left half of the figure (labeled HLD Plan) shows a sample of an inner layer high-level design route plan I did using Framemaker as the drawing tool on a design before any schematic was ever captured or pin-outs defined. Everything was planned from the number of layers to how the tracks needed to break out of the connector fields. The right half of the figure is the actual layout done in Cadence Allegro showing the inner layer routing of the artwork. The due diligence done in the high-level design stage made the actual layout fairly trivial. If you forgo this step, the worst-case scenario is the project will need to be reset to redesign shelf mechanicals or redefine card pin-outs causing delay in meeting time to market objectives and ballooning R&D costs. It’s a classic case of pay me now or pay me later.
At Lamsim Enterprises Inc., we can help you with these or any other design challenges you may have by providing innovative signal integrity and backplane solutions. Visit us at our web site at: lamsimenterprises.com .
Backplane Architecture Terms and Definitions
The following is a list of common terms and definitions associated with system architecture and backplane design:
A backplane is a multi-layered printed circuit board assembly serving as the backbone of a system. Its purpose is to interconnect several printed circuit board assemblies called circuit packs or cards using plug in connectors to form a complete system. These cards plug into one side of the shelf assembly. Usually in mission critical system applications like central office telco or data centers, the backplane is passive meaning it does not contain active semiconductor devices permanently attached as part of the final assembly. Usually only connectors are the only components, but occasionally capacitors and resistors are also used. Active backplanes on the other hand, contains active components and often found in enterprise or consumer grade applications
A midplane is similar to a backplane in function except that the circuit packs plug into both sides of the shelf assembly. In these systems, cards with I/O cabling from the faceplate plug into one side of the shelf, while non-I/O circuit pack plug in on the other side. Some midplane architectures have the front card plugged in orthogonally to the rear cards for high speed applications.
Parallel Bus Topologies
Parallel bus topologies carry data words in parallel on multiple traces from card-slot to card-slot across a backplane or from chip to chip on a circuit pack. Up until the late 1990’s, most system architectures used this form of interconnect. Due to signal integrity and timing issues associated with some parallel bus architectures with 10 to 16 card slots, the speed of the bus was limited to 25-66 MHz Two popular industry standard systems still using parallel busses today are CompactPCI and VMEbus.
The main issue with a parallel bus topology is fault tolerance where a single point of failure on the bus can bring down the entire system. Mission critical systems often had to employ redundant busses to guard against single point failures.
As performance demand increased, newer high speed system architectures were designed using serial technology in a point-to-point or point-to-multi-point switched fabric topologies.
Switched fabric, or just plain fabric, is the term most popular used in telecommunications and high-speed networks, including InfiniBand, Fiber Channel, PCIe, ATCA and other proprietary fabric based architectures. In these architectures, all data passes through the fabric before continuing to its destination. It offers better total throughput than parallel busses because traffic is spread across multiple physical links. It manages and controls all functions of the network and acts as a repeater for the data flow.
Single Star Topology
Star topologies are one of the most common high-speed serial topologies used in networks today. The advantage is it reduces the chance of network failure by connecting all of the systems to a central node. A failure of a link from any peripheral node to the central node results in the isolation of that peripheral node from all others. As a result, the rest of the systems remain unaffected.
In its simplest form, a single star topology consists of one central hub node interconnected point-to-point to other peripheral nodes resembling a spoke wheel or star configuration. When implemented in a backplane, the central node is usually the switched fabric card and the peripheral nodes are line cards. The fabric card switches messages between the other line cards in the network. The line cards usually have faceplate I/O connectors to connect to other shelves in a network.
The main disadvantage with a single star topology is high dependence of the system on the functioning of the central fabric. Failure of the fabric card can bring down the entire system. Because of this, mission critical systems employ two fabric cards for redundancy in a dual star topology configuration.
Dual Star/Multi-star Topology
The dual star or multi-star topology is similar to the star network topology except it has two or more central hub nodes interconnected point-to-point to other peripheral nodes. When implemented in a backplane application, these central nodes are usually the switched fabric cards and peripheral nodes are the line cards. The additional fabric(s) provides redundancy in mission critical system applications in case of failure, or for upgrading fabric card hardware.
Fully Connected Mesh Topology
A fully connected mesh topology, when applied to a backplane application, does not have one central fabric node(s) as in the case of star topologies. Instead, each line card node connects with all other line card nodes forming a mesh. Its major disadvantage is the number of connections grows significantly with the number of nodes. This requires additional backplane connector pins and layers to interconnect them. Because of this, it is impractical for large systems and only used when there are a small number of cards needing to be interconnected.
Fiber weave effect timing skew is becoming more of an issue as bit rates continue to soar upwards. For signaling rates of 5GB/s and beyond, it can actually ruin your day. For example, the figure on the left shows a 5GB/s received eye is totally closed due to 12.7 inches of fiber weave effect. It was modeled and simulated using Agilent ADS software.
So what is fiber weave effect anyways and why should we be concerned about it? Well, it’s the term commonly used when we want to describe the situation where a fiberglass reinforced dielectric substrate causes timing skew between two or more transmission lines of the same length. Since the dielectric material used in the PCB fabrication process is made up of fiberglass yarns woven into cloth and impregnated with epoxy resin, it becomes non-homogeneous.
The speed at which a signal propagates along a transmission line depends on the surrounding material’s relative permittivity (er), or dielectric constant (Dk). The higher the Dk, the slower the signal propagates along the transmission line. When one trace happens to line up over a bundle of glass yarns for a portion of its length, as illustrated by the top trace in the figure on the left, the propagation delay is different compared to another trace of the same length which lines up over mostly resin. This is known as timing or phase skew and is due to the delta Dk surrounding the respective traces.
Fiber weave effect is a statistical problem. It is not uncommon for PCB designs to have long parallel lengths of track routing without any bends or jogs. This is particularly true in large passive backplane designs. Because the fiber weave pattern tends to run parallel to the x-y axis, any traces running the same way will eventually encounter a situation of worst case timing skew if you build enough boards. This was demonstrated by Intel after compiling more than 58,000 TDR and TDT measurements over two years. In 2007, Jeff Loyer et al presented a DesignCon paper “Fiber Weave Effect: Practical Impact Analysis and Mitigation Strategies” where they published the data and proposed techniques to mitigate the effect of fiber weave skew. They showed statistically it is possible to have a worst case timing skew of approximately 16ps per inch representing a delta Dk of approximately 0.8.
In high speed differential signalling this is an issue because any timing skew between the positive (D+) and negative (D-) data converts some of the differential signal into a common signal component. Ultimately this results in eye closure at the receiver and contributes to EMI radiation.
You can calculate the timing skew using the following equation:
tskew = total timing skew due to fiber weave effect length (sec)
Dkmax= dielectric constant of material predominated by fiberglass.
Dkmin= dielectric constant of material predominated by resin.
c = speed of light = 2.998E+8 m/s (1.18E+10 in/s)
A practical methodology you can use to estimate the minimum and maximum values of Dk is by studying the material properties available from PCB laminate suppliers. Consider two extreme styles of fiberglass cloths used in modern PCB laminate construction as illustrated by the figure on the left. The loose weave pattern of 106 has the highest resin content of all the most popular weaves, while the tight weave pattern of 7628 has the lowest. Therefore, you could use the specified values of Dk for cloth styles 106 and 7628 to get Dkmin and Dkmax respectively. Once you have these and apply a tolerance, you can estimate the tskew .
Assume Fr4 material; one inch of fiber weave effect; Dk106= 3.34(+/-0.05) and Dk7628= 3.97(+/-0.05), then timing skew is calculated as follows:
Modern serial link interfaces use differential signalling on a pair of transmission lines of equal length for interconnect between two points. In a DesignCon 2007 paper, “Losses Induced by Asymmetry in Differential Transmission Lines” by Gustavo Blando et al, they showed how intra-pair timing skew between the positive (D+) and negative (D-) data caused an increase in the differential insertion loss profile due to timing induced resonances. These resonances appear as dips in the differential insertion loss profiles of the channel as shown in the following figure:
This figure presents the results from an ADS simulation I did recently of a PCIe Gen2 channel running at 5GT/s. The eye diagrams are at the receiver after approximately 30” of track length chip to chip. The channel model was parameterized to allow for adjusting the fiber weave effect length as required.
As you can see, when the length of the fiber weave effect induced skew increases from 0 to 12.7 inches, the fundamental frequency nulls in the differential insertion loss plots decrease. These nulls occur at the fundamental frequency (fo) and every odd harmonic.
Also, the eye shows some degradation at 5.6 inches of fiber weave effect and starts to distort significantly after 7.8 inches. At 12.7 inches, fo equals the Nyquist frequency of the data rate (in this case 2.5GHz) and the eye is totally closed.
You can predict the resonant frequency ahead of time and use it to gain some intuition before you simulate and validate the results. If you know the total intra-pair timing skew, fo is calculated using the following equation:
fo = resonant frequency
tskew = total intra-pair timing skew
Using tskew = 16 ps/in we calculated above and using 12.7 inches from the last simulation results in the figure above, the fundamental resonant frequency null is:
You can find more details of this phenomena plus a novel way to model and simulate it from a recent White Paper I published titled, “Practical Fiber Weave Effect Modeling”. It, along with other papers, is found on my website at LamsimEnterprises.com.
A transmission line is any two conductors with some length separated by a dielectric material. One conductor is the signal path and the other is its return path. As the leading edge of a signal propagates down a transmission line, the electric field strength between two oppositely charged conductors creates a voltage between them. Likewise, the current passing through them produces a corresponding magnetic field. A uniform transmission line terminated in its characteristic impedance will have a constant ratio of voltage to current at a given frequency at every point on the line.
To ensure good signal integrity, it is important to maintain a constant impedance at every point along the way. Any change in the characteristic impedance results in reflections which manifests itself into noise on the signal. In any printed circuit board design, it is almost impossible to maintain a constant impedance of the transmission path from transmitter to receiver. Things like vias, non-homogeneous dielectric, thickness variation and other component paracitics all contribute to impedance mismatch. In high-speed designs, uncontrolled impedance can significantly reduce voltage and timing margins to the point where the circuit may be marginal or worst inoperable. The best you can do is to try to minimize each impedance discontinuity when they occur.
Lossy Transmission Line Circuit Model:
The circuit model for a lossy transmission line assumes an infinite series of two-port components as illustrated. The series resistor represents the distributed resistance with the units as ohms (Ω) per unit length. The series inductor represents the distributed loop inductance with the units as henries (H) per unit length. Separating the two conductors is the dielectric material represented by conductance G in siemens (S) per unit length. Finally, the shunt capacitor represents the distributed capacitance between the two conductors with units of farads (F) per unit length.
A 2D field solver is the best tool to extract these parameters from a given transmission line geometry. It assumes, however, that the same geometry is maintained through its entire length. Many spice like simulators need these RLGC parameters for their lossy transmission line models.
Given the RLGC parameters, the characteristic impedance can be calculated by the following equation:
Zo is the intrinsic characteristic impedance of the transmission line.
Ro is the intrinsic series resistance per unit length of the transmission line.
Lo is the intrinsic loop inductance per unit length of the transmission line.
Go is the intrinsic conductance per unit length of the transmission line.
Co is the intrinsic capacitance per unit length of the transmission line.
Lossless Transmission Line:
For the lossless transmission line model, Ro and Go are assumed to be zero. As a result, the equation reduces to simply:
Propagation delay, as it relates to transmission lines, is the length of time it takes for the signal to propagate through the conductor from on point to another. Given the inductance and capacitance per unit length, the propagation delay of the signal can be determined by the following equation:
tpd is the propagation delay in seconds/unit length.
Lo is the intrinsic loop inductance per unit length of the transmission line.
Co is the intrinsic capacitance per unit length of the transmission line.
Relative permittivity is also known as relative dielectric constant . The number is a measure of an insulator material’s ability to transmit an electric field compared to a vacuum, which is 1. For simplicity, it is usually referred to it as just the dielectric constant, Dk.
Electromagnetic signals propagate at the speed of light through free space. When these signals are surrounded by insulating material other than air or a vacuum, the propagation delay increases proportionally. You can determine the propagation delay with a known Dk by the following equation:
Dk is the dielectric constant of the material.
c is the speed of light in free space = 2.998E8 m/s or 1.180E10 in/s.