Archive for December 2010
In a recent post from the SI-list I subscribe to asks a question; “How do you find the driver impedance information from the IBIS file?” Most of the time we want this information so that we can explore mitigation techniques to control reflections caused by impedance discontinuities of the transmission path.
IBIS stands for Input/Output Buffer Information Specification and is controlled by the IBIS Open Forum organization. It is a device modeling technique used in simulation to provide a simple table based; non-proprietary buffer model derived from a real semi-conductor device. IBIS models can be used to characterize I/V output curves, rising/falling waveforms and pin parasitics of the device packaging.
When a driver’s output impedance is not matched to the transmission line characteristic impedance (Zo), there are reflections which causes ringing at the receiver as shown by the red waveform in the figure on the left. Terminating the transmission line at the receiver using a pull-up or pull-down resistor to match Zo is one way to cure this. Although this approach works fine, it is not the preferred method because the resistor value would be in the 45-70 Ohm range to match the typical single-ended transmission line impedances found in modern PCB designs. Such a low resistance causes additional loading on the driver resulting in higher power dissipation.
A better method is to add a series resistor at the end of the driver to make up the difference in impedance. For example if the buffer’s output impedance is 20 Ohms driving a 50 Ohm transmission line, you would add a 30 Ohm resistor in series with the output.
Because the buffer is a semi-conductor, it’s output impedance could vary based on rising/falling edge transitions, manufacturing process (slow, typical, fast), and the load it is driving. Since IBIS models are ASCII based, you can simply use your favourite text editor to view and quickly estimate the output impedance when driving 50 Ohms using two of the four V-T waveform tables.
The output impedance is often different for the rising edge compared to the falling edge. To determine the output impedance of a low to high transition you would use the pull-down [Rising Waveform]; R_fixture = 50; V_fixture = 0.000 table. A sample of what this table looks like is shown below:
R_fixture = 50.0000
V_fixture = 0.000
| time V(typ) V(min) V(max)
0.000S 0.000V 0.000V 0.000V
0.2000nS 0.000V 0.000V -1.7835uV
0.4000nS -1.1143mV -8.0018uV -7.8340mV
0.6000nS 0.1336V -5.4161mV 0.9354V
0.8000nS 1.1220V -12.5300mV 2.3940V
* * * *
* * * *
9.6000nS 2.5680V 2.1880V 2.7880V
9.8000nS 2.5680V 2.1880V 2.7880V
10.0000nS 2.5680V 2.1880V 2.7880V
The combination of the output impedance (Zs) and the 50 Ohm load forms a simple voltage divider network described by the following equation:
VO = Voltage at the output pin of the buffer
VDC = Supply voltage
Zs = Buffer impedance
Solving for Zs, we end up with the following equation:
If VDC is 3.3V, and VO is 2.568V using the typical voltage at 10 nS from the V-T table above, the output impedance for the rising edge into 50 Ohms is equal to 14.25 Ohms.
To determine the output impedance of a high to low transition you would use the pull-up [Falling Waveform]; table similar to the following example:
R_fixture = 50.0000
V_fixture = 3.3000
V_fixture_min = 3.0000
V_fixture_max = 3.4500
| time V(typ) V(min) V(max)
0.000S 3.3000V 3.0000V 3.4500V
0.2000nS 3.3000V 3.0000V 3.4500V
0.4000nS 3.2995V 3.0000V 3.4500V
* * * *
* * * *
9.4000nS 0.5598V 0.6824V 0.4812V
9.6000nS 0.5598V 0.6824V 0.4812V
9.8000nS 0.5598V 0.6824V 0.4812V
10.0000nS 0.5598V 0.6824V 0.4812V
This time, the table tells us the falling waveform has a 50 Ohm resistor connected to the buffer output and pulled-up to V_fixture as shown by the equivalent circuit on the right.
The output impedance is calculated by the following equation:
VO = Output voltage when the driver is sinking current
V_Fix = Voltage of the test fixture
Using typical values for V_Fix = 3.3V and VO = 0.5598V at 10nS, Zs = 10.21 Ohms.
As you can see for this particular IBIS model, the output impedance varies depending on the edge transition. For a rising edge, the output impedance is 14.25 ohms and 10.21 Ohms for a falling edge when using the typical values. The impedances will also vary under min/max conditions.
If your load is something other than 50 Ohms, you should NOT rely on this simple method for signoff. Instead you should simulate it if the design is critical. Sometimes though we need a quick ball park number to gain some insight of a particular design or to give us some intuition of what to expect from simulation.
You can validate this methodology using any Spice-like simulator which supports IBIS models. There are many to choose from like HSPICE, Hyperlynx, Cadence Spectraquest, Ansoft Designer from ANSYS and Agilent ADS to name a few. Chances are if you work for a large company, you already have access to some of these tools. If you are a student or someone just starting to learn about signal integrity, there is an alternative available. Fortunately, Spectrum Software offers Micro-cap 10; a free trial of its SPICE software you can use. Although it is limited to the number of components, nodes and performance, it is more than adequate for this and other signal integrity studies. Personally, I found it quite easy to pick up and get productive fairly quickly.
For the purpose of the analysis, the output buffer and it’s impedance (Zs) can be simplified as shown by the schematic on the left. When the buffer drives a 50 Ohm transmission line, you typically see the waveforms at the driver’s output (blue) and receiver’s input (red) as shown in the following plot:
The initial step in the rising and falling edges of the blue waveform (Vs) is due to the voltage divider action between Zs and Zo. Let us call these steps as a “porch” and designate the voltages as Vp_rise/Vp_fall for the rising and falling porches respectively.
Vp_rise is equivalent to the maximum voltage of Rising Waveform table found in the IBIS model. Vp_fall is equivalent to the minimum voltage of Falling Waveform table.
The analysis is best summarized by the following Figure:
A common circuit topology was built using the schematic editor. The respective greyed-out devices are disabled during simulation making it a convenient way of switching them in and out for the different topologies. R1 is reserved for the series termination resistor and is set to 0 Ohms initially. Once the output impedance is determined, R1 is set to the difference between Zo and the output impedance Zs.
The top topology simulates the Pull-up test fixture and used to verify the Falling Waveform table in the IBIS model. Similarly, the center topology simulates the Pull-down test fixture for the Rising Waveform table. The bottom topology has the output buffer driving a real world 50 Ohm transmission line.
The results of the simulations are shown adjacent to their respective topologies. Referring to the last case, Vp_rise=2.555V and Vp_fall=3.3V-2.726V=0.574V . As you can see there is excellent correlation when you compare them against the IBIS model’s voltages of 2.568V and 0.5598V respectively. Using the simulated voltages and solving for Zs, we get 14.58 Ohms and 10.53 Ohms respectively.
Because Zs is different for the rise time and fall time, you can never perfectly compensate for the impedance mismatch. The best approach is sometimes to take the average value between the two. In this case Zs_avg=12.56 Ohms.
Once Zs is known, the series resistor can be calculated as follows:
When 38 ohms is substituted in the transmission line topology, the waveform is clean with minimum reflections as shown by the following results:
In conclusion, the methodology presented here is a simple and effective way to predict the driver’s output impedance from an IBIS model. Try it next time someone asks you the question, “How do you find the driver impedance information from the IBIS file?”
Present day FR4-style laminates used for PCB fabrication rely on woven glass fiber yarns to maintain the structural integrity of the finished product. These yarns are made up of electronic or E-Glass material. Because it is the same glass used in everything from Corvette bodies to boat hulls, it is a very inexpensive reinforcement material. NE-Glass has improved electrical and mechanical performance over E-Glass. It is used for higher performance laminate products such as Park Nelco 4000-13SI.
The table on the left shows five of the most common fiberglass styles used for laminate construction today. When glass fiber yarns are woven into fabric, the “Warp” yarns run the length of the roll, while the “Fill or Weft” yarns run the width. Yarn count refers to the number of warp threads per inch by the number of fill threads per inch.
Prepreg is the term we commonly use for a weave of glass fiber yarns pre-impregnated with resin which is only partially cured. The glass to resin thickness ratio defines the overall thickness of a prepreg mat. You can see from the table above, the typical resin content is a function of the thread count and yarn diameter. For example, the figure on the far left illustrates styles like 106 and 1080 having smaller diameter yarns and higher resin content. The right hand figure is indicative of yarns with larger diameter and lower resin content like style like 2116 or 7628.
When copper foil is attached to one or both sides of fully cured prepreg mats, the finished laminated panel is called a core. Both cores and prepreg mats are available in various panel sizes and thicknesses.
There are several different kinds of resin systems in use today to form prepreg and cores. The general specification FR4 is the most common. It refers to a specific fire-retardant level rather than specific resin chemistry. Since you have a choice of many laminates that meets the FR4 fire specification, there is no such thing as “standard FR4″. That being said, most of us consider “standard FR4” to mean a laminate having a typical dielectric constant (Dk) of about 4.3 and dissipation factor (Df) of 0.020 – 0.025 at 1MHZ and 50% resin content.
Each family of resin systems have their unique electrical and mechanical characteristics depending on the fiberglass style and resin chemistry. For example, Nelco 4000-6 at 50% resin content has a typical Dk of 4.0 and Df of 0.023 at 2.5GHz. A higher performance resin system like Nelco N4000-13 on the other hand, has a Dk of 3.7 and Df of 0.009 for the same resin content and frequency. This tells us two things:
A lower Dk means we can ultimately achieve an overall thinner board for the same characteristic impedance.
A lower DF means less high frequency attenuation allowing us to run at a higher bit rate or have longer traces.
When designing your board stack-up, it is best to refer the manufactures data sheet for exact values. The Park Electrochemical Corp. (Nelco) website is an excellent resource to explore when trying to decide on the best dielectric material to use for your next high-speed design.
Welcome to my Blog! I am Bert Simonovich, founder and president of Lamsim Enterprises Inc. I graduated in 1976 from Mohawk College of Applied Arts and Technology in Hamilton, Ontario, Canada as an Electronic Engineering Technologist. I started my consulting business after working 32 years at Bell Northern Research/Nortel. Throughout my career, I have held a variety of hardware design engineering positions and pioneered several advanced technologies into products. Currently I offer innovative signal integrity and backplane solutions as a consultant.
From as far back as I can remember, I was always interested in how things worked. I would often take things apart just to see what was inside; -not always successful in putting them back together again though ;-o. I was always fascinated with electricity and electronics. When I was about 10 or 11, I was mystified with how telephones worked. After reading about Alexander Graham Bell in a booklet published by The Bell Telephone Company of Canada, I became inspired to buy a pair of old push to talk handsets from a local army surplus store. I experimented with them using a drycell battery and lamp cord wire. When I finally was able to get two-way communications, it seemed like magic. I knew right then what my career choice would be.
I have been fortunate throughout my career to have been a part of and contribute to some of the technology that enable the gadgets we enjoy today. I have met and worked with many smart and talented individuals who took the time to unselfishly share their knowledge and experience.
And now, after all this time, the passion I had as kid to learn and understand new things is still there. Except now, like cradling a fine glass of wine, I am able to slowly swirl it around, sip it and savor the taste. This blog is about sharing some of that passion. It will cover a range of topics from signal integrity, PCBs, backplane design, circuit modeling, simulation tools and other practical engineering solutions. I hope you find my posts interesting and get inspired to explore them further on your own.
Thanks for visiting. I invite you to constructively comment and share your own thoughts and experiences as well.