Originally published in, The PCB Design Magazine, April 2013 issue.
By definition, a guard trace is a trace routed coplanar between an aggressor line and a victim line. There has always been an argument on whether to use guard traces in high-speed digital and mixed signal applications to reduce the noise coupled from an aggressor transmission line to a victim transmission line.
On one side of the debate, the argument is that the guard trace should be shorted to ground at regular intervals along its length using stitching vias spaced at 1/10th of a wavelength of the highest frequency component of the aggressor’s signal. By doing so, it is believed the guard trace will act as a shield between the aggressor and victim traces.
On the other side, merely separating the victim trace to at least three times the line width from the aggressor is good enough. The reasoning here is that crosstalk falls off rapidly with increased spacing anyways, and by adding a guard trace, you will already have at least three times the trace separation to fit it in.
In our DesignCon2013 paper titled, “Dramatic Noise Reduction using Guard Traces with Optimized Shorting Vias”, I coauthored along with Eric Bogatin, we showed that sometimes guard traces were effective, and sometime they were not; depending on how the guard trace was terminated. By correct management of the ends of the guard trace, we demonstrated it can reduce coupled noise on a victim line by an order of magnitude over not having the guard trace present. But if the guard trace was not optimized, the noise on the victim line can also be larger with the guard trace, than without.
Analysis Using Circuit Models
We started out the investigation by building circuit models for the topologies studied. Agilent’s EEsof EDS ADS software was used exclusively to model and simulate both stripline and microstrip configurations. The generic circuit model, with a guard trace, is shown in the top half of Figure 1. The circuit model, without a guard trace, is shown in the bottom half.
For the analysis, we used lossless transmission line models. The guard trace length was exactly matched to the coupled length. The ground stitching and the end-termination resistors, on the guard trace, could be deactivated, and/or shorted, as required. The line-width space geometry was set at 5-5-5 mils, and the spacing for the non-guarded topologies was set to three times the line width.
Figure 1 ADS schematic for generic topologies with a guard trace (top) and without (bottom). The transmission line were segmented and parameterized to easily change the lengths as required. The ground stitching and the end-termination resistors, shown in top schematic, can be deactivated and/or shorted as required.
Figure 2 is a summary of results when a guard trace was terminated in the characteristic impedance, left open, or shorted to ground at each end. The red waveforms are the results for topologies without a guard trace, and the blue waveforms are with a guard trace.
Depending on the nature of the termination, the reinfected noise on the guard trace can add or subtract to the directly coupled noise on the victim line. This often makes the net noise on the victim line worse than without a guard trace.
Unlike a simple two-line coupled model, where the near end crosstalk (NEXT) and far end crosstalk (FEXT) can be easily predicted from the RLGC matrix elements, trying to predict the same for a three-line coupled model is more difficult. Manually keeping track of all the noise induced on the guard trace, and its reinfection onto the victim line, is extremely tedious. First you must identify the directly coupled reinfected backward and forward noise on the victim line from the voltage on the guard trace. Then the problem is keeping track of the multiple reflections of the noise on the guard trace. Because of this, the only real way to analyse the effect is through circuit modeling and simulation.
In microstrip topologies, as you can see, there is little to no benefit to adding a guard trace; regardless of how the ends are terminated. This is because microstrip topologies are inherently prone to far end crosstalk. Therefore any far end noise, coupled onto the guard trace, will subsequently reinfect the victim with additional far end noise; as seen by the additional ringing superimposed on the blue waveform.
In stripline topologies, without a guard trace, there is no far-end cross talk generated. But when a guard trace is added, and depending on how the ends are terminated, any near end coupled noise on the guard trace can reinfect the victim. It is only when the ends are shorted to ground we see such a dramatic reduction of both near and far end noise.
Figure 2 Summary of simulation results when the ends of the guard trace was terminated, left open or shorted to ground for microstrip and stripline geometries.
Distributed Shorting Vias
When practically implementing a guard trace, to act as a shield, a rough rule of thumb suggests the spacing of shorting vias should be at least 1/10 the wavelength of the highest frequency content of the signal. For a risetime of 100 psec, the stitching via spacing, to meet l/10, is 0.18 inches; or 9 stitching vias over 1.5 inches.
Figure 3 summarizes the results when a guard trace was stitched to ground at multiple wavelengths; compared to the case of no guard. As you can see, in the case of microstrip, when the guard trace is shorted with fewer than 9 vias, there is still considerable ringing noise on the guard trace which can reinfect the victim line. But in the case of stripline, having two shorting vias at each end, or any number up to 9 shorting vias has the same result. This suggests there is no need for multiple shorting vias, other than at the end of the guard trace; as long as the guard trace is the same length as the coupled length. This dramatically simplifies the use of guard traces in stripline.
Figure 3 Summary of simulation results with guard trace stitched for microstrip and stripline geometries.
Practical Design Considerations
Up until now we have modeled and simulated ideal cases of shorting the guard traces to ground. But in reality, there are additional practical design considerations to consider. First is via size, and the impact it has on the line to line spacing. Next is the finite via inductance; since its impedance will prevent complete suppression of the noise on the guard trace. And finally, the extension of the guard trace compared to the coupled length.
Because through hole manufacturing design rules limit the smallest via and capture pads, the smallest mechanical drill size most PCB vendors will spec is 8 mils. By the time you factor in the minimum pad diameter and pad to copper spacing, the minimum space between the aggressor and victim lines would have to be at least 28 mils, as shown in Figure 4; just to fit a guard trace with grounding vias down its length.
At this point, you have to ask yourself if it is even worth it; especially for microstrip topologies. If the two signal lines were to be increased to 28 mils, the reduction in cross talk from just the added separation would likely be more significant than adding the shorted guard trace.
Figure 4 Minimum track to track spacing to fit an 8 mil drilled via and pad in through-hole technology.
Fortunately, the circuit analysis has shown there is little benefit to adding a guard trace to microstrip topologies, even if it was ground stitched appropriately. But to gain a dramatic reduction in cross talk in stripline all that is required is to short the guard trace at each end, and ensure the guard trace is exactly the same length as the coupled length. This means the minimum space to fit a via and guard trace can remain at three times the line width; as long as the guard trace is extended slightly, as shown in Figure 5(a). Alternatively, the guard trace can be made equal to the coupled length, as illustrated in Figure 5(b).
Agilent’s ADS Momentum planar 3D field solver was used to explore and quantify the implications vias and guard trace lengths have on noise reinfection. Figure 5 details a portion of the 3D model on the left end of the respective topologies. The right hand sides are identical. The reference planes are not shown for clarity.
Figure 5 Two examples of adding a grounded guard trace with minimum spacing of 3 x line width. Figure (a): guard trace is extended past the coupled length (A) by dimension B on both sides in order to satisfy minimum 5 mil pad-track spacing requirements. Figure (b): guard trace is equal to coupled length by separating the traces at each ends. Modeled in Agilent Momentum 3D field solver. Reference planes are not shown for clarity.
After simulation, the S-parameter data was saved in Touchstone format and brought into ADS for transient simulation analysis and comparison. Figure 6 shows the results. The plot on the left used 100 psec risetime for the step edge, while the plot on the right used 50 psec. Both plots are consistent with the dramatic noise reduction observed in Figure 2, except here we see some added noise ripple after about 0.8 nsec.
At 100 psec risetime, there is effectively no difference in near end noise signature for either (a) or (b) topology. But when the risetime was reduced to 50 psec, the noise ripple is more pronounced. The blue waveform shows that even when dimension B is 0 mils, there is still a small amount of noise due to the inductive length of the vias to the reference plane. The red waveform shows that adding just 12 mils to the guard trace length, at each end, the ripple magnitude is almost doubled.
It is a well-known fact that technology advancements over time results in faster and faster rise times. If you have engineered your design on the technology of the day, any future substitution of parts, with faster rise time, may cause your product to fail, or worse be intermittent.
Figure 6 Momentum transient simulation results comparing near end crosstalk at Port 1 when aggressor voltage was applied to Port 3. The red and blue waveforms are with a guard trace. The green waveform is with no guard and 15 mils separation. Aggressor voltage = 1V, 100 psec risetime (left) and 50 psec risetime(right)..
To explore this phenomenon, the guard trace was varied by 50 and 100 mils at each end, as illustrated in Figure 7. Here we can see that as the guard trace gets longer at each end, the noise ripple grows in magnitude quite rapidly. It is remarkable to note that when the guard trace is just 100 mils longer, at each end, the peak-peak amplitude of the noise just about equals the peak magnitude of the no guard case.
Figure 7 Momentum transient simulation results with guard trace extended. B = 12 mils (red), B = 50 mils (blue) and B = 100 mils (magenta) compared to no guard (green). Aggressor voltage = 1V, 100 psec risetime. Dimensions in mils.
When the guard trace was removed, and the space was increased to five times the line width, the near end crosstalk was reduced in magnitude and was approximately equal to the guard trace scenario, as seen in Figure 8. Furthermore, because there is no guard trace, there is no additional noise ripple.
Figure 8 Momentum transient simulation results comparing near end crosstalk at Port 1 when aggressor voltage was applied to Port 3. Aggressor voltage = 1V, 100 psec risetime.
So getting back to the original question, “Are guard traces worth it?” You be the judge. Using a guard trace, shorted at each end, can be effective, if you need the isolation. But it does have caveats. If you decide to go down this path, it is imperative for you to model and simulate your topology, preferably with a 3D field solver, before signing off on the design.
Eric Bogatin, Bert Simonovich,“Dramatic Noise Reduction using Guard Traces with Optimized Shorting Vias”, DesignCon2013, Santa Clara, CA, USA, Jan 28-31, 2013.
Originally published in, The PCB Design Magazine, November 2012 issue.
In normal PCB designs, crosstalk is usually an unwanted effect, due to electro-magnetic coupling, of two or more traces routed in close proximity to one another. We usually consider it to be our enemy, in any high-speed design, and go to great lengths to avoid it. So how, you may ask, can crosstalk ever be your friend?
To answer that question, I would like to start out by taking you back to the fall of 1994. This was the era of wide parallel busses running up to 33 MHz across backplanes. High-speed serial, point-point interfaces, and serdes technology, as we know and love today, was just a twinkle in some bright young engineer’s eye.
Nortel, a.k.a. Northern Telecom at the time, was looking to replace the computing module shelf of the DMS Supernode platform because it was projected to run out of steam a few years later. In order to address the issue, the system architects decided that a scalable, multi-processing, shared memory, computing architecture was needed to replace it.
My job was to develop a concept to package all these cards in a shelf, and then design a backplane to interconnect everything. It quickly became evident that a single shared bus could not support the bandwidth required for multi-processing. Nor could multiple parallel buses solve the problem, because of the lack of high-density backplane connector technology needed for all the I/O. Even if we had a suitable connector, and it could magically fit within the confines of the card slot, then the layer count of the backplane would have grown exponentially.
No, something else was needed. Fortunately, Bell Northern Research (BNR), the R&D lab of Nortel where I was working at the time, had an advanced technology group, that liked to play in the sand. I remember going to a meeting one day to see some presentations on some of the neat technology they were playing with.
One presentation they gave, was of a unique non-contact interconnect technology. I immediately saw the practical application that technology offered for our architecture, and it instantly became my friend. It allowed us to eventually invent a patented, proprietary point to multi-point interconnect solution, running at 1GB/s per pair .
The non-contact technology actually relied on controlled electro-magnetic coupling, or simply crosstalk. See Figure 1. In this simple high-level block diagram, each card on the shelf would transmit their data differentially across the backplane. As the differential pairs traversed through the connector fields of the card slots, the transmit signal was edge-coupled to an adjacent small trace, about three quarters of an inch long, connected to the respective receiver pin. After the last card slot, the transmit differential pairs switched layers where they returned back to the originating card and were terminated.
The beauty of this architecture was that each card only needed one set of transmitters to broadcast its data to all the other cards. Since each card had enough receivers to listen to the other cards, the point to multi-point interconnect achieved the equivalent of a multipoint to multipoint architecture; but without the overhead of additional pins and PCB layers. Furthermore, an effective line rate of 1GB/s was achieved using simple, inexpensive 2mm connectors; the same ones chosen for compact PCI standard.
Figure 2 is a photograph of an inner layer, double-sided core of the backplane, prior to lamination and drilling. It shows the couplers in more detail. The round pads are for the connector vias, and are used to attach the coupler traces to the connector pins. The rows of pads on the left are for one card slot, while the rows of pads on the right are for another card slot.
If we look at the two traces entering the picture from the bottom left side, we can see how they are routed through the connector field. These two traces are part of a differential pair where each are routed as single-ended traces, i.e. with no coupling to one another. As these traces approach the first row of pads, they jog down to minimum spacing to ensure close coupling to the coupler traces attached to the pads. The close spacing continues to ensure maximum coupling to the next set of pads, where the pattern stars all over again at the bottom right. This pattern repeats all the way up the photo for each differential pair.
You may be astute to notice that the bottom coupler trace connects to a pad at each end, while the mate coupler, above it does not. When two, coplanar parallel traces are in close proximity to one another, there are two types of crosstalk generated; backward or Near-End crosstalk (NEXT); and forward or Far-End crosstalk (FEXT).
As the transmit signal propagates, from left to right in the photo, the rising edge of the signal initiates NEXT at the beginning of the coupled length. The NEXT voltage saturates after a critical length equal to the risetime divided by twice the propagation delay; where the risetime is in seconds, and propagation delay is in seconds per unit length. It stays saturated for twice the time delay of the coupled length. Because of differential signalling, the NEXT voltages are of opposite phase on the respective couplers.
At the coupler pin, there is a reflection caused by the via. Since the couplers, at the far-end, are not terminated, in the characteristic impedance, and left open, any secondary reflections due to coupler via reflects back towards the receiver, again with opposite phase. When both reflections arrive back at the receiver, they will add together and add additional noise to the eye, causing inter-symbol interference, as shown by the shoulder in Figure 3(A). By leaving one end open, and shorting the other one to ground, means that any secondary noise will have the same phase, and when they arrive at the receiver, they will cancel, thereby eliminating the inter-symbol interference and increasing the eye amplitude as shown in Figure 3(B).
You will notice that the eye waveforms do not resemble the traditional eye diagram we are used to seeing. Instead we observe a typical NEXT eye, when the coupled length is short, compared to the bit time. There is also a line right in the middle.
Figure 4 can help to explain the reason. The blue waveform is the NEXT voltage, seen at the near-end of the coupler, in response to the red transmitted waveform. Notice that there are only pulses at an edge transition of the transmitted waveform. A rising edge creates a positive pulse, and a falling edge generates a negative pulse. The duration of each pulse is twice the time delay of the coupler length.
The receiver uses simple peak-detectors and latch to regenerate the signal back to the original waveform. A positive going pulse is detected by the positive peak-detector. When it crosses the positive voltage threshold (+Vth), it sets the latch output to logic high. The output remains high until a negative pulse crosses the negative threshold (-Vth), of the negative peak-detector, and resets the latch to logic low.
And that is how crosstalk can be your friend! Of course the small coupled crosstalk signal means we have to guard against CROSSTALK from other digital signals on board. But that’s nothing that mixed signal layout design rules can’t solve. ……Wait a minute! ……We both share the same enemy? …….. Who would have thought an old Proverb, “The enemy of my enemy is my friend” [sic], would apply here too?
 L. Simonovich et al, U.S. Patent 6,091,739, “HIGH SPEED DATA BUS UTILIZING POINT TO MULTI-POINT INTERCONNECT NON-CONTACT COUPLER TECHNOLOGY ACHIEVING A MULTI-POINT TO MULTI-POINT INTERCONNECT.”
 J. Williamson et al, U.S. Patent 6,016,086, “NOISE CANCELLATION MODIFICATION TO NON-CONTACT BUS.”
 Alexandre Guterman, Robert J.Zani, “Point-to-Multipoint Gigabit Backplane Design”, IEEE International Symposium on EMC, May 11-16, 2003.
Recently I came across a blog post titled, “Can Oscilloscopes Really Calculate BERs?”, written by Ransom Stephens.
I liked this article. I liked it because, as usual, Ransom likes to challenge your way of thinking and makes you go back to basics in order to understand. For example, when he debates whether BER is “bit error ratio” or “bit error rate”, it stopped me in my tracks to question if I was using the correct terminology, and why. For the record, when I started my career working on T1 line repeaters, I was taught it was “rate”. But, technically, Ransom’s assertion that it really is “ratio” is also correct.
Before you discount this and say, “In mathematics, there can be only one answer”, stay with me here, and let me try to explain where I’m coming from. According to Merriam-Webster dictionary, the definition of ratio is, “the indicated quotient of two mathematical expressions”, or “the relationship in quantity, amount, or size between two or more things: proportion”. If you take the number of bit errors and divide them by the total number of bits, then you have, by definition, a ratio, as Ransom claims. For example, if you have 1 error in 1 TBits of data, then you have a “bit error ratio” of 1E-12.
When you look up the word rate, in the same dictionary, the definition is, “reckoned value: valuation” or “a fixed ratio between two things”. In terms of BER, when it is defined as rate, the fixed ratio between two things is the number of errors over some period of time. Since a bit has a time component associated with it, you can convert the total number of bits into time by multiplying it by the bit time. For example, at 10 GB/s, the bit time is 100 ps. So 1TB of data takes 100 seconds to transmit all of the bits. If there was 1 bit error during that time, you would have a “bit error rate” of 1 error per 100 seconds.
In mission critical applications, we usually aspire to have error-free performance for the life of the product. As bit rates continue to climb, that’s an awful lot of bits. Theoretically, if you want your product to have a bit error rate of 1 error in 25 yrs, then, at 10GB/s, you would need to transmit 7.884E+18 bits;[25yrs*(60*60*24*365)sec/yr*10GB/s] to have a bit error ratio of 1.268E-19!
Bit error ratio, or bit error rate? It kind of reminds me of part of the song, “Let’s Call the Whole Thing Off”, by George and Ira Gershwin; “You like to-may-toes, and I like to-mah-toes”. At the end of the day, it’s still tomatoes. In the right context, I think both terms are equally valid. You need to be ambidextrous, so to speak, in your analysis and how you quote the number.
Huh? …… What do you mean by that? ……
For years now the popular opinion was that PCB vias were capacitive in nature, and therefore could be modeled with lumped capacitors. Although this might be true when the rise time of the signal is greater than or equal to 3 times the delay of the via discontinuity, I’ll show you why it is no longer appropriate to think this way; even risky to continue to model your high-speed channel using this methodology.
Let’s start the discussion by saying vias are transmission lines with excess parasitic capacitance or inductance. Vias are considered transparent when their impedance equals the characteristic impedance of the transmission lines attached to them. In almost all cases, vias passing through multi-layer PCBs are capacitive because of the distributed capacitance between the via barrel and anti-pads. As a result, they end up having lower impedance than the traces connected to them. Like any other transmission line, when a rising edge of a signal encounters a lower impedance, it will cause a negative reflection for the length of the discontinuity.
Getting back to the point, it is best demonstrated by an example as summarized in Figure 1. Consider a via at the far end of a long 50 Ohm transmission line. The via has a short through section and a long stub section. The through section is 15 mils and the stub is 269 mils for a total via length of 284 mils. This is not unusual for modern backplane designs.
For this particular via geometry, the impedance is 33 Ohms and the excess via capacitance is 1.9pf. Even with a fast 50ps rise time at the source, by the time the signal reaches the via at the far end, the rise time will degrade due to dispersion caused by the lossy dielectric. In this example, after 23 inches, the rise time has degraded to approximately 230ps.
If the total delay (TD) of the via discontinuity is 60 ps, then the 230 ps rise time at the via is greater than 3TD (180ps). As expected, when modeling the via with a lumped capacitor equal to the excess capacitance, and comparing it with the transmission line via model, the TDR plot of the reflections are virtually the same using a 230ps rise time.
Figure 1 Via model TDR comparison after 23 inches. Top topology uses 33 Ohm transmission lines for both the through and stub portion of the via. The bottom topology models the via with a 50 Ohm transmission line to represent the delay of the through portion and a 1.9pf capacitor to represent the excess capacitance. Modeled and simulated with Agilent ADS.
So far so good, right? Well maybe so. The only way to know is to explore this topology even further and compare eye diagrams. Let us say your circuit needs to work at XAUI rate of 3.125 GB/s. You modify both topologies by adding a driver and receiver. After simulating you end up with eye diagrams as shown in Figure 2.
Figure 2 Eye comparison at 3.125Gb/s. Top topology uses 33 Ohm transmission lines for both the through and stub portion of the via. The bottom topology models the via with a 50 Ohm transmission line to represent the delay of the through portion and a 1.9pf capacitor to represent the excess capacitance. Modeled and simulated with Agilent ADS.
Still ok. So what is your point, you might ask?
You are correct when you comment there is a good match for reflections and the eyes are wide open. Ah, but now let us say you want to run this at 10GB/s down the road. So you dial up the bit rate on the transmitters and simulate both topologies again. But this time, you get some unexpected results as shown in Figure 3.
Figure 3 Eye comparison at 10Gb/s. Top topology uses 33 Ohm transmission lines for both the through and stub portion of the via. The bottom topology models the via with a 50 Ohm transmission line to represent the delay of the through portion and a 1.9pf capacitor to represent the excess capacitance. Modeled and simulated with Agilent ADS.
Ouch! What happened here? Looking at the TDR, the reflections at the end of the channel look the same so why doesn’t the receive eyes match? To answer this question, we really need to look at the S-parameter plots of both channels. Figure 4 shows the insertion and return losses of both topologies. Red is the transmission line model and the blue is the capacitor model.
Figure 4 Insertion and return loss of both topologies. Red curves are the transmission line via model and blue curves are the capacitor model.
The insertion loss plot represents the transmitted output power vs. frequency while the return loss is the reflected power vs. frequency. In the time domain, the insertion loss and return loss is equivalent to the TDT and TDR plots respectively. As you can see, the return loss matches pretty well; just like the TDR plot we observed earlier, but It is only obvious when we view the insertion loss plot as to the real reason for the eye discrepancy of Figure 3.
Notice the first resonant null at approximately 4.5 GHz. This null represents the quarter wave resonant frequency fo, and is due to the long 269 mil via stub. The other null at 13.5GHz is the 3rd harmonic of fo. The longer the stub length, the lower the resonant frequency. When there is a null at or near one-half the bit rate, then the eye will be devastated. In our example, 4.5GHz is approximately half of 10GB/s and as you can see from Figure 3 the resultant eye is totally closed.
But the S-parameters tell us even more. We can use them to confirm the rule of thumb used earlier with respect to the rise time of the signal being greater than, or equal to, 3 times the delay through the via discontinuity.
If you study the return loss plot, you will see there is an excellent match up to about 1.83GHz. This is the effective bandwidth for which the capacitor model is good for. Put another way, a bandwidth of 1.83GHz means you could use an equivalent capacitor model for the via for bit-rates up to 3.6GB/s.
Equation 1 is a commonly used to convert 3dB bandwidth to equivalent 10-90 rise time. Substituting 1.83 GHz for the 3dB bandwidth, the rise time equals approximately 185 ps.
When you divide 185 ps by 3, you end up with approximately 62ps compared to approximately 60ps for the propagation delay through the via we originally determined earlier.
Figure 5 is a summary of a simulation with the transmission line length reduced to 18 inches to reduce the rise time to 185 ps. As you can see the transmission line via model’s eye at 3.6 Gb/s is just starting to distort while the capacitor model is still relatively smooth; confirming our bandwidth rule of thumb. Using a capacitor as a via model past this bit-rate will result in optimistic results and long nights when your 10 Gig prototype hits the lab.
So now you see what I mean when I say that vias are capacitive, but not necessarily capacitors.
Figure 5 Eye comparison at 3.6Gb/s. Top topology uses 33 Ohm transmission lines for both the through and stub portion of the via. The bottom topology models the via with a 50 Ohm transmission line to represent the delay of the through portion and a 1.9pf capacitor to represent the excess capacitance. Modeled and simulated with Agilent ADS.
For more Information:
If you liked this design note and want to learn more, or get more details on modeling vias using transmission lines, you can visit my web site, LAMSIM Enterprises.com , and download a copy of the white paper I wrote along with Eric Bogatin and Yazi Cao titled, “Method of Modeling Differential Vias” .
While you are there, feel free to investigate my other white papers and publications.
If you would like more information on our signal integrity and backplane services, or how we can help you achieve your next high-speed design challenge, email us at: email@example.com.
I recently came across some souvenir pictures and artwork of work I had done early in my career at Bell Northern Research. For those of you who are old enough to remember, it will bring back some fond memories of the technology back in the day; and for you young designers, this is how we did things back in the late ‘70s, early ‘80s.
Figure1 Northern Telecom T1C line repeater circa 1980.
Figure 1 is a T1C line repeater I helped to design early in my career circa 1980. Line repeaters were used to regenerate digital signals along a span between two central offices. There were two regenerators per line repeater, and one repeater for every 4-pairs (2Tx, 2Rx) in the cable. They were housed in apparatus cases mounted on telephone poles or pedestals every mile or so. In the city they were usually installed in manhole vaults buried underground.
T1 digital transmission was introduced in 1961 as a way to replace older analog voice frequency technology, and is still in use today. T1 data rate is 1.544 Mb/s and carries 24 channels of DS0 at 64Kb/s. As digital technology exploded through the 1970’s, it became more affordable, allowing T1 to become more popular. By the early 1980’s, the installed base was reaching capacity especially in large cities, and the industry was looking for ways to increase its bandwidth. Sound familiar? To address this issue, a new T1C standard was developed to double the bandwidth. T1C stands for T1-concatenated, and doubles the data rate to 3.152 Mb/s allowing it to carry 48 DS0 channels.
As part of the T1C project team, my primary responsibility was to package the design and lay out the printed circuit board. Because of the limited real estate available and because through-hole component technology was the only choice for PCBs, we needed to use thick-film technology for the receiver equalization circuitry.
Thick-film technology was quite popular at the time, and was the predecessor to today’s surface-mount technology on PCB’s. It allowed for the miniaturization of circuitry by screen printing conductive traces and resistive ink onto a ceramic substrate, then firing it to a high temperature. Surface mount components were limited to capacitors, SOT transistors and diodes.
At the time, Northern Telecom (NT) had their own in-house thick-film design and manufacturing facility located in Aylmer, Quebec. All of the thick-film designs used in NT’s products prior to the T1C project were single in-line packages (SIPs). Because of the height restriction, and the amount of circuitry needed to be integrated onto the substrate, SIPs were impractical, so we had to develop dual in-line manufacturing capability at the same time we were developing the product.
The final dual in-line thick-film packages are shown near the faceplate. Since the packaging of the repeater was so dense, I needed to place components under the thick-film substrates. This was all well and good until I was testing a bunch of repeaters for a field trial in California coming up in December of that year. I accidentally dropped one and it happened to land flat with component side up. After I picked it up, I had noticed both thick-film substrates were cracked. How could this be? There was enough clearance from the highest component underneath, and enough pins to support the ceramic substrate, so why did it break?
Fortunately, we had a state of the art photography lab in the building with high-speed camera equipment. So we set up a controlled experiment to capture what went wrong. We built up some test samples and dropped them while capturing it all at high-speed. Well it wasn’t a fluke. Every one that we dropped and filmed showed the same result. It turns out there was enough flex in the long right angle pins, that the momentum of the substrate caused it to hit the radial capacitor underneath, then spring back as if nothing had ever happened. Under other circumstances, this would have been cool to see, but not when the project was in jeopardy.
To make a long story shorter, I eventually came up with an elegant solution for a plastic carrier that would support the substrate and keep it at a fixed height above the board. Not only did it solve the reliability problem, but it also solved the shipping and handling protective packaging issue for the thick-film assembly at the same time.
Figure 2 shows the actual artwork for the repeater’s PCB. Back then, all our boards were double-sided and all layouts were done by hand; first in colored pencil, then using red/blue tape and pads on mylar film for final artwork. Red usually represented the solder (bottom) side of the board and blue was the component (top) side. The artwork was usually done at 2:1 scale and later photo reduced to produce the 1:1 photo-masks. Red and blue filters were used during the photo reduction process to separate individual layer masks. A red filter generated the component side and blue filter produced the solder side photo-masks respectively. All drilled holes were manually specified on a separate drawing with various symbols for the drill sizes. Line widths and space were typically 25 mils and components were on 100 mil pitch. All components were through-hole mounted on one side only and passed through a solder wave.
Figure 2 Example of double-sided artwork for the T1C line repeater. Red is solder side, blue is component side.
The T1C line repeater project from its inception, to designing, testing, building 50 prototypes by hand and completing a successful field trial in California, took about 6 months; all with a team of three plus our manager, and mechanical design support staff. Finding these pictures truly was a blast from the past. Looking back, I sometimes wonder if we could have done it any faster with today’s modern technology, CAD tools and outsourcing business model. What do you think?
Born in Hamilton, Ontario, Canada, Bert graduated in 1976 from Mohawk College of Applied Arts and Technology in Hamilton, Ontario, Canada as an Electronic Engineering Technologist. Over a 32 year career at Bell Northern Research and Nortel, he helped pioneer several advanced technology solutions into products and has held a variety of R&D positions, eventually specializing in high-speed signal integrity and backplane design. He is the founder of Lamsim Enterprises Inc. providing innovative signal integrity and backplane solutions. He is currently engaged in signal integrity, characterization and modeling of high-speed serial links associated with backplane interconnects. With three patent applications and two patent grants to his name, he has also (co)authored several publications, including an award-winning DesignCon2009 paper related to PCB via modeling. His current research interests include signal integrity, high-speed characterization, and modeling of high-speed serial links associated with backplane interconnects. To contact Bert, email him at: firstname.lastname@example.org
You are a backplane designer and have been assigned to engineer a new high-speed, multi-gigabit serial link architecture from several line cards to multiple fabric switch cards across a backplane. These links must operate at 6GB/s day one and be 10GB/s (IEEE 802.3KR) ready for product evolution. The schedule is tight, and you need to come up with a backplane architecture to allow the rest of the program to progress on schedule.
You come up with a concept you think will work, but the backplane is thick with over 30 layers. There are some long traces over 30 inches and some short traces of less than 2 inches between card slots. There is strong pressure to reuse the same connector you used in your last design, but your gut tells you its design may not be good enough for this higher speed application.
Finally, you are worried about the size and design of the differential via footprint used for the backplane connectors because you know they can be devastating to the quality of the received signal. You want to maximize the routing channel through the connector field, which requires you to shrink the anti-pad dimensions, so the tracks will be covered by the reference planes, but you can’t easily quantify the consequences on the via of doing so.
You have done all you can think of, based on experience, to make the vias as transparent as possible without simulating. Removal of non-functional pads on the inner layers, and planning to back-drill the connector via stubs will help, but is it enough? You know in the back of your mind the best way to answer these questions, and to help you sleep at night, is to put in the numbers.
So you decide to model and simulate the channel. But to do so, you need accurate models of the vias to plug into your favorite circuit simulator. But how do you get these? You have heard it all before; “for high-speed, the best way to model a via is with a 3D electro-magnetic field solver”. Although this might be true, what if you don’t have access to such a tool, because the cost is more than your company wants to spend, or because you don’t have the expertise nor the time to learn how to build a model you can trust to make a timely decision?
On top of that, 3D field solvers typically produce S-parameter behavioral models. Since they represent only one sample of a given construction, it is impossible to perform what-if, worst case, min/max analysis with a single behavioral model. Because of this, many iterations of the model are required; causing further delay in getting your answer.
A circuit model on the other hand, is a schematic representation of the actual device. For any physical structure, there can be more than one circuit model to describe it. All can give the same performance, up to some bandwidth. When run in a circuit simulator, it predicts a measurable performance of the structure. These models can be parameterized so that worst case analysis can be explored quickly.
The problem with a circuit model is that you often need a behavioral model to calibrate it, or need to use analytical equations to estimate the parameters. But, as my friend Eric Bogatin often says, “an OK answer NOW! is better than a great answer late”.
In the past, it was next to impossible to develop a circuit model of a differential via structure without a behavioral model to calibrate it. These behavioral models were developed through empirical formulas, measured data, or through the use of 3D EM field solvers.
Now, there is another way. I have nicknamed it, “The Poor Man’s PCB Via Modeling Methodology”. Here’s how it works.
Anatomy of a Differential Via Structure:
The via barrel is a plated through hole extending the entire length of a PCB stack-up. The outside diameter equals the drill diameter. The inside diameter is the finished hole size (FHS) after plating. Pads are used on layers to ensure there is sufficient copper for track attachment after drilling operation. When used in this fashion, they are referred to as functional pads. Anti-pads are the clearance holes in the plane layers allowing the via barrel to pass through them without shorting.
The via portion is the length of the barrel connecting one signal layer to another. It is often referred to as the through via since it is part of the signal net. The stub portion is the rest of the barrel extending to the outer layer of the PCB. In high-speed designs, a good rule of thumb to remember is that a via stub should be less than 300mils/BR in length; where BR is the bit rate in Gb/s.
Building a Simple Scalable Circuit Model:
On close examination of Figure 2, a differential via structure can be represented by a twin-rod transmission line geometry with excess capacitance (shown in red) distributed over its entire length. The smaller the anti-pad diameter, the greater the excess capacitance. This ultimately results in lower via impedance, causing higher reflections.
In all high-speed serial link designs, it is common practice to remove all non-functional pads and to maximize the anti-pad clearance as much as practically possible. Oval anti-pads are often used in this regard to further mitigate excess via capacitance.
Figure 3 illustrates the equivalent circuit for a differential via that could be used in a channel topology simulation. Here it is modeled with Agilent ADS software using a coupled line transmission line model for each section. This equivalent circuit model can be scaled for any combination of layer transitions and integrated in any channel simulation scenario.
Since the cross-section of the via is constant throughout its length, the differential impedance of all sections of the via are the same. We only need to know the physical length of each segment and the effective dielectric constant (Dkeff) to get the time delay of each segment.
When driven differentially, the odd-mode parameters of each via are of major importance. Since the even-mode parameters have no impact on differential performance, both odd and even-mode parameters are set to the same values in the model.
The challenge then is to calculate the odd mode impedance (Zodd), representing the individual via impedance (Zvia), of a differential via structure and the effective dielectric constant (Dkeff) based on its geometry. Simple equations are used to determine these parameters.
Developing the Equations:
Anti-pads can vary in size and shape. They can be anything from round, to oval around each via, or even a large oval surrounding both vias as illustrated in Figure 4. Square, or rectangular variations (not shown) are similar.
Referring back to Figure 2, we see the structure of each via looks a lot like two coaxial transmission lines with the inner layer reference planes acting like a shield. Electrostatically this is a good approximation, but because the shield is not continuous, the magnetic fields are not contained like they are in a coaxial structure. Instead they behave more like magnetic fields around a twin-rod structure.
So here lies the secret in modeling a differential via. We take the best of both geometries to calculate the odd-mode impedance representing Zvia.
For inductance, we will use the odd-mode inductance formula from the twin-rod transmission line geometry to calculate Lvia :
Referring to Figure 4, we then calculate the odd-mode capacitance for Cvia derived from an approximate formula for an elliptic coaxial structure developed by M.A.R. Gunston in his book, “Microwave Transmission Line Impedance Data” . In the original formula, both shield (W’+b) and inner conductor (w+t) are elliptical in shape and are dimensioned as shown. When the anti-pads are circular, then ln[(W’+b) /(w+t)] reduces to just ln[b/t)]; which is the denominator in the Ccoax equation. If we use Gunston’s approximation to calculate Cvia, then the equation becomes:
Since conventional FR4 type laminates are fabricated with a weave of glass fiber yarns and resin, they are anisotropic in nature. Because of this, the dielectric constant value depends on the direction of the electric fields. In a multi-layer PCB, there are effectively two directions of electric fields.
The one we are most familiar with has the electric fields perpendicular to the surface of the PCB; as is the case of stripline shown here in Figure 5. The dielectric constant, designated as Dkz in this case, is normally the bulk value of the dielectric specified by the laminate manufacturer’s data sheet.
The other case has the electric fields running parallel to the surface of the PCB, as is the case when a signal propagates through a differential via structure. In this situation, the dielectric constant, designated as Dkxy, can be15-20% higher than Dkz .
Therefore, assuming a nominal 18% anisotropic factor, Dkxy = 1.18(Dkz)
Now that we have defined Lvia, Cvia and Dkavg, Zvia can be estimated using the following equation:
But we are not finished yet. We still need to determine the effective dielectric constant (Dkeff) in order to accurately model the delay through the via and stub portion. Without the correct value, the quarter-wave resonant nulls in the insertion loss plot, due to the stub length, cannot be accurately predicted. The value for Dkeff is determined based on how much the via’s odd-mode impedance is decreased due to the distributed capacitive loading of the anti-pads.
To help us with this task, we start with the twin-rod formula. The odd-mode impedance (Zodd) is half the differential impedance (Ztwin), and is expressed as:
By substituting Equation 1 for Zodd into the equation above, and solving for Dkeff we eventually come up with the following equation:
Validating the Model:
A simple 26 layer test vehicle was fabricated to compare the accuracy of the differential via circuit model to real vias. It consisted of two differential via pairs separated by 6 inches of 100 Ohm stripline differential pairs. Three sample via structures representing long, medium and short via stubs, as summarized in Figure 6, were measured using an Agilent N5230A VNA.
The differential vias had the following common parameters:
Via drill diameter; D = 28 mils
Center to center pitch; s = 59 mils
Oval anti-pads= 53 mils x 73 mils
Dk of the laminate = 3.65
Anisotropy in Dkxy = 18%
Zvia = Zstub = 31.7 Ohms (per Equation 1)
Dkeff = 6.8 (per Equation 2)
Agilent ADS software was used to model and facilitate simulation correlation of the measured data as captured in Figure 7. This simple model accounts for the discontinuity of the long through section and the long stub section. The top half is the measured channel using an S-parameter file. The bottom half is a circuit model of the channel. Since the probes were not calibrated out, they are part of the device under test. The balun transformers are used to facilitate the display of the S-parameter and TDR results.
The comparison between the measured and simulated results of the insertion loss and TDR response for the three via stub cases using this simple approximation methodology is summarized in Figure 8. The insertion loss plots, in the frequency domain, are shown on the left, while the TDR plots are shown on the right.
The resonant nulls in the SDD21 plots are due to the stub lengths. As you can see, the longer the stub, the lower the resonant frequency null. If this null happens at the Nyquist frequency of the bit rate, the eye will be totally closed. This is why we back-drill them out after the board has been fabricated.
The simulation correlation is excellent up to about 12 GHz. The TDR plots show excellent impedance matching and delay for all three cases, while the simulated stub resonant frequencies match the measured frequencies very well. As you can see, these simple approximations for Dkeff and Zvia are perfectly adequate in providing a quick and accurate circuit model for differential through hole vias typically used in backplane applications.
As illustrated, a simple twin-rod model (Figure 2) is used as the basis for a practical differential via circuit modeling methodology. By using Equation 1 and Equation 2, you can quickly determine the odd-mode impedance and effective dielectric constant needed for the circuit model.
Of course, you should use this methodology first as a rough starting point to quickly estimate the performance of your differential via design. If your worst case topology simulations show the performance is marginal, then it is worth while to invest the time and money to develop a 3D full wave model to perform a more accurate analysis.
On the other hand, if you find this approximation shows the vias have little impact on the channel performance, it may be of greater value for you to invest your time and money in resolving other critical issues with your design.
Try it the next time you are losing sleep over your design challenges.
For more Information:
If you liked this design note and want to learn more, or get more details on this innovative via modeling methodology, you can visit my web site, LAMSIM Enterprises.com , and download a copy of the white paper I wrote along with Eric Bogatin and Yazi Cao titled, “Method of Modeling Differential Vias” .
While you are there, feel free to investigate my other white papers and publications.
If you would like more information on our signal integrity and backplane services, or how we can help you achieve your next high-speed design challenge, email us at: email@example.com.
In my last Design Note on coaxial transmission geometry, I mentioned it was one of three unique cross-sectional geometries that have exact equations for inductance and capacitance. The other two are twin-rod and rod-over-plane. All three relationships assume the dielectric material is homogeneous and completely fills the space when there are electric fields.
A common application for twin-rod geometry is twin-lead ribbon cable; once used for RF transmission between antenna and TV sets. With the popularity of cable and satellite TV over the years, twin-lead has given way to coaxial cable due to its superior noise rejection and shielding effectiveness.
If we look at Figure1, we can see the electromagnetic field relationship of a twin-rod geometry when it is driven differentially. As current propagates along one rod, an equal and opposite current flows in the opposite direction along the other.
The right half of Figure 1 shows the magnetic-field loops and direction of rotation around each rod. Only one loop is shown for clarity, but the number of loops is a function of the amount of current and the length of the rods. The counter-rotating loops of current forms a virtual return at exactly one half of the space between the two rods. We call this a virtual return because if we were to put a conducting plane in the same position, the electromagnetic fields would look exactly the same.
Figure 1 Twin-rod geometry showing electromagnetic field relationship.
In his book, “Signal Integrity Simplified”, Eric Bogatin defines the loop inductance as, “the total number of field line loops around a conductor per amp of current”, and the loop self-inductance as, “the total number of field line loops around a conductor per amp of current in the same loop” . Applying these definitions to the figure, the loop inductance (L) is the inductance between the two rods, and the loop self-inductance (L/2) is the loop self inductance to the virtual return plane; equal to one half the loop inductance.
Likewise, the left half of Figure 1 shows the electric field with a capacitance (C) between the two rods, and twice the capacitance (2C) from each rod to the virtual return plane.
The relationships between capacitance, inductance and impedance of a twin-rod geometry are described by the following equations:
Ctwin = Capacitance between twin-rods – F
Ltwin = Loop Inductance between twin-rods – H
Zdiff = Differential impedance of twin-rods – Ω
Dk = Dielectric constant of material
Len = Length of the rods – inches
r = Radius of the rods – inches
s = Space between the rods – inches
Because the electro-magnetic fields create a virtual return plane at exactly one half of the spacing between the rods, each rod behaves like a single rod-over-plane geometry as illustrated in Figure 2.
Figure 2 Electromagnetic fields comparison of Twin-rod (left) vs. Rod-over-plane (right) geometries.
Whenever an AC current carrying conductor is in close proximity to a conducting plane, as is the case for rod-over-plane, some of the magnetic-field lines penetrate it. When the current changes direction, the associated magnetic-field lines also change direction; causing small voltages to be induced in the plane. These voltages create eddy currents, which in turn produce their own magnetic-fields.
Eddy current-induced magnetic-field line patterns look exactly like magnetic-field lines from an imaginary current below the plane; located the same distance as the real current above the plane. This imaginary current is called an image current, and has the same magnitude as the real current; except in the opposite direction . The image current creates associated image magnetic-field lines in the opposite direction of the real field lines. As a result, the real magnetic-field lines are compressed between the rod and the plane. Since the rod-over-plane geometry has only one rod, the loop inductance is the same as the loop self-inductance.
For a twin-rod geometry, the odd mode capacitance is the capacitance of each rod to virtual return plane and is equal to twice the capacitance between rods.
Likewise, the odd mode inductance is the inductance of each rod to virtual return plane and equal to one half the inductance between rods.
The odd mode impedance of each rod is half of the differential impedance, and is equivalent to the rod-over-plane impedance.
 “Signal Integrity Simplified”, Eric Bogatin